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Pi Firmware: Updated pinout to quad starts at gpio0, sp_clken now a global input 

Change-Id: Ie417316e9d444f8244301f666ebea461d78c6920
issue_1022
David Banks 2018-06-08 07:35:39 +01:00
rodzic 5cf77dc03c
commit bf83a84ff2
2 zmienionych plików z 28 dodań i 28 usunięć
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12
src/defs.h
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@ -102,8 +102,8 @@
#endif // __ASSEMBLER__
// Quad Pixel input on GPIOs 2..13
#define PIXEL_BASE (2)
// Quad Pixel input on GPIOs 0..11
#define PIXEL_BASE (0)
#define SW1_PIN (16) // active low
#define SW2_PIN (26) // active low
@ -112,12 +112,12 @@
#define CSYNC_PIN (18)
#define MODE7_PIN (22)
#define GPCLK_PIN (21)
#define SP_CLK_PIN (23)
#define SP_CLKEN_PIN (1)
#define SP_DATA_PIN (20)
#define SP_CLK_PIN (20)
#define SP_CLKEN_PIN (13)
#define SP_DATA_PIN (23)
#define ELK_PIN (24)
#define LINK_PIN (25)
#define SPARE_PIN (0)
#define SPARE_PIN (12)
#define CAL_PIN SW1_PIN

44
src/rgb_to_fb.S
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@ -229,43 +229,43 @@ process_chars_loop:
// Wait for 0-1 edge on PSYNC
WAIT_FOR_PSYNC_1
// Pixel 0 in GPIO 4.. 2 -> 7.. 4
// Pixel 1 in GPIO 7.. 5 -> 3.. 0
// Pixel 2 in GPIO 10.. 8 -> 15..12
// Pixel 3 in GPIO 13..11 -> 11.. 8
// Pixel 0 in GPIO 2..0 -> 7.. 4
// Pixel 1 in GPIO 5..3 -> 3.. 0
// Pixel 2 in GPIO 8..6 -> 15..12
// Pixel 3 in GPIO 11..9 -> 11.. 8
and r9, r8, #(7 << PIXEL_BASE)
orr r10, r10, r9, lsl #2
and r9, r8, #(7 << (PIXEL_BASE + 3))
orr r10, r10, r9, lsr #5
and r9, r8, #(7 << (PIXEL_BASE + 6))
orr r10, r10, r9, lsl #4
and r9, r8, #(7 << (PIXEL_BASE + 9))
and r9, r8, #(7 << (PIXEL_BASE + 3))
orr r10, r10, r9, lsr #3
and r9, r8, #(7 << (PIXEL_BASE + 6))
orr r10, r10, r9, lsl #6
and r9, r8, #(7 << (PIXEL_BASE + 9))
orr r10, r10, r9, lsr #1
// Wait for 1-0 edge on PSYNC
WAIT_FOR_PSYNC_0
// Pixel 4 in GPIO 4.. 2 -> 23..20
// Pixel 5 in GPIO 7.. 5 -> 19..16
// Pixel 6 in GPIO 10.. 8 -> 31..28
// Pixel 7 in GPIO 13..11 -> 27..24
// Pixel 4 in GPIO 2..0 -> 23..20
// Pixel 5 in GPIO 5..3 -> 19..16
// Pixel 6 in GPIO 8..6 -> 31..28
// Pixel 7 in GPIO 11..9 -> 27..24
and r9, r8, #(7 << PIXEL_BASE)
orr r10, r10, r9, lsl #18
and r9, r8, #(7 << (PIXEL_BASE + 3))
orr r10, r10, r9, lsl #11
and r9, r8, #(7 << (PIXEL_BASE + 6))
orr r10, r10, r9, lsl #20
and r9, r8, #(7 << (PIXEL_BASE + 9))
and r9, r8, #(7 << (PIXEL_BASE + 3))
orr r10, r10, r9, lsl #13
and r9, r8, #(7 << (PIXEL_BASE + 6))
orr r10, r10, r9, lsl #22
and r9, r8, #(7 << (PIXEL_BASE + 9))
orr r10, r10, r9, lsl #15
// Line double always in Modes 0-6 regardless of interlace
// On the multi core Pi this introduces stalling artefacts
#ifndef HAS_MULTICORE