diff --git a/src/capture_line_fast_4bpp_8bpp.S b/src/capture_line_fast_4bpp_8bpp.S index b622ec80..8cf86c4b 100644 --- a/src/capture_line_fast_4bpp_8bpp.S +++ b/src/capture_line_fast_4bpp_8bpp.S @@ -25,7 +25,7 @@ capture_line_fast_4bpp: push {lr} SETUP_VSYNC_DEBUG_R11 - SKIP_PSYNC_NO_H_SCROLL + SKIP_PSYNC_NO_OLD_CPLD loop: WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8 CAPTURE_LOW_BITS_NORMAL r11 // input in r8 @@ -61,7 +61,7 @@ preload_capture_line_fast: capture_line_fast_8bpp: push {lr} SETUP_VSYNC_DEBUG_R11_R12 - SKIP_PSYNC_NO_H_SCROLL + SKIP_PSYNC_NO_OLD_CPLD loop_8bpp: WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8 CAPTURE_BITS_8BPP_NORMAL r11 r5 // input in r8 diff --git a/src/capture_line_fast_eightbits_8bpp_16bpp.S b/src/capture_line_fast_eightbits_8bpp_16bpp.S index db0450ab..84e1c3f4 100644 --- a/src/capture_line_fast_eightbits_8bpp_16bpp.S +++ b/src/capture_line_fast_eightbits_8bpp_16bpp.S @@ -30,7 +30,7 @@ capture_line_fast_eightbits_8bpp: push {lr} SETUP_VSYNC_DEBUG_R11_R12 - SKIP_PSYNC_NO_H_SCROLL + SKIP_PSYNC_NO_OLD_CPLD SETUP_EIGHT_BITS_MASK_R14 loop_8bpp: WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8 @@ -90,7 +90,7 @@ preload_capture_line_fast_eightbits_8bpp: capture_line_fast_eightbits_16bpp: push {lr} SETUP_VSYNC_DEBUG_16BPP_R11_R12 - SKIP_PSYNC_NO_H_SCROLL + SKIP_PSYNC_NO_OLD_CPLD SETUP_TWELVE_BITS_MASK_R14 loop_16bpp: WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8 diff --git a/src/capture_line_fast_sixbits_8bpp_16bpp.S b/src/capture_line_fast_sixbits_8bpp_16bpp.S index 372bc529..1fc236c4 100644 --- a/src/capture_line_fast_sixbits_8bpp_16bpp.S +++ b/src/capture_line_fast_sixbits_8bpp_16bpp.S @@ -28,7 +28,7 @@ capture_line_fast_sixbits_4bpp: push {lr} SETUP_VSYNC_DEBUG_R11 - SKIP_PSYNC_NO_H_SCROLL + SKIP_PSYNC_NO_OLD_CPLD loop: WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8 CAPTURE_0_BITS_WIDE r11 // input in r8 @@ -70,7 +70,7 @@ preload_capture_line_fast_sixbits: capture_line_fast_sixbits_8bpp: push {lr} SETUP_VSYNC_DEBUG_R11_R12 - SKIP_PSYNC_NO_H_SCROLL + SKIP_PSYNC_NO_OLD_CPLD loop_8bpp: WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8 CAPTURE_LOW_BITS_8BPP_WIDE r11 // input in r8 @@ -113,7 +113,7 @@ preload_capture_line_fast_sixbits_8bpp: capture_line_fast_sixbits_16bpp: push {lr} SETUP_VSYNC_DEBUG_16BPP_R11_R12 - SKIP_PSYNC_NO_H_SCROLL + SKIP_PSYNC_NO_OLD_CPLD SETUP_TWELVE_BITS_MASK_R14 loop_16bpp: WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8 diff --git a/src/macros.S b/src/macros.S index cf5026c4..752c70aa 100644 --- a/src/macros.S +++ b/src/macros.S @@ -212,7 +212,10 @@ skip_psync_loop\@: WAIT_FOR_CSYNC_0_FAST_SKIP_HSYNC READ_CYCLE_COUNTER r10 push {r10} - bic r3, r3, #PSYNC_MASK // wait for zero after CSYNC + bic r3, r3, #PSYNC_MASK // wait for zero after CSYNC + mov r6, r9, lsr #16 //HSYNC_SCROLL_HI + bic r9, r9, #0xff000000 + bic r9, r9, #0x00ff0000 //HSYNC_SCROLL_LO // Wait for the end of hsync WAIT_FOR_CSYNC_1_FAST READ_CYCLE_COUNTER r14 @@ -229,11 +232,9 @@ skip_psync_loop\@: // new CPLD code only (not called from CPLD v1 & v2) mov r8, r7 - cmp r10, r9, lsr #16 //HSYNC_SCROLL_HI + cmp r10, r6 //HSYNC_SCROLL_HI addlt r8, r8, #1 orrgt r3, r3, #BIT_INHIBIT_MODE_DETECT - bic r9, r9, #0xff000000 - bic r9, r9, #0x00ff0000 cmp r10, r9 //HSYNC_SCROLL_LO addlt r8, r8, #1 orrlt r3, r3, #BIT_INHIBIT_MODE_DETECT @@ -246,18 +247,18 @@ skip_psync_loop_no_old\@: bne skip_psync_loop_no_old\@ .endm -.macro SKIP_PSYNC_NO_H_SCROLL - // only called if in fast mode (both 3 & 6 bpp) - fast mode never called from old CPLDs v1 & v2 - WAIT_FOR_CSYNC_0_FAST_SKIP_HSYNC - READ_CYCLE_COUNTER r10 - push {r10} - bic r3, r3, #PSYNC_MASK // wait for zero after CSYNC - WAIT_FOR_CSYNC_1_FAST -skip_psync_loop_no_h_scroll\@: - WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync - subs r7, r7, #1 - bne skip_psync_loop_no_h_scroll\@ -.endm +//.macro SKIP_PSYNC_NO_H_SCROLL +// // only called if in fast mode (both 3 & 6 bpp) - fast mode never called from old CPLDs v1 & v2 +// WAIT_FOR_CSYNC_0_FAST_SKIP_HSYNC +// READ_CYCLE_COUNTER r10 +// push {r10} +// bic r3, r3, #PSYNC_MASK // wait for zero after CSYNC +// WAIT_FOR_CSYNC_1_FAST +//skip_psync_loop_no_h_scroll\@: +// WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync +// subs r7, r7, #1 +// bne skip_psync_loop_no_h_scroll\@ +//.endm #ifdef USE_MULTICORE .macro CAPTURE_FROM_CORE1 diff --git a/src/rgb_to_fb.S b/src/rgb_to_fb.S index 9a92de31..a2993bcc 100644 --- a/src/rgb_to_fb.S +++ b/src/rgb_to_fb.S @@ -244,8 +244,8 @@ skip_double_check: tsteq r3, #BIT_OLD_FIRMWARE_SUPPORT // if version < 3 have to do the second PSYNC read movne r7, r10 // if any are enabled make index point to non-fast versions - tst r3, #BIT_NO_H_SCROLL // H scrolling enbled? - moveq r7, r10 // make index point to non-fast versions(fast versions don't support fine H scrolling) + // tst r3, #BIT_NO_H_SCROLL // H scrolling enbled? + // moveq r7, r10 // make index point to non-fast versions(fast versions don't support fine H scrolling) ldr r9, param_capture_line ldr r8, [r9, r7, lsl #2] diff --git a/src/rgb_to_hdmi.c b/src/rgb_to_hdmi.c index 494392f4..da36af57 100644 --- a/src/rgb_to_hdmi.c +++ b/src/rgb_to_hdmi.c @@ -1423,8 +1423,10 @@ int cpld_version_id = 0; static void cpld_init() { // have to set mux to 0 to allow analog detection to work // so clock out 32 bits of 0 into register chain as later CPLDs have mux as a register bit - for (int i = 0; i < 32; i++) { - RPI_SetGpioValue(SP_DATA_PIN, 0); + + int sp = 0b00011000000000000000000000; //sets the rate bits to 12bit capture for testing simple mode with amiga + for (int i = 0; i < 26; i++) { + RPI_SetGpioValue(SP_DATA_PIN, sp & 1); delay_in_arm_cycles_cpu_adjust(250); RPI_SetGpioValue(SP_CLKEN_PIN, 1); delay_in_arm_cycles_cpu_adjust(250); @@ -1434,6 +1436,7 @@ static void cpld_init() { delay_in_arm_cycles_cpu_adjust(250); RPI_SetGpioValue(SP_CLKEN_PIN, 0); delay_in_arm_cycles_cpu_adjust(250); + sp >>= 1; } RPI_SetGpioValue(MUX_PIN, 0); // have to set mux to 0 to allow analog detection to work (GPIO on older cplds) // Assert the active low version pin