Update RGB CPLD to V93 with Apple IIGS autoswitch detection

vhdl_RGB_12bit/6-12_BIT_RGB_CPLD_v85_tempImpact.svf

@@ -1,10 +0,0 @@
-// Created using Xilinx Cse Software [ISE - 14.7]
-// Date: Thu Nov 05 15:54:31 2020
-
-TRST OFF;
-ENDIR IDLE;
-ENDDR IDLE;
-STATE RESET;
-STATE IDLE;
-FREQUENCY 1E6 HZ;
-FREQUENCY 1E6 HZ;

vhdl_RGB_12bit/RGBtoHDMI.vhdl

@@ -59,8 +59,8 @@ architecture Behavorial of RGBtoHDMI is
     --         3 = six bit CPLD (if required);
     --         4 = RGB CPLD (TTL)
     --         C = RGB CPLD (Analog)
-    constant VERSION_NUM_RGB_TTL    : std_logic_vector(11 downto 0) := x"492";
-    constant VERSION_NUM_RGB_ANALOG : std_logic_vector(11 downto 0) := x"C92";
+    constant VERSION_NUM_RGB_TTL    : std_logic_vector(11 downto 0) := x"493";
+    constant VERSION_NUM_RGB_ANALOG : std_logic_vector(11 downto 0) := x"C93";
 
     signal shift_R  : std_logic_vector(3 downto 0);
     signal shift_G  : std_logic_vector(3 downto 0);
@@ -133,6 +133,8 @@ architecture Behavorial of RGBtoHDMI is
     signal divider    : unsigned(2 downto 0);
     signal mux        : std_logic;
 
+    signal latched_vsync : std_logic;
+
 begin
     offset     <= sp_reg(3 downto 0);
     delay      <= unsigned(sp_reg(6 downto 4));
@@ -177,7 +179,6 @@ begin
         if rising_edge(clk) then
 
             -- synchronize CSYNC to the sampling clock
-            -- if link fitted sync is inverted. If +ve vsync connected to link & +ve hsync to S then generate -ve composite sync
             csync1 <= mux_sync xor invert;
 
             -- De-glitch CSYNC
@@ -197,14 +198,17 @@ begin
 
             -- Counter is used to find sampling point for first pixel
             last <= csync2;
+
             -- reset counter on the rising edge of csync
             if last = '0' and csync2 = '1' then
-                    if rateswitch = '1' then
-                        counter(8 downto 4) <= "10" & delay; -- 3 low bits of delay with 1bpp so 10xxx
-                    else
-                        counter(8 downto 4) <= "11" & delay; -- only 2 low bits of delay used unless 1bpp so 110xx
-                    end if;
+                latched_vsync <= '0';
+                if rateswitch = '1' then
+                    counter(8 downto 4) <= "10" & delay; -- 3 low bits of delay with 1bpp so 10xxx
+                else
+                    counter(8 downto 4) <= "11" & delay; -- only 2 low bits of delay used unless 1bpp so 110xx
+                end if;
                 counter(3 downto 0) <= "0000";
+
             elsif divider = "000" then
                 if counter(3 downto 0) /= 2 then
                     if counter(counter'left) = '1' then
@@ -244,6 +248,14 @@ begin
                 sample_toggle <= not (sample_toggle);
             end if;
 
+            if sample = '1' then
+                if latched_vsync = '0' then
+                    latched_vsync <= vsync_I;
+                else
+                    latched_vsync <= latched_vsync;
+                end if;
+            end if;
+
             -- R Sample/shift register
             if sample = '1' then
                 if rate = "00" and rateswitch = '1' then
@@ -343,7 +355,7 @@ begin
                 quad(2)  <= shift_B(0);
                 quad(1)  <= shift_G(0);
                 quad(0)  <= shift_R(0);
-            end if;
+               end if;
 
             -- Output a skewed version of psync
             if version = '0' then
@@ -366,7 +378,7 @@ begin
         end if;
     end process;
 
-    csync <= csync2; -- output the registered version to save a macro-cell
+    csync <= csync2 when version = '1' else latched_vsync; -- output the registered version to save a macro-cell
 
     -- csync2 is cleaned but delayed so OR with csync1 to remove delay on trailing edge of sync pulse
     -- clamp not usable in 4 LEVEL mode (rate = 10) or 8/12 bit mode (rate = 11) so use as multiplex signal instead

vhdl_RGB_12bit/_impactbatch.log

@@ -0,0 +1,55 @@
+iMPACT Version: Oct 13 2013 10:22:21
+
+iMPACT log file Started on Sun Jun 27 03:40:41 2021
+
+Preference Table
+Name                 Setting             
+StartupClock         Auto_Correction     
+AutoSignature        False               
+KeepSVF              False               
+ConcurrentMode       False               
+UseHighz             False               
+ConfigOnFailure      Stop                
+UserLevel            Novice              
+MessageLevel         Detailed            
+svfUseTime           false               
+SpiByteSwap          Auto_Correction     
+AutoInfer            false               
+SvfPlayDisplayComments false               
+'1': Loading file 'C:\Github\RGBtoHDMI\vhdl_RGB_12bit\working\RGBtoHDMI.jed' ...
+done.
+INFO:iMPACT:1777 - 
+   Reading C:/Xilinx/14.7/ISE_DS/ISE/xc9500xl/data/xc9572xl.bsd...
+INFO:iMPACT:501 - '1': Added Device xc9572xl successfully.
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+Active mode is BS
+INFO:iMPACT - Digilent Plugin: Plugin Version: 2.4.4
+INFO:iMPACT - Digilent Plugin: no JTAG device was found.
+AutoDetecting cable. Please wait.
+*** WARNING ***: When port is set to auto detect mode, cable speed is set todefault 6 MHz regardless of explicit arguments supplied for setting the baudrates
+Connecting to cable (Usb Port - USB21).
+Checking cable driver.
+ Driver file xusb_xlp.sys found.
+ Driver version: src=1029, dest=1029.
+ Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS14:14:44, version = 1021.
+Cable connection failed.
+Connecting to cable (Parallel Port - LPT1).
+Checking cable driver.
+ Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS14:14:44, version = 1021.
+ LPT base address = 0378h.
+ ECP base address = FFFFFFFFh.
+Cable connection failed.
+Connecting to cable (Parallel Port - LPT2).
+Checking cable driver.
+ Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS14:14:44, version = 1021.
+Cable connection failed.
+Connecting to cable (Parallel Port - LPT3).
+Checking cable driver.
+ Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS14:14:44, version = 1021.
+Cable connection failed.
+Connecting to cable (Parallel Port - LPT4).
+Checking cable driver.
+ Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS14:14:44, version = 1021.
+Cable connection failed.
+Cable autodetection failed.

vhdl_RGB_12bit/iseconfig/RGBtoHDMI.projectmgr

@@ -21,6 +21,7 @@
       <ClosedNodes>
          <ClosedNodesVersion>1</ClosedNodesVersion>
          <ClosedNode>Design Utilities</ClosedNode>
+         <ClosedNode>Implement Design/Optional Implementation Tools</ClosedNode>
          <ClosedNode>Implement Design/Optional Implementation Tools/Generate Timing</ClosedNode>
          <ClosedNode>Implement Design/Synthesize - XST</ClosedNode>
          <ClosedNode>User Constraints</ClosedNode>

vhdl_RGB_12bit/iseconfig/RGBtoHDMI.xreport

@@ -1,9 +1,9 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2020-11-05T16:04:40</DateModified>
+  <DateModified>2021-06-27T21:19:53</DateModified>
   <ModuleName>RGBtoHDMI</ModuleName>
-  <SummaryTimeStamp>2020-11-05T15:49:22</SummaryTimeStamp>
+  <SummaryTimeStamp>2021-06-27T18:39:16</SummaryTimeStamp>
   <SavedFilePath>C:/Github/RGBtoHDMI/vhdl_RGB_12bit/iseconfig/RGBtoHDMI.xreport</SavedFilePath>
   <ImplementationReportsDirectory>C:/Github/RGBtoHDMI/vhdl_RGB_12bit/working\</ImplementationReportsDirectory>
   <DateInitialized>2019-12-05T17:57:48</DateInitialized>

vhdl_RGB_12bit/working/RGBtoHDMI_summary.html

@@ -72,5 +72,5 @@
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 11/05/2020 - 16:04:41</center>
+<br><center><b>Date Generated:</b> 06/27/2021 - 21:19:53</center>
 </BODY></HTML>