kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Update vhdl
IanSB
rodzic
502e4a0cb0
commit
942aac9518
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@ -6,7 +6,7 @@ NET "sp_clk" BUFG=CLK;
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# 96MHz clock domain
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NET "clk" TNM_NET = clk_period_grp_1;
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TIMESPEC TS_clk_period_1 = PERIOD "clk_period_grp_1" 10.4ns HIGH;
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TIMESPEC TS_clk_period_1 = PERIOD "clk_period_grp_1" 5.2ns HIGH;
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# 10MHz clock domain
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#NET "sp_clk" TNM_NET = clk_period_grp_2;
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@ -14,23 +14,25 @@ TIMESPEC TS_clk_period_1 = PERIOD "clk_period_grp_1" 10.4ns HIGH;
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NET "clk" LOC = "P43"; # input gpio21 (gclk)
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NET "R0" LOC = "P32"; # input
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NET "G0" LOC = "P31"; # input
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NET "B0" LOC = "P30"; # input
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NET "R1" LOC = "P34"; # input
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NET "G1" LOC = "P36"; # input
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NET "B1" LOC = "P37"; # input
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NET "csync_in" LOC = "P23"; # input
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NET "R3_I" LOC = "P32"; # input
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NET "G3_I" LOC = "P31"; # input
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NET "B3_I" LOC = "P30"; # input
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NET "R2_I" LOC = "P34"; # input
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NET "G2_I" LOC = "P36"; # input
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NET "B2_I" LOC = "P37"; # input
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NET "R1_I" LOC = "P39"; # input (was gpio26)
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NET "G1_I" LOC = "P40"; # input (was gpio19)
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NET "B1_I" LOC = "P38"; # input (was gpio16)
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NET "R0_I" LOC = "P21"; # input (was gpio27)
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NET "G0_I" LOC = "P42"; # input (was gpio25)
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NET "B0_I" LOC = "P18"; # input (was gpio24)
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NET "csync_I" LOC = "P23"; # input
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NET "version" LOC = "P33"; # input gpio18 (gsr)
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NET "SW1" LOC = "P38"; # input gpio16 (connects to sw1)
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NET "SW2" LOC = "P39"; # input gpio26 (connects to sw2)
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NET "SW3" LOC = "P40"; # input gpio19 (connects to sw3)
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NET "vsync_in" LOC = "P41"; # input (connects to vsync)
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NET "vsync_I" LOC = "P41"; # input (connects to vsync)
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NET "analog" LOC = "P19"; # input gpio22
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NET "mode7_in" LOC = "P42"; # input gpio25 (connects to LED2, driven from Pi)
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NET "mux" LOC = "P18"; # input gpio24
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NET "sp_clk" LOC = "P44"; # input gpio20 (gclk)
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NET "sp_data" LOC = "P7"; # input gpio0 (input only)
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NET "sp_clken" LOC = "P6"; # input gpio1 (input only)
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@ -51,8 +53,6 @@ NET "quad(11)" LOC = "P1"; # output gpio13
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NET "psync" LOC = "P22"; # output gpio17
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NET "csync" LOC = "P20"; # output gpio23
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NET "LED1" LOC = "P21"; # input gpio27 (connects to LED1, driven from Pi)
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NET "quad(0)" SLOW;
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NET "quad(1)" SLOW;
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NET "quad(2)" SLOW;
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@ -1,5 +1,5 @@
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----------------------------------------------------------------------------------
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-- Engineer: David Banks
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-- Engineer: David Banks & Ian Bradbury
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--
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-- Create Date: 15/7/2018
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-- Module Name: RGBtoHDMI CPLD
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@ -19,20 +19,25 @@ entity RGBtoHDMI is
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);
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Port (
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-- From RGB Connector
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R0: in std_logic;
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G0: in std_logic;
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B0: in std_logic;
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R1: in std_logic;
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G1: in std_logic;
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B1: in std_logic;
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csync_in: in std_logic;
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vsync_in: in std_logic;
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R3_I: in std_logic;
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G3_I: in std_logic;
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B3_I: in std_logic;
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R2_I: in std_logic;
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G2_I: in std_logic;
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B2_I: in std_logic;
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R1_I: in std_logic;
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G1_I: in std_logic;
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B1_I: in std_logic;
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R0_I: in std_logic;
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G0_I: in std_logic;
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B0_I: in std_logic;
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csync_I: in std_logic;
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vsync_I: in std_logic;
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analog: inout std_logic;
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-- From Pi
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clk: in std_logic;
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mode7_in: in std_logic;
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mux: in std_logic;
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sp_clk: in std_logic;
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sp_clken: in std_logic;
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sp_data: in std_logic;
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@ -43,19 +48,12 @@ entity RGBtoHDMI is
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csync: out std_logic;
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-- User interface
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version: in std_logic;
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SW1: in std_logic;
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SW2: in std_logic;
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SW3: in std_logic;
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LED1: in std_logic -- allow it to be driven from the Pi
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version: in std_logic
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);
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end RGBtoHDMI;
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architecture Behavorial of RGBtoHDMI is
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subtype counter_type is unsigned(7 downto 0);
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-- Version number: Design_Major_Minor
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-- Design: 0 = BBC CPLD
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-- 1 = Alternative CPLD
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@ -63,12 +61,10 @@ architecture Behavorial of RGBtoHDMI is
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-- 3 = six bit CPLD (if required);
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-- 4 = RGB CPLD (TTL)
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-- C = RGB CPLD (Analog)
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constant VERSION_NUM_BBC : std_logic_vector(11 downto 0) := x"066";
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constant VERSION_NUM_RGB_TTL : std_logic_vector(11 downto 0) := x"477";
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constant VERSION_NUM_RGB_ANALOG : std_logic_vector(11 downto 0) := x"C77";
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-- Sampling points
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constant INIT_SAMPLING_POINTS : std_logic_vector(23 downto 0) := "000000011011011011011011";
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constant VERSION_NUM_BBC : std_logic_vector(11 downto 0) := x"067";
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constant VERSION_NUM_RGB_TTL : std_logic_vector(11 downto 0) := x"478";
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constant VERSION_NUM_RGB_ANALOG : std_logic_vector(11 downto 0) := x"C78";
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signal shift_R : std_logic_vector(3 downto 0);
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signal shift_G : std_logic_vector(3 downto 0);
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@ -91,34 +87,11 @@ architecture Behavorial of RGBtoHDMI is
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-- 4. Handles double buffering of alternative quad pixels (bit 5)
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--
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-- At the moment we don't count pixels with the line, the Pi does that
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subtype counter_type is unsigned(7 downto 0);
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signal counter : counter_type;
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-- Sample point register;
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--
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-- In Mode 7 each pixel lasts 8 clocks (96MHz / 12MHz). The original
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-- pixel clock is a regenerated 6Mhz clock, and both edges are used.
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-- Due to the way it is generated, there are three distinct phases,
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-- each with different rising/falling edge speeds, hence six sampling
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-- points are used.
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--
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-- In Modes 0..6 each pixel lasts 6 clocks (96MHz / 16MHz). The original
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-- pixel clock is a clean 16Mhz clock, so only one sample point is needed.
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-- To achieve this, all six values are set to be the same. This minimises
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-- the logic in the CPLD.
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signal sp_reg : std_logic_vector(23 downto 0) := INIT_SAMPLING_POINTS;
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-- Break out of sp_reg
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signal invert : std_logic;
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signal rate : std_logic_vector(1 downto 0);
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signal delay : unsigned(1 downto 0);
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signal half : std_logic;
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signal offset_A : std_logic_vector(2 downto 0);
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signal offset_B : std_logic_vector(2 downto 0);
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signal offset_C : std_logic_vector(2 downto 0);
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signal offset_D : std_logic_vector(2 downto 0);
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signal offset_E : std_logic_vector(2 downto 0);
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signal offset_F : std_logic_vector(2 downto 0);
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-- Pipelined offset mux output
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signal offset : std_logic_vector(2 downto 0);
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@ -133,9 +106,8 @@ architecture Behavorial of RGBtoHDMI is
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-- RGB Input Mux
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signal old_mux : std_logic;
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signal mode7 : std_logic;
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signal mux_sync : std_logic;
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signal mux_sync : std_logic;
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signal R : std_logic;
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signal G : std_logic;
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signal B : std_logic;
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@ -143,12 +115,42 @@ architecture Behavorial of RGBtoHDMI is
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signal clamp_int : std_logic;
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signal clamp_enable : std_logic;
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begin
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old_mux <= mux when not(SupportAnalog) else '0';
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-- Sample point register;
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--
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-- In Mode 7 each pixel lasts 8 clocks (96MHz / 12MHz). The original
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-- pixel clock is a regenerated 6Mhz clock, and both edges are used.
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-- Due to the way it is generated, there are three distinct phases,
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-- each with different rising/falling edge speeds, hence six sampling
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-- points are used.
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--
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-- In Modes 0..6 each pixel lasts 6 clocks (96MHz / 16MHz). The original
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-- pixel clock is a clean 16Mhz clock, so only one sample point is needed.
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-- To achieve this, all six values are set to be the same. This minimises
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-- the logic in the CPLD.
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R <= R1 when old_mux = '1' else R0;
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G <= G1 when old_mux = '1' else G0;
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B <= B1 when old_mux = '1' else B0;
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-- Sampling points
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constant INIT_SAMPLING_POINTS : std_logic_vector(23 downto 0) := "000000011011011011011011";
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signal sp_reg : std_logic_vector(23 downto 0) := INIT_SAMPLING_POINTS;
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-- Break out of sp_reg
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signal offset_A : std_logic_vector(2 downto 0);
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signal offset_B : std_logic_vector(2 downto 0);
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signal offset_C : std_logic_vector(2 downto 0);
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signal offset_D : std_logic_vector(2 downto 0);
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signal offset_E : std_logic_vector(2 downto 0);
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signal offset_F : std_logic_vector(2 downto 0);
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signal half : std_logic;
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signal delay : unsigned(1 downto 0);
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signal rate : std_logic_vector(1 downto 0);
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signal divider : std_logic;
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begin
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old_mux <= B0_I when not(SupportAnalog) else '0'; -- B0_I used to be mux_in from Pi GPIO
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R <= R2_I when old_mux = '1' else R3_I;
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G <= G2_I when old_mux = '1' else G3_I;
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B <= B2_I when old_mux = '1' else B3_I;
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offset_A <= sp_reg(2 downto 0);
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offset_B <= sp_reg(5 downto 3);
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@ -159,8 +161,7 @@ begin
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half <= sp_reg(18);
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delay <= unsigned(sp_reg(20 downto 19));
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rate <= sp_reg(22 downto 21);
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invert <= sp_reg(23) when not(SupportAnalog) else '0';
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mode7 <= mode7_in when not(SupportAnalog) else sp_reg(23);
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divider <= sp_reg(23);
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-- Shift the bits in LSB first
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process(sp_clk)
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@ -177,8 +178,7 @@ begin
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if rising_edge(clk) then
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-- synchronize CSYNC to the sampling clock
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-- if link fitted sync is inverted. If +ve vsync connected to link & +ve hsync to S then generate -ve composite sync
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csync1 <= csync_in xor invert;
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csync1 <= csync_I;
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-- De-glitch CSYNC
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-- csync1 is the possibly glitchy input
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@ -201,24 +201,17 @@ begin
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if last = '0' and csync2 = '1' then
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if rate(1) = '1' then
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counter(7 downto 3) <= "10" & delay & "0";
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if half = '1' then
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counter(2 downto 0) <= "000";
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elsif mode7 = '1' then
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counter(2 downto 0) <= "100";
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else
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counter(2 downto 0) <= "011";
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end if;
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else
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counter(7 downto 3) <= "110" & delay;
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if half = '1' then
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counter(2 downto 0) <= "000";
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elsif mode7 = '1' then
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counter(2 downto 0) <= "100";
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else
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counter(2 downto 0) <= "011";
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end if;
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end if;
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elsif mode7 = '1' or counter(2 downto 0) /= 5 then
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if half = '1' then
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counter(2 downto 0) <= "000";
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elsif divider = '1' then
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counter(2 downto 0) <= "100";
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else
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counter(2 downto 0) <= "011";
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end if;
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elsif divider = '1' or counter(2 downto 0) /= 5 then
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if counter(counter'left) = '1' then
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counter <= counter + 1;
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else
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@ -238,7 +231,7 @@ begin
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else
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-- so index offset changes at the same time counter wraps 7->0
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-- so index offset changes at the same time counter wraps ->0
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if (mode7 = '0' and counter(2 downto 0) = 4) or (mode7 = '1' and counter(2 downto 0) = 6) then
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if (divider = '0' and counter(2 downto 0) = 4) or (divider = '1' and counter(2 downto 0) = 6) then
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case index is
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when "000" =>
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index <= "001";
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@ -281,37 +274,53 @@ begin
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-- R Sample/shift register
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if sample = '1' then
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if rate = "01" then
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shift_R <= R1 & R0 & shift_R(3 downto 2); -- double
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if rate = "01" and sp_data = '0' then
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shift_R <= R2_I & R3_I & shift_R(3 downto 2); -- 6 bpp
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elsif rate = "00" and sp_data = '1' then
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shift_R <= R1_I & G2_I & B3_I & B3_I; -- 9 bpp
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elsif rate /= "00" and sp_data = '1' then
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shift_R <= R1_I & G2_I & B3_I & B0_I; -- 12 bpp
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else
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shift_R <= R & shift_R(3 downto 1);
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shift_R <= R3_I & shift_R(3 downto 1); -- 3 bpp
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end if;
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end if;
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-- G Sample/shift register
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if sample = '1' then
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if rate = "01" then
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shift_G <= G1 & G0 & shift_G(3 downto 2); -- double
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if rate = "01" and sp_data = '0' then
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shift_G <= G2_I & G3_I & shift_G(3 downto 2); -- 6 bpp
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elsif rate = "00" and sp_data = '1' then
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shift_G <= R2_I & G3_I & G3_I & B1_I; -- 9 bpp
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elsif rate /= "00" and sp_data = '1' then
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shift_G <= R2_I & G3_I & G0_I & B1_I; -- 12 bpp
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else
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shift_G <= G & shift_G(3 downto 1);
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shift_G <= G3_I & shift_G(3 downto 1); -- 3 bpp
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end if;
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end if;
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-- B Sample/shift register
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if sample = '1' then
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if rate = "01" then
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shift_B <= B1 & B0 & shift_B(3 downto 2); -- double
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if rate = "01" and sp_data = '0' then
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shift_B <= B2_I & B3_I & shift_B(3 downto 2); -- 6 bpp
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elsif rate = "00" and sp_data = '1' then
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shift_B <= R3_I & R3_I & vsync_I & B2_I; -- 9 bpp with G1 on vsync_I
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elsif rate /= "00" and sp_data = '1' then
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shift_B <= R3_I & R0_I & G1_I & B2_I; -- 12 bpp
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else
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shift_B <= B & shift_B(3 downto 1);
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shift_B <= B3_I & shift_B(3 downto 1); -- 3 bpp
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end if;
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end if;
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-- Pipeline when to update the quad
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if counter(counter'left) = '0' and (
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(rate = "00" and counter(4 downto 0) = 0) or -- normal
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(rate = "01" and counter(3 downto 0) = 0) or -- double
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(rate = "10" and counter(5 downto 0) = 0) or -- subsample even
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(rate = "11" and counter(5 downto 0) = 32)) then -- subsample odd
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(rate = "00" and sp_data = '0' and counter(4 downto 0) = 0) or -- 3bpp
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(rate = "01" and sp_data = '0' and counter(3 downto 0) = 0) or -- 6bpp
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(rate = "00" and sp_data = '1' and counter(2 downto 0) = 0) or -- 9bpp
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(rate = "01" and sp_data = '1' and counter(2 downto 0) = 0) or -- 12bpp
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(rate = "10" and sp_data = '0' and counter(5 downto 0) = 0) or -- subsample even 3bpp
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(rate = "11" and sp_data = '0' and counter(5 downto 0) = 32) or -- subsample odd 3bpp
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(rate = "10" and sp_data = '1' and counter(3 downto 0) = 0) or -- subsample even 12bpp
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(rate = "11" and sp_data = '1' and counter(3 downto 0) = 8)) then -- subsample odd 12bpp
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-- toggle is asserted in cycle 1
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toggle <= '1';
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else
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@ -348,30 +357,32 @@ begin
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end if;
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-- Output a skewed version of psync
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if version = '0' then
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psync <= vsync_in;
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elsif counter(counter'left) = '1' then
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if counter(counter'left) = '1' then
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psync <= '0';
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elsif counter(3 downto 0) = 3 then -- comparing with N gives N-1 cycles of skew
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if rate = "00" then
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psync <= counter(5); -- normal
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elsif rate = "01" then
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psync <= counter(4); -- double
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elsif counter(5) = rate(0) then
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elsif counter(2 downto 0) = 2 then -- comparing with N gives N-1 cycles of skew
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if rate = "00" and sp_data = '0' then
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psync <= counter(5); -- 3bpp
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elsif rate = "01" and sp_data = '0' then
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psync <= counter(4); -- 6bpp
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elsif rate = "00" and sp_data = '1' then
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psync <= counter(3); -- 9bpp one edge for every pixel
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elsif rate = "01" and sp_data = '1' then
|
||||
psync <= counter(3); -- 12 bpp one edge for every pixel
|
||||
elsif sp_data = '0' and rate(0) = counter(5) then
|
||||
psync <= counter(6); -- subsample
|
||||
elsif sp_data = '1' and rate(0) = counter(3) then
|
||||
psync <= counter(4); -- subsample
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
csync <= csync2; -- output the registered version to save a macro-cell
|
||||
|
||||
analog_additions: if SupportAnalog generate
|
||||
-- csync2 is cleaned but delayed so OR with csync1 to remove delay on trailing edge of sync pulse
|
||||
-- spdata is overloaded as clamp on/off
|
||||
-- csync2 is cleaned but delayed so OR with csync1 to remove delay on trailing edge of sync pulse
|
||||
-- spdata is overloaded as clamp on/off
|
||||
clamp_int <= not(csync1 or csync2) and sp_data;
|
||||
|
||||
analog <= 'Z' when version = '0' else clamp_int;
|
||||
end generate;
|
||||
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue