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Atom CPLD: Clock pixel pipeline every cycle 

Change-Id: I2bd518340399117bdd089218e22496f536d228c5
pull/11/head
David Banks 2018-11-24 16:32:08 +00:00
rodzic ac921f0796
commit 92e812e20d
2 zmienionych plików z 28 dodań i 20 usunięć
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37
vhdl_atom/RGBtoHDMI.vhdl
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@ -61,7 +61,7 @@ architecture Behavorial of RGBtoHDMI is
constant atom_clamp_end : unsigned(8 downto 0) := to_unsigned(512 - 255 + 248, 9);
-- Sampling points
constant INIT_SAMPLING_POINTS : std_logic_vector(3 downto 0) := "1111";
constant INIT_SAMPLING_POINTS : std_logic_vector(3 downto 0) := "0010";
signal shift_R : std_logic_vector(3 downto 0);
signal shift_G : std_logic_vector(3 downto 0);
@ -177,28 +177,25 @@ begin
end if;
-- Atom pixel processing
if counter(0) /= offset(0) then
AL1 <= AL_I;
AH1 <= AH_I;
BL1 <= BL_I;
BH1 <= BH_I;
AL1 <= AL_I;
AH1 <= AH_I;
BL1 <= BL_I;
BH1 <= BH_I;
AL2 <= AL1;
AH2 <= AH1;
BL2 <= BL1;
BH2 <= BH1;
AL2 <= AL1;
AH2 <= AH1;
BL2 <= BL1;
BH2 <= BH1;
AL3 <= AL2;
AH3 <= AH2;
BL3 <= BL2;
BH3 <= BH2;
L1 <= L_I;
L2 <= L1;
L3 <= L2;
end if;
AL3 <= AL2;
AH3 <= AH2;
BL3 <= BL2;
BH3 <= BH2;
L1 <= L_I;
L2 <= L1;
L3 <= L2;
if sample_C = '1' then
AL <= (AL1 AND AL2) OR (AL1 AND AL3) OR (AL2 AND AL3);
AH <= (AH1 AND AH2) OR (AH1 AND AH3) OR (AH2 AND AH3);

11
vhdl_atom/fitting.notes
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@ -63,3 +63,14 @@ FB3 18/18* 30/54 69/90 8/ 9
FB4 18/18* 30/54 72/90 7/ 7*
----- ----- ----- -----
69/72 119/216 234/360 27/34
7. Atom CPLD: Clock pixel pipeline every cycle
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 28/54 53/90 8/ 9
FB2 15/18 25/54 28/90 4/ 9
FB3 18/18* 30/54 69/90 8/ 9
FB4 18/18* 28/54 39/90 7/ 7*
----- ----- ----- -----
69/72 111/216 189/360 27/34