kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Pi Firmware: Use FLIP_BUFFER and remove obsolete POLL_VSYNC code
Change-Id: I7b885bdd0d7f87914e2811bce5bae567d6323452soft_delitch
rodzic
89b278b163
commit
89853f5e48
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@ -32,13 +32,12 @@
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#define BIT_PROBE 0x02
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#define BIT_CALIBRATE 0x04
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#define BIT_CAL_COUNT 0x08
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#define BIT_VSYNC_SEEN 0x10
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#define BIT_INITIALIZE 0x10
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#define BIT_ELK 0x20
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#define BIT_SCANLINES 0x40
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#define BIT_FIELD_TYPE 0x80
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#define BIT_CLEAR 0x100
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#define BIT_VSYNC 0x200
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#define BIT_INITIALIZE 0x400
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// Note, due to a hack, bits 16, 19 and 26 are unavailale
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// as the are used for switch change detection
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@ -19,28 +19,6 @@
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mov r7, #0
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tst r3, #(BIT_VSYNC)
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beq novsync\@
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tst r3, #(BIT_MODE7 | BIT_PROBE | BIT_VSYNC_SEEN)
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bne novsync\@
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ldr r0, =INTPEND2
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ldr r0, [r0]
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tst r0, #(1<<VSYNCINT)
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beq novsync\@
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#ifndef MULTI_BUFFER
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ldr r0, =SMICTRL
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mov r10, #0
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str r10, [r0]
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#endif
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orr r7, #0x11000000
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orr r7, #0x00110000
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orr r7, #0x00001100
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orr r7, #0x00000011
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orr r3, r3, #BIT_VSYNC_SEEN
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novsync\@:
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.endm
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.macro POLL_VSYNC
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#ifdef MULTI_BUFFER
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// Skip the multi buffering in mode 7 and probe mode
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tst r3, #(BIT_MODE7 | BIT_PROBE)
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bne novsync\@
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// Poll for the VSYNC interrupt
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@ -52,15 +30,29 @@ novsync\@:
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ldr r0, =SMICTRL
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mov r10, #0
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str r10, [r0]
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// Mark the next line in red
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orr r7, #0x11000000
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orr r7, #0x00110000
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orr r7, #0x00001100
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orr r7, #0x00000011
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novsync\@:
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.endm
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#ifdef MULTI_BUFFER
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.macro FLIP_BUFFER
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// Skip the multi buffering in mode 7 and probe mode
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tst r3, #(BIT_MODE7 | BIT_PROBE)
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bne noflip\@
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// Flip to the last completed draw buffer
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// It seems the GPU delays this until the next vsync
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push {r0-r3}
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mov r0, r3, lsr #OFFSET_LAST_BUFFER
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and r0, r0, #3
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bl swapBuffer
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pop {r0-r3}
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novsync\@:
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#endif
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noflip\@:
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.endm
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#endif
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.macro WAIT_FOR_CSYNC_0
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wait\@:
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@ -247,12 +239,8 @@ skip_swap:
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frame:
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POLL_VSYNC
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bl wait_for_vsync
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POLL_VSYNC
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// Working registers in the second half
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//
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// r0 = scratch register
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@ -379,8 +367,6 @@ skip_switch_test:
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skip_line_loop:
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POLL_VSYNC
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WAIT_FOR_CSYNC_0
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WAIT_FOR_CSYNC_1
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@ -390,14 +376,10 @@ skip_line_loop:
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// Process active lines
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ldr r5, =NUM_ACTIVE
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// Clear the vsync-seen flag
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bic r3, r3, #BIT_VSYNC_SEEN
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process_line_loop:
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SHOW_VSYNC
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POLL_VSYNC
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// Wait for the start of hsync
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WAIT_FOR_CSYNC_0
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READ_CYCLE_COUNTER r10
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@ -471,8 +453,9 @@ skip_osd_update:
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and r0, #3
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bic r3, r3, #MASK_LAST_BUFFER
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orr r3, r3, r0, lsl #OFFSET_LAST_BUFFER
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// Flip to it on next V SYNC
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FLIP_BUFFER
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#endif
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POLL_VSYNC
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// Loop back if not calibrate mode...
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tst r3, #BIT_CALIBRATE
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