kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
New version of Atom YUV CPLD to work with 6 bit board (includes invert bit for 6847 direct connection)
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# Global Clock Nets
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NET "clk" BUFG=CLK;
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# Global Clock Nets
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NET "sp_clk" BUFG=CLK;
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# 96MHz clock domain
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NET "clk" TNM_NET = clk_period_grp_1;
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TIMESPEC TS_clk_period_1 = PERIOD "clk_period_grp_1" 10.4ns HIGH;
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# 10MHz clock domain
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#NET "sp_clk" TNM_NET = clk_period_grp_2;
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#TIMESPEC TS_clk_period_2 = PERIOD "clk_period_grp_2" 100ns HIGH;
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NET "clk" LOC = "P43"; # input gpio21 (gclk)
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NET "AH_I" LOC = "P32"; # input
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NET "AL_I" LOC = "P34"; # input
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NET "BH_I" LOC = "P30"; # input
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NET "BL_I" LOC = "P37"; # input
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NET "LH_I" LOC = "P31"; # input
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NET "LL_I" LOC = "P36"; # input
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NET "HS_I" LOC = "P23"; # input
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NET "FS_I" LOC = "P41"; # input
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NET "version" LOC = "P33"; # input gpio18 (gsr)
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NET "clamp" LOC = "P19"; # input gpio24
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NET "sp_clk" LOC = "P44"; # input gpio20 (gclk)
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NET "sp_data" LOC = "P7"; # input gpio0 (input only)
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NET "sp_clken" LOC = "P6"; # input gpio1 (input only)
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NET "quad(0)" LOC = "P29"; # output gpio2
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NET "quad(1)" LOC = "P28"; # output gpio3
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NET "quad(2)" LOC = "P27"; # output gpio4
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NET "quad(3)" LOC = "P5"; # output gpio5
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NET "quad(4)" LOC = "P2"; # output gpio6
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NET "quad(5)" LOC = "P8"; # output gpio7
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NET "quad(6)" LOC = "P12"; # output gpio8
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NET "quad(7)" LOC = "P14"; # output gpio9
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NET "quad(8)" LOC = "P16"; # output gpio10
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NET "quad(9)" LOC = "P13"; # output gpio11
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NET "quad(10)" LOC = "P3"; # output gpio12
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NET "quad(11)" LOC = "P1"; # output gpio13
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NET "psync" LOC = "P22"; # output gpio17
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NET "csync" LOC = "P20"; # output gpio23
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NET "quad(0)" SLOW;
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NET "quad(1)" SLOW;
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NET "quad(2)" SLOW;
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NET "quad(3)" SLOW;
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NET "quad(4)" SLOW;
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NET "quad(5)" SLOW;
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NET "quad(6)" SLOW;
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NET "quad(7)" SLOW;
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NET "quad(8)" SLOW;
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NET "quad(9)" SLOW;
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NET "quad(10)" SLOW;
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NET "quad(11)" SLOW;
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NET "psync" SLOW;
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NET "csync" SLOW;
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@ -0,0 +1,342 @@
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----------------------------------------------------------------------------------
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-- Engineer: David Banks
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--
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-- Create Date: 15/7/2018
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-- Module Name: RGBtoHDMI CPLD
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-- Project Name: RGBtoHDMI
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-- Target Devices: XC9572XL
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--
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-- Version: 1.0
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity RGBtoHDMI is
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Port (
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-- From Atom L/PA/PB Comparators
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AL_I: in std_logic;
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AH_I: in std_logic;
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BL_I: in std_logic;
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BH_I: in std_logic;
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LL_I: in std_logic;
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LH_I: in std_logic;
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HS_I: in std_logic;
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FS_I: in std_logic;
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-- To Atom L/PA/PB Comparators
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clamp: out std_logic;
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-- From Pi
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clk: in std_logic;
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sp_clk: in std_logic;
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sp_clken: in std_logic;
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sp_data: in std_logic;
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-- To PI GPIO
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quad: out std_logic_vector(11 downto 0);
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psync: out std_logic;
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csync: out std_logic;
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-- User interface
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version: in std_logic
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);
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end RGBtoHDMI;
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architecture Behavorial of RGBtoHDMI is
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-- Version number: Design_Major_Minor
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-- Design: 0 = Normal CPLD, 1 = Alternative CPLD, 2=Atom CPLD
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constant VERSION_NUM : std_logic_vector(11 downto 0) := x"230";
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-- Default offset to start sampling at
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constant default_offset : unsigned(8 downto 0) := to_unsigned(512 - 255 + 8, 9);
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-- Turn on back porch clamp
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constant atom_clamp_start : unsigned(8 downto 0) := to_unsigned(512 - 255 + 48, 9);
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-- Turn off back port clamo
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constant atom_clamp_end : unsigned(8 downto 0) := to_unsigned(512 - 255 + 248, 9);
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-- Sampling points
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constant INIT_SAMPLING_POINTS : std_logic_vector(6 downto 0) := "0110000";
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signal shift_R : std_logic_vector(1 downto 0);
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signal shift_G : std_logic_vector(1 downto 0);
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signal shift_B : std_logic_vector(1 downto 0);
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signal shift_X : std_logic_vector(1 downto 0);
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-- The sampling counter runs at 8x pixel clock of 7.15909MHz = 56.272720MHz
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--
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-- The luminance signal is sampled every 8 counts (bits 2..0)
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-- The chromance signal is sampled every 16 counts (bits 3..0)
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-- The pixel shift register is shifter every 4 counts (bits 1..0)
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-- (i.e. each pixel is replicated twice)
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-- The quad counter is bits 3..2
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-- The psync flag is bit 4
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--
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-- At the moment we don't count pixels with the line, the Pi does that
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signal counter : unsigned(8 downto 0);
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-- Sample point register;
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signal sp_reg : std_logic_vector(6 downto 0) := INIT_SAMPLING_POINTS;
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-- Break out of sp_reg
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signal offset : unsigned (3 downto 0);
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signal filter_C : std_logic;
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signal filter_L : std_logic;
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signal invert_L : std_logic;
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-- Sample pixel on next clock; pipelined to reduce the number of product terms
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signal sample_C : std_logic;
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signal sample_L : std_logic;
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-- Decoded RGB signals
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signal R : std_logic;
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signal G : std_logic;
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signal B : std_logic;
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signal X : std_logic; -- indicates either dark orange or bright orange
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-- R/PA/PB processing pipeline
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signal AL1 : std_logic;
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signal AH1 : std_logic;
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signal BL1 : std_logic;
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signal BH1 : std_logic;
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signal LL1 : std_logic;
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signal LH1 : std_logic;
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signal AL2 : std_logic;
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signal AH2 : std_logic;
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signal BL2 : std_logic;
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signal BH2 : std_logic;
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signal LL2 : std_logic;
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signal LH2 : std_logic;
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signal AL3 : std_logic;
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signal AH3 : std_logic;
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signal BL3 : std_logic;
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signal BH3 : std_logic;
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signal LL3 : std_logic;
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signal LH3 : std_logic;
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signal AL : std_logic;
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signal AH : std_logic;
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signal BL : std_logic;
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signal BH : std_logic;
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signal LL : std_logic;
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signal LH : std_logic;
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signal HS1 : std_logic;
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signal HS2 : std_logic;
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signal FS1 : std_logic;
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function map_to_sixbit_pixel (i : std_logic_vector(3 downto 0))
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return std_logic_vector is
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variable temp : std_logic_vector(5 downto 0);
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begin
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case i is
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when "0000" => temp := "000000";
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when "0001" => temp := "000001";
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when "0010" => temp := "000010";
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when "0011" => temp := "000011";
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when "0100" => temp := "000100";
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when "0101" => temp := "000101";
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when "0110" => temp := "000110";
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when "0111" => temp := "000111";
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when "1000" => temp := "001011";
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when "1001" => temp := "010011";
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when "1010" => temp := "001000";
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when "1011" => temp := "010000";
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when others => temp := "000000";
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end case;
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return temp;
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end function;
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begin
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offset <= unsigned(sp_reg(3 downto 0));
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filter_C <= sp_reg(4);
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filter_L <= sp_reg(5);
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invert_L <= sp_reg(6);
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-- Shift the bits in LSB first
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process(sp_clk)
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begin
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if rising_edge(sp_clk) then
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if sp_clken = '1' then
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sp_reg <= sp_data & sp_reg(sp_reg'left downto sp_reg'right + 1);
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end if;
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end if;
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end process;
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process(clk)
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begin
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if rising_edge(clk) then
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-- synchronize CSYNC to the sampling clock
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HS1 <= HS_I;
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HS2 <= HS1;
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-- Counter is used to find sampling point for first pixel
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if HS2 = '0' and HS1 = '1' then
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counter <= default_offset;
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elsif counter(counter'left) = '1' then
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counter <= counter + 1;
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else
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counter(5 downto 0) <= counter(5 downto 0) + 1;
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end if;
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-- sample luminance signal
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if counter(2 downto 0) = (not offset(2)) & offset(1 downto 0) then
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sample_L <= '1';
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else
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sample_L <= '0';
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end if;
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-- sample colour signal
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if counter(3 downto 0) = (not offset(3)) & offset(2 downto 0) then
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sample_C <= '1';
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else
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sample_C <= '0';
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end if;
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-- Atom pixel processing (invert lsb of u/v)
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AL1 <= not(AL_I);
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AH1 <= AH_I;
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BL1 <= not(BL_I);
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BH1 <= BH_I;
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AL2 <= AL1;
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AH2 <= AH1;
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BL2 <= BL1;
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BH2 <= BH1;
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AL3 <= AL2;
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AH3 <= AH2;
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BL3 <= BL2;
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BH3 <= BH2;
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LL1 <= (LL_I AND (NOT invert_L)) OR ((NOT LH_I) AND invert_L);
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LL2 <= LL1;
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LL3 <= LL2;
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LH1 <= (LH_I AND (NOT invert_L)) OR ((NOT LL_I) AND invert_L);
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LH2 <= LH1;
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LH3 <= LH2;
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if sample_C = '1' then
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if filter_C = '1' then
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AL <= (AL1 AND AL2) OR (AL1 AND AL3) OR (AL2 AND AL3);
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AH <= (AH1 AND AH2) OR (AH1 AND AH3) OR (AH2 AND AH3);
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BL <= (BL1 AND BL2) OR (BL1 AND BL3) OR (BL2 AND BL3);
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BH <= (BH1 AND BH2) OR (BH1 AND BH3) OR (BH2 AND BH3);
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else
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AL <= AL2;
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AH <= AH2;
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BL <= BL2;
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BH <= BH2;
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end if;
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end if;
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if sample_L = '1' then
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if filter_L = '1' then
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LL <= (LL1 AND LL2) OR (LL1 AND LL3) OR (LL2 AND LL3);
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LH <= (LH1 AND LH2) OR (LH1 AND LH3) OR (LH2 AND LH3);
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else
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LL <= LL2;
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LH <= LH2;
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end if;
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end if;
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-- YUV to RGB
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if sample_L = '1' then
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-- AL AH BL BH LL LH X B G R
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--YELLOW WH 1.5 1.0 0 0 1 0 X X 0 0 1 1
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--RED WL 2.0 1.5 0 1 0 0 X X 0 0 0 1
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--MAGENTA WM 2.0 2.0 0 1 0 1 X X 0 1 0 1
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--BUFF WH 1.5 1.5 0 0 0 0 1 X 0 1 1 1
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--BRIGHT ORANGE WH 2.0 1.0 0 1 1 0 X 1 1 0 0 1
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--DARK ORANGE BL 2.0 1.0 0 1 1 0 0 X 1 0 1 1
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R <= (NOT AL AND NOT AH AND BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND BH) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND LL) OR (NOT AL AND AH AND BL AND NOT BH AND LH) OR (NOT AL AND AH AND BL AND NOT BH AND LH) OR (NOT AL AND AH AND BL AND NOT BH AND NOT LL);
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-- AL AH BL BH LL LH X B G R
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--YELLOW WM 1.5 1.0 0 0 1 0 X X 0 0 1 1
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--CYAN WM 1.0 1.5 1 0 0 0 X X 0 1 1 0
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--GREEN WM 1.0 1.0 1 0 1 0 1 X 0 0 1 0
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--DARK GREEN BL 1.0 1.0 1 0 1 0 0 X 1 0 1 0
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--BUFF WM 1.5 1.5 0 0 0 0 1 X 0 1 1 1
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--DARK ORANGE BL 2.0 1.0 0 1 1 0 0 X 1 0 1 1
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G <= (NOT AL AND NOT AH AND BL AND NOT BH) OR (AL AND NOT AH AND NOT BL AND NOT BH) OR (AL AND NOT AH AND BL AND NOT BH) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND LL) OR (NOT AL AND AH AND BL AND NOT BH AND NOT LL);
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-- AL AH BL BH LL LH X B G R
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--BLUE WL 1.5 2.0 0 0 0 1 X X 0 1 0 0
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--CYAN WM 1.0 1.5 1 0 0 0 X X 0 1 1 0
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--MAGENTA WM 2.0 2.0 0 1 0 1 X X 0 1 0 1
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--BUFF WM 1.5 1.5 0 0 0 0 1 X 0 1 1 1
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B <= (NOT AL AND NOT AH AND NOT BL AND BH) OR (AL AND NOT AH AND NOT BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND BH) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND LL);
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-- AL AH BL BH LL LH X B G R
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--NORMAL ORANGE WM 2.0 1.0 0 1 1 0 1 0 1 0 0 0
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--BRIGHT ORANGE WH 2.0 1.0 0 1 1 0 1 1 1 0 0 1
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--DARK GREEN BL 1.0 1.0 1 0 1 0 0 X 1 0 1 0
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--DARK ORANGE BL 2.0 1.0 0 1 1 0 0 X 1 0 1 1
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X <= (NOT AL AND AH AND BL AND NOT BH) OR (AL AND NOT AH AND BL AND NOT BH AND NOT LL);
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end if;
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if sample_L = '1' and counter(counter'left) = '0' then
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-- R Sample/shift register
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shift_R <= R & shift_R(1);
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-- G Sample/shift register
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shift_G <= G & shift_G(1);
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-- B Sample/shift register
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shift_B <= B & shift_B(1);
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-- X Sample/shift register
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shift_X <= X & shift_X(1);
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end if;
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-- Output quad register
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if version = '0' then
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quad <= VERSION_NUM;
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psync <= '0';
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elsif counter(counter'left) = '0' then
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if counter(3 downto 0) = "0000" then
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quad(11 downto 6) <= map_to_sixbit_pixel(shift_X(1) & shift_B(1) & shift_G(1) & shift_R(1));
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quad( 5 downto 0) <= map_to_sixbit_pixel(shift_X(0) & shift_B(0) & shift_G(0) & shift_R(0));
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end if;
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if counter(3 downto 0) = "0010" then
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psync <= counter(4);
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end if;
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else
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quad <= (others => '0');
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psync <= '0';
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end if;
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-- generate the clamp output
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if counter >= atom_clamp_start AND counter < atom_clamp_end then
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clamp <= '1';
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else
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clamp <= '0';
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end if;
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-- generate the csync output
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if HS2 = '0' and HS1 = '1' then
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FS1 <= FS_I;
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end if;
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if HS2 = '1' and HS1 = '0' then
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csync <= '0';
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elsif HS2 = '0' and HS1 = '1' and not (FS1 = '0' and FS_I = '1') then
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csync <= '1';
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end if;
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end if;
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end process;
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end Behavorial;
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@ -0,0 +1,237 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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|
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<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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</header>
|
||||
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="RGBtoHDMI.vhdl" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="RGBtoHDMI.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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<properties>
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<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="None" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|RGBtoHDMI|Behavorial" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../RGBtoHDMI.vhdl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/RGBtoHDMI" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="RGBtoHDMI" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="RGBtoHDMI_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="RGBtoHDMI_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="RGBtoHDMI_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="RGBtoHDMI_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="RGBtoHDMI" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Detail" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="RGBtoHDMI" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-04-24T12:02:15" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D441DEAB1BF331CCD57BEACA4EE893A0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,175 @@
|
|||
1. Atom CPLD: Initial version for home-etched prototype
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 30/54 49/90 8/ 9
|
||||
FB2 17/18 26/54 38/90 4/ 9
|
||||
FB3 18/18* 30/54 69/90 8/ 9
|
||||
FB4 18/18* 32/54 48/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
71/72 118/216 204/360 27/34
|
||||
|
||||
2. Atom CPLD: Reworked for a 57.272MHz clock
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 26/54 48/90 8/ 9
|
||||
FB2 14/18 23/54 31/90 4/ 9
|
||||
FB3 18/18* 30/54 61/90 8/ 9
|
||||
FB4 18/18* 29/54 45/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
68/72 108/216 185/360 27/34
|
||||
|
||||
3. Atom CPLD: Shave two bits of the counter
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 30/54 49/90 8/ 9
|
||||
FB2 12/18 22/54 27/90 4/ 9
|
||||
FB3 18/18* 28/54 60/90 8/ 9
|
||||
FB4 18/18* 30/54 44/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
66/72 110/216 180/360 27/34
|
||||
|
||||
4. Atom CPLD: Added back in glitch filtering
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 30/54 58/90 8/ 9
|
||||
FB2 12/18 24/54 39/90 4/ 9
|
||||
FB3 18/18* 27/54 60/90 8/ 9
|
||||
FB4 18/18* 31/54 83/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
66/72 112/216 240/360 27/34
|
||||
|
||||
5. Atom CPLD: Generate CSYNC from HS_N and FS_N
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 30/54 58/90 8/ 9
|
||||
FB2 13/18 25/54 40/90 4/ 9
|
||||
FB3 18/18* 29/54 63/90 8/ 9
|
||||
FB4 18/18* 31/54 83/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
67/72 115/216 244/360 27/34
|
||||
|
||||
6. Atom CPLD: Increase Offset to 4 bits
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 29/54 52/90 8/ 9
|
||||
FB2 15/18 30/54 41/90 4/ 9
|
||||
FB3 18/18* 30/54 69/90 8/ 9
|
||||
FB4 18/18* 30/54 72/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
69/72 119/216 234/360 27/34
|
||||
|
||||
7. Atom CPLD: Clock pixel pipeline every cycle
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 28/54 53/90 8/ 9
|
||||
FB2 15/18 25/54 28/90 4/ 9
|
||||
FB3 18/18* 30/54 69/90 8/ 9
|
||||
FB4 18/18* 28/54 39/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
69/72 111/216 189/360 27/34
|
||||
|
||||
8. Atom CPLD: Send two 4-bit pixels per psync edge
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 27/54 46/90 8/ 9
|
||||
FB2 11/18 20/54 21/90 4/ 9
|
||||
FB3 18/18* 28/54 63/90 8/ 9
|
||||
FB4 18/18* 27/54 36/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
65/72 102/216 166/360 27/34
|
||||
|
||||
9. Atom CPLD: Discriminate normal and bright orange
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 28/54 46/90 8/ 9
|
||||
FB2 15/18 24/54 25/90 5/ 9
|
||||
FB3 18/18* 28/54 63/90 8/ 9
|
||||
FB4 18/18* 29/54 39/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
69/72 109/216 173/360 28/34
|
||||
|
||||
10. Atom CPLD: Discriminate dark green/dark orange text background
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 28/54 48/90 8/ 9
|
||||
FB2 15/18 24/54 25/90 5/ 9
|
||||
FB3 18/18* 28/54 63/90 8/ 9
|
||||
FB4 18/18* 29/54 39/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
69/72 109/216 175/360 28/34
|
||||
|
||||
10. Atom CPLD: Made C/L noise filters configurable
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 29/54 49/90 8/ 9
|
||||
FB2 17/18 26/54 29/90 5/ 9
|
||||
FB3 18/18* 28/54 63/90 8/ 9
|
||||
FB4 18/18* 31/54 44/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
71/72 114/216 185/360 28/34
|
||||
|
||||
11. Atom CPLD: Added two cycles of skew to PSYNC
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 29/54 49/90 8/ 9
|
||||
FB2 17/18 26/54 29/90 5/ 9
|
||||
FB3 18/18* 28/54 63/90 8/ 9
|
||||
FB4 18/18* 31/54 44/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
71/72 114/216 185/360 28/34
|
||||
|
||||
13. Atom CPLD: Use sixbit pixels, with a new mapping of colours
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 32/54 59/90 8/ 9
|
||||
FB2 17/18 26/54 29/90 5/ 9
|
||||
FB3 18/18* 32/54 76/90 8/ 9
|
||||
FB4 18/18* 33/54 45/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
71/72 123/216 209/360 28/34
|
||||
|
||||
14. Atom CPLD: Changed .ucf file for PCB v2
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 33/54 63/90 9/ 9*
|
||||
FB2 18/18* 35/54 47/90 7/ 9
|
||||
FB3 18/18* 32/54 76/90 9/ 9*
|
||||
FB4 17/18 18/54 23/90 3/ 7
|
||||
----- ----- ----- -----
|
||||
71/72 118/216 209/360 28/34
|
||||
|
||||
15. Atom CPLD: Adjust start offset by one pixel to allow perfect centering (now v2.3)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 33/54 63/90 9/ 9*
|
||||
FB2 18/18* 35/54 47/90 7/ 9
|
||||
FB3 18/18* 32/54 77/90 9/ 9*
|
||||
FB4 17/18 18/54 23/90 3/ 7
|
||||
----- ----- ----- -----
|
||||
71/72 118/216 210/360 28/34
|
||||
|
||||
16. Atom CPLD: Adjust colour sampling point (now v2.4)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 33/54 63/90 9/ 9*
|
||||
FB2 18/18* 35/54 47/90 7/ 9
|
||||
FB3 18/18* 32/54 75/90 9/ 9*
|
||||
FB4 17/18 18/54 23/90 3/ 7
|
||||
----- ----- ----- -----
|
||||
71/72 118/216 208/360 28/34
|
||||
Ładowanie…
Reference in New Issue