diff --git a/vhdl_YUV_6bit/RGBtoHDMI.vhdl b/vhdl_YUV_6bit/RGBtoHDMI.vhdl index 71ee3bdd..53197d51 100644 --- a/vhdl_YUV_6bit/RGBtoHDMI.vhdl +++ b/vhdl_YUV_6bit/RGBtoHDMI.vhdl @@ -49,7 +49,7 @@ architecture Behavorial of RGBtoHDMI is -- Version number: Design_Major_Minor -- Design: 0 = Normal CPLD, 1 = Alternative CPLD, 2=Atom CPLD, 3=YUV6847 CPLD - constant VERSION_NUM : std_logic_vector(11 downto 0) := x"372"; + constant VERSION_NUM : std_logic_vector(11 downto 0) := x"373"; -- NOTE: the difference between the leading and trailing offsets is -- 256 clks = 32 pixel clocks. @@ -122,6 +122,9 @@ architecture Behavorial of RGBtoHDMI is signal LH_S : std_logic; signal swap_bits : std_logic; + signal sample_L : std_logic; + signal sample_AB : std_logic; + signal HS_counter : unsigned(1 downto 0); begin @@ -265,9 +268,22 @@ begin LL2 <= LL1; LH2 <= LH1; + -- Pipeline the sample signals to reduce the product terms + if (subsam_C = '0' and counter(2 downto 0) = "111") or + (subsam_C = '1' and counter(3 downto 0) = "0011") then + sample_AB <= '1'; + else + sample_AB <= '0'; + end if; + + if counter(2 downto 0) = "111" then + sample_L <= '1'; + else + sample_L <= '0'; + end if; + -- sample colour signal - if (subsam_C = '0' and counter(2 downto 0) = "000") or - (subsam_C = '1' and counter(3 downto 0) = "0100") then + if sample_AB = '1' then AL <= AL_next; AH <= AH_next; BL <= BL_next; @@ -275,7 +291,7 @@ begin end if; -- sample luminance signal - if counter(2 downto 0) = "000" then + if sample_L = '1' then LL <= LL_next; LH <= LH_next; end if; diff --git a/vhdl_YUV_6bit/YUV_CPLD_v73.xsvf b/vhdl_YUV_6bit/YUV_CPLD_v73.xsvf new file mode 100644 index 00000000..a281761e Binary files /dev/null and b/vhdl_YUV_6bit/YUV_CPLD_v73.xsvf differ diff --git a/vhdl_YUV_6bit/fitting.notes b/vhdl_YUV_6bit/fitting.notes index 2e95a38c..850cbb93 100644 --- a/vhdl_YUV_6bit/fitting.notes +++ b/vhdl_YUV_6bit/fitting.notes @@ -41,3 +41,58 @@ FB3 11/18 44/54 83/90 9/ 9* FB4 17/18 33/54 83/90 6/ 7 ----- ----- ----- ----- 59/72 150/216 296/360 29/34 + +vhdl_YUV: Revert to original clamp timing (v6.1) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 14/18 41/54 89/90 6/ 9 +FB2 18/18* 31/54 44/90 8/ 9 +FB3 11/18 44/54 83/90 9/ 9* +FB4 16/18 29/54 82/90 6/ 7 + ----- ----- ----- ----- + 59/72 145/216 298/360 29/34 + +Adjustable clamp (v7.0) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 15/18 36/54 87/90 6/ 9 +FB2 18/18* 38/54 66/90 8/ 9 +FB3 13/18 47/54 87/90 9/ 9* +FB4 18/18* 36/54 85/90 6/ 7 + ----- ----- ----- ----- + 64/72 157/216 325/360 29/34 + +Improved clamping times (v7.1) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 15/18 36/54 87/90 6/ 9 +FB2 18/18* 38/54 66/90 8/ 9 +FB3 13/18 47/54 87/90 9/ 9* +FB4 18/18* 36/54 85/90 6/ 7 + ----- ----- ----- ----- + 64/72 157/216 325/360 29/34 + +Further increased clamping times (v7.2) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 15/18 36/54 87/90 6/ 9 +FB2 18/18* 38/54 66/90 8/ 9 +FB3 13/18 47/54 87/90 9/ 9* +FB4 18/18* 36/54 85/90 6/ 7 + ----- ----- ----- ----- + 64/72 157/216 325/360 29/34 + +Pipeline the sample signals to reduce the product terms (v7.3) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 16/18 41/54 86/90 6/ 9 +FB2 18/18* 27/54 39/90 8/ 9 +FB3 14/18 36/54 88/90 9/ 9* +FB4 18/18* 36/54 75/90 6/ 7 + ----- ----- ----- ----- + 66/72 140/216 288/360 29/34