kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
First part of universal binary (Pi0,1,2,3) conversion
IanSB
rodzic
05b649fe91
commit
60453dce62
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@ -4,14 +4,15 @@
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#include "rpi-interrupts.h"
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//#include "tube-defs.h"
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#include "startup.h"
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#include "defs.h"
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// From here: https://www.raspberrypi.org/forums/viewtopic.php?f=72&t=53862
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void reboot_now(void)
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{
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const int PM_PASSWORD = 0x5a000000;
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const int PM_RSTC_WRCFG_FULL_RESET = 0x00000020;
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unsigned int *PM_WDOG = (unsigned int *) (_get_peripheral_base() + 0x00100024);
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unsigned int *PM_RSTC = (unsigned int *) (_get_peripheral_base() + 0x0010001c);
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//const int PM_PASSWORD = 0x5a000000;
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//const int PM_RSTC_WRCFG_FULL_RESET = 0x00000020;
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//unsigned int *PM_WDOG = (unsigned int *) (_get_peripheral_base() + 0x00100024);
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//unsigned int *PM_RSTC = (unsigned int *) (_get_peripheral_base() + 0x0010001c);
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// timeout = 1/16th of a second? (whatever)
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*PM_WDOG = PM_PASSWORD | 1;
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@ -75,10 +76,10 @@ void dump_info(unsigned int *context, int offset, char *type) {
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// The stacked LR points one or two words afer the exception address
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addr = (unsigned int *)((reg[13] & ~3) - offset);
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dump_hex((unsigned int)addr);
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#ifdef HAS_MULTICORE
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dump_string(" on core ");
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dump_digit(_get_core());
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#endif
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if (_get_hardware_id() >= _RPI2) {
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dump_string(" on core ");
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dump_digit(_get_core());
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}
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dump_string("\r\n");
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dump_string("Registers:\r\n");
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for (i = 0; i <= 13; i++) {
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@ -28,6 +28,7 @@
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// Relocate to just below 32MB
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#include "defs.h"
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#include "rpi-base.h"
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.equ STACK_SIZE, 0x00100000
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@ -38,14 +39,12 @@
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.equ C0_ABORT_STACK, STACK_SIZE*5
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.equ C0_UNDEFINED_STACK, STACK_SIZE*6
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#if defined(RPI2) || defined(RPI3) || defined(RPI4)
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.equ C1_SVR_STACK, STACK_SIZE*7
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.equ C1_IRQ_STACK, STACK_SIZE*8
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.equ C1_FIQ_STACK, STACK_SIZE*9
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.equ C1_USER_STACK, STACK_SIZE*10
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.equ C1_ABORT_STACK, STACK_SIZE*11
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.equ C1_UNDEFINED_STACK, STACK_SIZE*12
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#endif
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.equ SCTLR_ENABLE_DATA_CACHE, 0x4
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.equ SCTLR_ENABLE_BRANCH_PREDICTION, 0x800
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@ -79,11 +78,9 @@
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.global _get_gpu_data_base_r4
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.global _get_gpu_command_base_r10
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#ifdef HAS_MULTICORE
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.global _get_core
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.global _init_core
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.global _spin_core
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#endif
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// From the ARM ARM (Architecture Reference Manual). Make sure you get the
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// ARMv5 documentation which includes the ARMv6 documentation which is the
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@ -141,8 +138,9 @@ _reset_:
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#endif
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// BL _enable_l1_cache
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#ifdef HAS_MULTICORE
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bl _get_hardware_id
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cmp r0, #_RPI2
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blt rpi0_1_d
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#ifdef KERNEL_OLD
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// if kernel_old=1 all cores are running and we need to sleep 1-3
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@ -192,8 +190,7 @@ _not_in_hyp_mode:
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_reset_continue:
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#endif
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#endif
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rpi0_1_d:
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// We enter execution in supervisor mode. For more information on
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// processor modes see ARM Section A2.2 (Processor Modes)
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@ -238,10 +235,10 @@ _reset_continue:
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// Enable VFP ------------------------------------------------------------
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#ifdef HAS_MULTICORE
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bl _get_hardware_id
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cmp r0, #_RPI2
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bge rpi2_4_a
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#else
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// r1 = Access Control Register
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MRC p15, #0, r1, c1, c0, #2
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// enable full access for p10,11
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@ -256,7 +253,8 @@ _reset_continue:
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MOV r0,#0x40000000
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// FPEXC = r0
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FMXR FPEXC, r0
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#endif
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rpi2_4_a:
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// The c-startup function which we never return from. This function will
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// initialise the ro data section (most things that have the const
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@ -338,26 +336,34 @@ _get_cpsr:
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.section ".text._init_cycle_counter"
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_init_cycle_counter:
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// Enable the cycle counter, and run at the ARM clock rate
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#if defined(RPI2) || defined(RPI3) || defined(RPI4)
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mov r0, #7
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mcr p15, 0, r0, c9, c12, 0
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mov r0, #(1 << 31)
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mcr p15, 0, r0, c9, c12, 1
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#else
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mov r0, #7
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mcr p15, 0, r0, c15, c12, 0
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#endif
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mov pc, lr
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// Enable the cycle counter, and run at the ARM clock rate
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push {r0, lr}
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bl _get_hardware_id
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cmp r0, #_RPI2
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blt rpi0_1_a
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mov r0, #7
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mcr p15, 0, r0, c9, c12, 0
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mov r0, #(1 << 31)
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mcr p15, 0, r0, c9, c12, 1
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b donerpi0_1_a
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rpi0_1_a:
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mov r0, #7
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mcr p15, 0, r0, c15, c12, 0
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donerpi0_1_a:
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pop {r0, pc}
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.section ".text._get_cycle_counter"
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_get_cycle_counter:
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#if defined(RPI2) || defined(RPI3) || defined(RPI4)
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push {r0, lr}
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bl _get_hardware_id
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cmp r0, #_RPI2
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blt rpi0_1_b
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mrc p15, 0, r0, c9, c13, 0
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#else
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b donerpi0_1_b
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rpi0_1_b:
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mrc p15, 0, r0, c15, c12, 1
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#endif
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mov pc, lr
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donerpi0_1_b:
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pop {r0, pc}
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.section ".text._set_interrupts"
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_set_interrupts:
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@ -480,13 +486,17 @@ _invalidate_dtlb_mva:
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.section ".text._data_memory_barrier"
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_data_memory_barrier:
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#if defined(RPI2) || defined(RPI3) || defined(RPI4)
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push {r0, lr}
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bl _get_hardware_id
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cmp r0, #_RPI2
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blt rpi0_1_c
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dmb
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#else
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b donerpi0_1_c
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rpi0_1_c:
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 5
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#endif
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mov pc, lr
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donerpi0_1_c:
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pop {r0, pc}
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#ifdef USE_MULTICORE
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.section ".text._init_core"
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@ -551,7 +561,10 @@ _init_continue:
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bl run_core
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#endif
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#ifdef HAS_MULTICORE
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bl _get_hardware_id
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cmp r0, #_RPI2
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blt rpi0_1_e
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.section ".text._spin_core"
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// If main does return for some reason, just catch it and stay here.
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_spin_core:
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@ -581,8 +594,8 @@ _get_core:
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mrc p15, 0, r0, c0, c0, 5
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and r0, #3
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mov pc, lr
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#endif
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rpi0_1_e:
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// Default handlers for FIQ/IRQ do nothing
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56
src/cache.c
56
src/cache.c
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@ -22,8 +22,6 @@ const static int aa = 1;
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const static int bb = 1;
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const static int shareable = 1;
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#if defined(RPI2) || defined (RPI3) || defined(RPI4)
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#define SETWAY_LEVEL_SHIFT 1
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// 4 ways x 128 sets x 64 bytes per line 32KB
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@ -134,7 +132,6 @@ void CleanDataCache (void)
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}
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}
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#endif
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// TLB 4KB Section Descriptor format
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// 31..12 Section Base Address
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@ -157,11 +154,11 @@ void map_4k_page(int logical, int physical) {
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// XP (bit 23) in SCTRL no longer exists, and we see to be using ARMv6 table formats
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// this means bit 0 of the page table is actually XN and must be clear to allow native ARM code to execute
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// (this was the cause of issue #27)
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#if defined(RPI2) || defined (RPI3) || defined(RPI4)
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PageTable2[logical] = (physical<<12) | 0x132 | (bb << 6) | (aa << 2);
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#else
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PageTable2[logical] = (physical<<12) | 0x133 | (bb << 6) | (aa << 2);
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#endif
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if (_get_hardware_id() >= _RPI2) {
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PageTable2[logical] = (physical<<12) | 0x132 | (bb << 6) | (aa << 2);
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} else {
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PageTable2[logical] = (physical<<12) | 0x133 | (bb << 6) | (aa << 2);
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}
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}
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void enable_MMU_and_IDCaches(int cached_screen_area, int cached_screen_size)
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@ -296,34 +293,33 @@ void enable_MMU_and_IDCaches(int cached_screen_area, int cached_screen_size)
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asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
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//log_debug("ttbcr = %08x", ttbcr);
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#if defined(RPI2) || defined(RPI3) || defined(RPI4)
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// set TTBR0 - page table walk memory cacheability/shareable
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// [Bit 0, Bit 6] indicates inner cachability: 01 = normal memory, inner write-back write-allocate cacheable
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// [Bit 4, Bit 3] indicates outer cachability: 01 = normal memory, outer write-back write-allocate cacheable
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// Bit 1 indicates sharable
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// 4A = 0100 1010
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int attr = ((aa & 1) << 6) | (bb << 3) | (shareable << 1) | ((aa & 2) >> 1);
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asm volatile ("mcr p15, 0, %0, c2, c0, 0" :: "r" (attr | (unsigned) &PageTable));
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#else
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// set TTBR0 (page table walk inner cacheable, outer non-cacheable, shareable memory)
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asm volatile ("mcr p15, 0, %0, c2, c0, 0" :: "r" (0x03 | (unsigned) &PageTable));
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#endif
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if (_get_hardware_id() >= _RPI2) {
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// set TTBR0 - page table walk memory cacheability/shareable
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// [Bit 0, Bit 6] indicates inner cachability: 01 = normal memory, inner write-back write-allocate cacheable
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// [Bit 4, Bit 3] indicates outer cachability: 01 = normal memory, outer write-back write-allocate cacheable
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// Bit 1 indicates sharable
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// 4A = 0100 1010
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int attr = ((aa & 1) << 6) | (bb << 3) | (shareable << 1) | ((aa & 2) >> 1);
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asm volatile ("mcr p15, 0, %0, c2, c0, 0" :: "r" (attr | (unsigned) &PageTable));
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} else {
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// set TTBR0 (page table walk inner cacheable, outer non-cacheable, shareable memory)
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asm volatile ("mcr p15, 0, %0, c2, c0, 0" :: "r" (0x03 | (unsigned) &PageTable));
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}
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unsigned ttbr0;
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asm volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttbr0));
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//log_debug("ttbr0 = %08x", ttbr0);
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// Invalidate entire data cache
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#if defined(RPI2) || defined(RPI3) || defined(RPI4)
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// asm volatile ("isb" ::: "memory");
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asm volatile (".word 0xf57ff06f" ::: "memory");
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InvalidateDataCache();
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#else
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// invalidate data cache and flush prefetch buffer
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// NOTE: The below code seems to cause a Pi 2 to crash
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asm volatile ("mcr p15, 0, %0, c7, c5, 4" :: "r" (0) : "memory");
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asm volatile ("mcr p15, 0, %0, c7, c6, 0" :: "r" (0) : "memory");
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#endif
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if (_get_hardware_id() >= _RPI2) {
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asm volatile (".word 0xf57ff06f" ::: "memory"); // asm volatile ("isb" ::: "memory"); (won't compile on arm v6)
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InvalidateDataCache();
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} else {
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// invalidate data cache and flush prefetch buffer
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// NOTE: The below code seems to cause a Pi 2 to crash
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asm volatile ("mcr p15, 0, %0, c7, c5, 4" :: "r" (0) : "memory");
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asm volatile ("mcr p15, 0, %0, c7, c6, 0" :: "r" (0) : "memory");
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}
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// enable MMU, L1 cache and instruction cache, L2 cache, write buffer,
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// branch prediction and extended page table on
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20
src/defs.h
20
src/defs.h
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@ -11,27 +11,15 @@
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//do not leave USE_ARM_CAPTURE uncommented during a release build as all versions will be ARM
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//#define USE_ARM_CAPTURE //uncomment to select ARM capture build
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#define USE_ALT_M7DEINTERLACE_CODE // uses re-ordered code for mode7 deinterlace
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#define USE_CACHED_SCREEN // caches the upper half of the screen area and uses it for mode7 deinterlace
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#define CACHED_SCREEN_OFFSET 0x00B00000 // offset to cached screen area
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#define CACHED_SCREEN_SIZE 0x00100000 // size of cached screen area
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#define USE_ALT_M7DEINTERLACE_CODE // uses re-ordered code for mode7 deinterlace
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#if defined(RPI2) || defined(RPI3)
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#define HAS_MULTICORE // indicates multiple cores are available
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#if defined(USE_ARM_CAPTURE)
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#define WARN_12BIT // warn that 9bpp & 12bpp won't work
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#define HIDE_12BIT_PROFILES // 12 bit profile won't work on Pi zero2 etc
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#define INHIBIT_DOUBLE_HEIGHT // inhibit line doubling as it causes memory stalls
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#endif
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#endif
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#if defined(RPI4)
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#define HAS_MULTICORE // indicates multiple cores are available
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#define USE_CACHED_SCREEN // caches the upper half of the screen area and uses it for mode7 deinterlace
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#define USE_ALT_M7DEINTERLACE_CODE // uses re-ordered code for mode7 deinterlace
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#define MODE7_ALWAYS_ARM // always runs mode7 capture code on ARM
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#endif
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//#define WARN_12BIT // warn that 9bpp & 12bpp won't work
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//#define HIDE_12BIT_PROFILES // 12 bit profile won't work on Pi zero2 etc
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//#define INHIBIT_DOUBLE_HEIGHT // inhibit line doubling as it causes memory stalls
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//#define USE_MULTICORE //can be used to add code in an extra core
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@ -428,15 +428,11 @@ static param_t features[] = {
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{ F_RETURN, "Return Position", "return", 0, 1, 1 },
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{ F_DEBUG, "Debug", "debug", 0, 1, 1 },
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{ F_DIRECTION, "Button Reverse", "button_reverse", 0, 1, 1 },
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#if defined(RPI2) || defined(RPI3) || defined(RPI4)
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{ F_OCLOCK_CPU, "Overclock CPU", "overclock_cpu", 0, 100, 1 },
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{ F_OCLOCK_CORE, "Overclock Core", "overclock_core", 0, 125, 1 },
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{ F_OCLOCK_SDRAM, "Overclock SDRAM", "overclock_sdram", 0, 175, 1 },
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#else
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{ F_OCLOCK_CPU, "Overclock CPU", "overclock_cpu", 0, 75, 1 },
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{ F_OCLOCK_CORE, "Overclock Core", "overclock_core", 0, 175, 1 },
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{ F_OCLOCK_SDRAM, "Overclock SDRAM", "overclock_sdram", 0, 175, 1 },
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#endif
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{ F_RSTATUS, "Powerup Message", "powerup_message", 0, 1, 1 },
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{ F_FRONTEND, "Interface", "interface", 0, NUM_FRONTENDS - 1, 1 },
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{ -1, NULL, NULL, 0, 0, 0 }
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@ -54,16 +54,8 @@ typedef void (*func_ptr)();
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#if defined(RPI4)
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#define USE_PLLD4
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#define SYS_CLK_DIVIDER 5
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#elif defined(RPI3)
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#define USE_PLLA
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#define SYS_CLK_DIVIDER 3
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#elif defined(RPI2)
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#define USE_PLLA
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#define SYS_CLK_DIVIDER 4
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#else
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#define USE_PLLA
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#define SYS_CLK_DIVIDER 3 // should be 4 for Pi 1 depending on core clock speed
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#endif
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//PLL defaults for different Pi versions
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@ -954,9 +946,22 @@ int calibrate_sampling_clock(int profile_changed) {
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set_pll_frequency(((double) (pll_freq >> prediv)) / 1e6, PLL_CTRL, PLL_FRAC);
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#ifdef USE_PLLC
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#if defined(USE_PLLC)
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int sys_clk_divider = 3;
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switch (_get_hardware_id()) {
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case 2:
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sys_clk_divider = 4;
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break;
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case 4:
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sys_clk_divider = 5;
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break;
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default:
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sys_clk_divider = 3; // should be 4 for Pi 1 depending on core clock speed
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break;
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}
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// Reinitialize the UART as the Core Clock has changed
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RPI_AuxMiniUartInit_With_Freq(115200, 8, pll_freq / pll_scale / SYS_CLK_DIVIDER);
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RPI_AuxMiniUartInit_With_Freq(115200, 8, pll_freq / pll_scale / sys_clk_divider);
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#endif
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// And remember for next time
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@ -1854,13 +1859,11 @@ int extra_flags() {
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return extra;
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}
|
||||
|
||||
#ifdef HAS_MULTICORE
|
||||
static void start_core(int core, func_ptr func) {
|
||||
printf("starting core %d\r\n", core);
|
||||
*(unsigned int *)(0x4000008c + 0x10 * core) = (unsigned int) func;
|
||||
asm ( "sev" );
|
||||
}
|
||||
#endif
|
||||
|
||||
// =============================================================
|
||||
// Public methods
|
||||
|
|
@ -2421,7 +2424,7 @@ void swapBuffer(int buffer) {
|
|||
#ifndef RPI4
|
||||
if (capinfo->bpp == 16) {
|
||||
// directly manipulate the display list in 16BPP mode otherwise display list gets reconstructed
|
||||
int dli = ((int)capinfo->fb | 0xc0000000) + (buffer * capinfo->height * capinfo->pitch);
|
||||
int dli = ((int)capinfo->fb | 0xc0000000) + (buffer * capinfo->height * capinfo->pitch);
|
||||
do {
|
||||
display_list[display_list_index + 5] = dli;
|
||||
} while (dli != display_list[display_list_index + 5]);
|
||||
|
|
@ -3595,24 +3598,24 @@ void kernel_main(unsigned int r0, unsigned int r1, unsigned int atags)
|
|||
}
|
||||
log_info("Pi Hardware detected as type %d", _get_hardware_id());
|
||||
display_list = SCALER_DISPLAY_LIST;
|
||||
gpioreg = (volatile uint32_t *)(_get_peripheral_base() + 0x101000UL);
|
||||
gpioreg = (volatile uint32_t *)(_get_peripheral_base() + 0x101000UL);
|
||||
init_hardware();
|
||||
|
||||
#ifdef HAS_MULTICORE
|
||||
int i;
|
||||
printf("main running on core %u\r\n", _get_core());
|
||||
for (i = 0; i < 10000000; i++);
|
||||
if (_get_hardware_id() >= _RPI2) {
|
||||
int i;
|
||||
printf("main running on core %u\r\n", _get_core());
|
||||
for (i = 0; i < 10000000; i++);
|
||||
#ifdef USE_MULTICORE
|
||||
start_core(1, _init_core);
|
||||
start_core(1, _init_core);
|
||||
#else
|
||||
start_core(1, _spin_core);
|
||||
#endif
|
||||
for (i = 0; i < 10000000; i++);
|
||||
start_core(2, _spin_core);
|
||||
for (i = 0; i < 10000000; i++);
|
||||
start_core(3, _spin_core);
|
||||
for (i = 0; i < 10000000; i++);
|
||||
start_core(1, _spin_core);
|
||||
#endif
|
||||
for (i = 0; i < 10000000; i++);
|
||||
start_core(2, _spin_core);
|
||||
for (i = 0; i < 10000000; i++);
|
||||
start_core(3, _spin_core);
|
||||
for (i = 0; i < 10000000; i++);
|
||||
}
|
||||
|
||||
rgb_to_hdmi_main();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -38,7 +38,8 @@
|
|||
|
||||
// Raspberry Pi3 has a differentway of controlling the LED
|
||||
|
||||
#if defined(RPIZERO) || defined(RPIBPLUS) || defined(RPI2) || defined(RPI3)|| defined(RPI4)
|
||||
//#if defined(RPIZERO) || defined(RPIBPLUS) || defined(RPI2) || defined(RPI3)|| defined(RPI4)
|
||||
|
||||
#define LED_GPFSEL GPFSEL[4]
|
||||
#define LED_GPFBIT 21
|
||||
#define LED_GPSET GPSET1
|
||||
|
|
@ -46,15 +47,16 @@
|
|||
#define LED_GPIO_BIT 15
|
||||
#define LED_ON() do { RPI_GpioBase->LED_GPCLR = (1 << LED_GPIO_BIT); } while(0)
|
||||
#define LED_OFF() do { RPI_GpioBase->LED_GPSET = (1 << LED_GPIO_BIT); } while(0)
|
||||
#else
|
||||
#define LED_GPFSEL GPFSEL[1]
|
||||
#define LED_GPFBIT 18
|
||||
#define LED_GPSET GPSET0
|
||||
#define LED_GPCLR GPCLR0
|
||||
#define LED_GPIO_BIT 16
|
||||
#define LED_ON() do { RPI_GpioBase->LED_GPSET = (1 << LED_GPIO_BIT); } while(0)
|
||||
#define LED_OFF() do { RPI_GpioBase->LED_GPCLR = (1 << LED_GPIO_BIT); } while(0)
|
||||
#endif
|
||||
|
||||
//#else
|
||||
// #define LED_GPFSEL GPFSEL[1]
|
||||
// #define LED_GPFBIT 18
|
||||
// #define LED_GPSET GPSET0
|
||||
// #define LED_GPCLR GPCLR0
|
||||
// #define LED_GPIO_BIT 16
|
||||
// #define LED_ON() do { RPI_GpioBase->LED_GPSET = (1 << LED_GPIO_BIT); } while(0)
|
||||
// #define LED_OFF() do { RPI_GpioBase->LED_GPCLR = (1 << LED_GPIO_BIT); } while(0)
|
||||
//#endif
|
||||
|
||||
typedef enum
|
||||
{
|
||||
|
|
|
|||
|
|
@ -56,13 +56,35 @@ set( CMAKE_OBJCOPY ${TC_PATH}${CROSS_COMPILE}objcopy
|
|||
CACHE FILEPATH "The toolchain objcopy command " FORCE )
|
||||
|
||||
# Set the CMAKE C flags (which should also be used by the assembler!
|
||||
set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mfpu=vfp" )
|
||||
|
||||
#use hardware floating point
|
||||
set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mfloat-abi=hard" )
|
||||
|
||||
#pi1 flags
|
||||
#set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=armv6zk" )
|
||||
#set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mtune=arm1176jzf-s" )
|
||||
#set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mfpu=vfp" )
|
||||
|
||||
#pi2 flags
|
||||
#set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=armv7-a" )
|
||||
#set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mtune=cortex-a7" )
|
||||
#set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mfpu=neon-vfpv4" )
|
||||
|
||||
#pi3 flags
|
||||
#set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=armv8-a" )
|
||||
#set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mtune=cortex-a53" )
|
||||
#set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mfpu=crypto-neon-fp-armv8" )
|
||||
|
||||
#current flags for pi2 & pi3
|
||||
set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=armv6zk" )
|
||||
set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mtune=arm1176jzf-s" )
|
||||
|
||||
set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mfpu=vfp" )
|
||||
set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
|
||||
set( CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
|
||||
|
||||
set( CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -march=armv7-a" )
|
||||
set( CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -mfpu=neon-vfpv4" )
|
||||
set( CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS}" CACHE STRING "" )
|
||||
|
||||
|
||||
set( KERNEL_NAME "./kernelrpi.img" )
|
||||
|
||||
|
|
|
|||
|
|
@ -81,8 +81,8 @@ set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mtune=arm1176jzf-s" )
|
|||
set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mfpu=vfp" )
|
||||
set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
|
||||
|
||||
set( CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -march=armv8-a" )
|
||||
set( CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -mfpu=crypto-neon-fp-armv8" )
|
||||
set( CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -march=armv7-a" )
|
||||
set( CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -mfpu=neon-vfpv4" )
|
||||
set( CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS}" CACHE STRING "" )
|
||||
|
||||
# Add the raspberry-pi 3 definition so conditional compilation works
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue