kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Merge remote-tracking branch 'upstream/dev' into dev
# Conflicts: # src/rgb_to_fb.Spull/20/head
IanSB
commit
5dcc730e75
26
src/defs.h
26
src/defs.h
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@ -26,15 +26,15 @@
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#define BIT_MODE7 0x01 // bit 0, indicates mode 7
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#define BIT_PROBE 0x02 // bit 1, indicates the mode is being determined
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#define BIT_CALIBRATE 0x04 // bit 2, indicates calibration is happening
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#define BIT_OSD 0x08 // bit 3, indicated the OSD is visible
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#define BIT_OSD 0x08 // bit 3, indicates the OSD is visible
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#define BIT_MODE_DETECT 0x10 // bit 4, indicates mode changes should be detected
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#define BIT_ELK 0x20 // bit 5, indicated we are an Electron
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#define BIT_ELK 0x20 // bit 5, indicates we are an Electron
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#define BIT_SCANLINES 0x40 // bit 6, indicates scan lines should be made visible
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#define BIT_FIELD_TYPE 0x80 // bit 7, indicates the field type (0 = odd, 1 = even) of the last field
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#define BIT_CLEAR 0x100 // bit 8, indicates the frame buffer should be cleared
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#define BIT_VSYNC 0x200 // bit 9, indicates the vsync frequency is being probed
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#define BIT_VSYNC_MARKER 0x400 // bit 10, indicates red vsync line displayed
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#define BIT_DEBUG 0x800 // bit 11, indicated the debug grid should be displayed
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#define BIT_VSYNC 0x200 // bit 9, indicates the red vsync indicator should be displayed
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#define BIT_VSYNC_MARKER 0x400 // bit 10, indicates current line should be replaced by the red vsync indicator
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#define BIT_DEBUG 0x800 // bit 11, indicates the debug grid should be displayed
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#define OFFSET_LAST_BUFFER 12 // bit 12-13 LAST_BUFFER
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#define MASK_LAST_BUFFER (3 << OFFSET_LAST_BUFFER)
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@ -52,12 +52,18 @@
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#define OFFSET_INTERLACE 20 // bit 20-22 INTERFACE
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#define MASK_INTERLACE (7 << OFFSET_INTERLACE)
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// bit 23-31 unused
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#define BIT_FIELD_TYPE1 0x00800000 // bit 23, indicates the field type of the previous field
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#define BIT_FIELD_TYPE1_VALID 0x01000000 // bit 24, indicates FIELD_TYPE1 is valid
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#define BIT_FIELD_TYPE2 0x02000000 // bit 25, indicates the field type of the previous but one field
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#define BIT_FIELD_TYPE2_VALID 0x04000000 // bit 26, indicates FIELD_TYPE2 is valid
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// bits 27-31 unused
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// R0 return value bits
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#define RET_SW1 0x02
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#define RET_SW2 0x04
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#define RET_SW3 0x08
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#define RET_EXPIRED 0x10
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#define RET_SW1 0x02
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#define RET_SW2 0x04
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#define RET_SW3 0x08
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#define RET_EXPIRED 0x10
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#define RET_INTERLACE_CHANGED 0x20
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// Channel definitions
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#define NUM_CHANNELS 3
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@ -427,13 +427,13 @@ static int get_feature(int num) {
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static void set_feature(int num, int value) {
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switch (num) {
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break;
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case F_DEINTERLACE:
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set_deinterlace(value);
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break;
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case F_PALETTE:
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palette = value;
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osd_update_palette();
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break;
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case F_SCANLINES:
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set_scanlines(value);
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break;
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@ -13,7 +13,6 @@
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.global sw3counter
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.global vsync_line
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.global default_vsync_line
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.global lock_fail
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// ======================================================================
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// Macros
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@ -210,8 +209,9 @@ skip_swap:
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tst r3, #BIT_CLEAR
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blne clear_screen
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// clear all the state bits apart from the following:
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// Clear the following state bits:
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bic r3, r3, #(BIT_FIELD_TYPE | BIT_CLEAR)
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bic r3, r3, #(BIT_FIELD_TYPE1_VALID | BIT_FIELD_TYPE2_VALID)
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// In Mode 7 (or on probe) write to buffer 0, display buffer 0
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bic r3, r3, #(MASK_LAST_BUFFER | MASK_CURR_BUFFER)
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@ -225,9 +225,9 @@ skip_swap:
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frame:
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bl wait_for_vsync
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ldr r0, default_vsync_line
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ldr r0, default_vsync_line
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str r0, vsync_line // default for vsync line if vsync in blanking area
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// Working registers while frame is being captured
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//
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// r0 = scratch register
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@ -313,13 +313,48 @@ buffer_chosen:
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bne exit
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skip_switch_test:
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tst r3, #BIT_MODE_DETECT // Have we been told to exit on mode change
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beq skip_mode_test
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tst r3, #BIT_MODE7
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moveq r5, #0 // Modes 0-6
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movne r5, #1 // Mode 7
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tst r3, #BIT_MODE_DETECT // Have we been told to exit on mode change
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cmpne r5, r0 // Check if we have changed mode
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cmp r5, r0 // Check if we have changed mode
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bne exit // If so, then bail, as the frame buffer needs to be resized
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tst r3, #BIT_FIELD_TYPE2_VALID
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beq skip_interlace_test // we haven't yet seen two field, so skip the test
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// compare BIT_FIELD_TYPE and BIT_FIELD_TYPE2
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// FT2 FT
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// 0 0 -> 0
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// 0 1 -> 1
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// 1 0 -> 1
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// 1 1 -> 0
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tst r3, #BIT_FIELD_TYPE
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eorne r3, #BIT_FIELD_TYPE2
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tst r3, #BIT_FIELD_TYPE2
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orrne r0, #RET_INTERLACE_CHANGED
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bne exit
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skip_interlace_test:
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// copy BIT_FIELD_TYPE_1 to BIT_FIELD_TYPE2
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tst r3, #BIT_FIELD_TYPE1
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biceq r3, #BIT_FIELD_TYPE2
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orrne r3, #BIT_FIELD_TYPE2
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tst r3, #BIT_FIELD_TYPE1_VALID // also copy the valid bit
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biceq r3, #BIT_FIELD_TYPE2_VALID
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orrne r3, #BIT_FIELD_TYPE2_VALID
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// copy BIT_FIELD_TYPE to BIT_FIELD_TYPE1
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tst r3, #BIT_FIELD_TYPE
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biceq r3, #BIT_FIELD_TYPE1
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orrne r3, #BIT_FIELD_TYPE1
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orr r3, #BIT_FIELD_TYPE1_VALID // set the valid bit
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skip_mode_test:
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// Save a copy of the frame buffer base
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push {r11}
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@ -457,6 +492,7 @@ skip_osd_update:
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// Flip to it on next V SYNC
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FLIP_BUFFER
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#endif
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push {r0-r12, lr}
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bl recalculate_hdmi_clock_line_locked_update
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pop {r0-r12, lr}
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@ -464,7 +500,7 @@ skip_osd_update:
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ldr r0, lock_fail
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cmp r0,#0
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bne lock_failed
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// Loop back if required number of fields has not been reached
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// or if negative (capture forever)
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ldr r5, param_ncapture
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@ -473,8 +509,8 @@ skip_osd_update:
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sub r5, #1
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str r5, param_ncapture
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bne frame
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lock_failed:
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lock_failed:
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// Setup the response code
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mov r0, r3
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and r0, #BIT_MODE7
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@ -687,9 +723,10 @@ linecountmod10:
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default_vsync_line:
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.word 0
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vsync_line:
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.word 0
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lock_fail:
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.word 0
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.word 0
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@ -87,7 +87,7 @@ static int vlockline = 5;
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static int nbuffers = 0;
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#endif
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static int current_vlockmode = 0xffffffff;
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static int current_vlockmode = -1;
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// Calculated so that the constants from librpitx work
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static volatile uint32_t *gpioreg = (volatile uint32_t *)(PERIPHERAL_BASE + 0x101000UL);
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@ -362,6 +362,9 @@ static int calibrate_sampling_clock() {
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init_gpclk(GPCLK_SOURCE, gpclk_divisor);
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log_debug("Done setting up divisor");
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// Invalidate the current vlock mode to force an updated, as vsync_time_ns will have changed
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current_vlockmode = -1;
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return a;
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}
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@ -1265,6 +1268,13 @@ void rgb_to_hdmi_main() {
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calibrate_sampling_clock();
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}
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if (result & RET_INTERLACE_CHANGED) {
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// Measure the frame time and set the sampling clock
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calibrate_sampling_clock();
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// Recalculate the HDMI clock (if the vlockmode property requires this)
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recalculate_hdmi_clock_line_locked_update();
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}
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} while (mode7 == last_mode7 && !fb_size_changed);
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osd_clear();
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