kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Add motion adaptive deinterlacing to Mode 0 (IanB)
Change-Id: I7d1f924d7567da000668ce15f14f4a1549f1fa70pull/28/head
rodzic
edb410c711
commit
48efdc7d61
120
src/rgb_to_fb.S
120
src/rgb_to_fb.S
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@ -121,6 +121,9 @@ wait\@:
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.endm
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.macro PROCESS_CHARS_LOOP psync_polarity
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tst r3, #BIT_MODE7
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bne process_chars_7\@
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process_chars_loop\@:
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// Initialize 8 pixel block
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@ -185,20 +188,119 @@ process_chars_loop\@:
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tst r3, #BIT_SCANLINES
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movne r0, #0
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moveq r0, r10
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tst r3, #BIT_MODE7
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streq r0, [r12, r2]
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#endif
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tst r3, #(BIT_MODE7)
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ldrne r0, [r12]
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bicne r0, #0x77000000
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bicne r0, #0x00770000
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bicne r0, #0x00007700
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bicne r0, #0x00000077
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orrne r10, r0
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str r10, [r12], #4
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str r10, [r12], #4
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subs r6, r6, #1
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bne process_chars_loop\@
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b exit_process_chars\@
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process_chars_7\@:
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push {r1, r5,r11} //*** need scratch registers
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mov r1, r2 //*** save offset to next line in r0
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tst r3, #BIT_FIELD_TYPE //*** test odd or even field
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rsbeq r1, r1,#0 //*** negate offset if odd field to write to line above
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mov r5, #0x77000000 //*** extract OSD mask
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orr r5, #0x00770000
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orr r5, #0x00007700
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orr r5, #0x00000077
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mov r11, #540
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mul r11, r11, r2 //*** offset to second buffer used for comparison not for display
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process_chars_loop_7\@:
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// Initialize 8 pixel block
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mov r10, #0
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.if \psync_polarity == 1
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// Wait for 0-1 edge on PSYNC
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WAIT_FOR_PSYNC_1
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.else
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// Wait for 1-0 edge on PSYNC
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WAIT_FOR_PSYNC_0
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.endif
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// Pixel 0 in GPIO 4.. 2 -> 7.. 4
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// Pixel 1 in GPIO 7.. 5 -> 3.. 0
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// Pixel 2 in GPIO 10.. 8 -> 15..12
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// Pixel 3 in GPIO 13..11 -> 11.. 8
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and r9, r8, #(7 << PIXEL_BASE)
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orr r10, r10, r9, lsl #(4 - PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 3))
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orr r10, r10, r9, lsr #(3 + PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 6))
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orr r10, r10, r9, lsl #(6 - PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 9))
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orr r10, r10, r9, lsr #(1 + PIXEL_BASE)
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.if \psync_polarity == 1
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// Wait for 1-0 edge on PSYNC
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WAIT_FOR_PSYNC_0
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.else
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// Wait for 0-1 edge on PSYNC
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WAIT_FOR_PSYNC_1
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.endif
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// Pixel 4 in GPIO 4.. 2 -> 23..20
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// Pixel 5 in GPIO 7.. 5 -> 19..16
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// Pixel 6 in GPIO 10.. 8 -> 31..28
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// Pixel 7 in GPIO 13..11 -> 27..24
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and r9, r8, #(7 << PIXEL_BASE)
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orr r10, r10, r9, lsl #(20 - PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 3))
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orr r10, r10, r9, lsl #(13 - PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 6))
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orr r10, r10, r9, lsl #(22 - PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 9))
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orr r10, r10, r9, lsl #(15 - PIXEL_BASE)
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// constants set above:
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// r1 = offset to adjacent line in other field either above or below
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// r5 = bitmask 0x77777777 to extract OSD bits
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// r11 = offset to comparison buffer
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ldr r9, [r12,r11] //*** read old pixel value from comparison (2nd) buffer
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mov r0, r9 //*** move to r0 to extract OSD (mask in r5)
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bic r0, r5 //*** this won't work ATM as OSD need to be written to the comparison buffer
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orr r10, r0 //*** merge new pixel data and OSD
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str r10, [r12,r11] //*** save in comparison buffer
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//*** test for OSD required here. If enabled branch to skip_deinterlace\@ as deinterlace code messes up the OSD
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cmp r10, r9 //*** is new value same as old value?
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strne r10, [r12, r1] //*** if different then overwrite other field pixel value (offset above or below in r1)
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addne r8, r11, r2 //*** adjust pointer to next line in comparison buffer
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strne r10, [r12,r8] //*** if pixels different overwrite next line of comparison buffer (delays end of deinterlacing)
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skip_deinterlace\@:
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// Orr in the VSync indicator
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orr r10, r7
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str r10, [r12], #4 //*** write new pixel value to video buffer
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subs r6, r6, #1
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bne process_chars_loop_7\@
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pop {r1, r5, r11} //*** restore scratch registers
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exit_process_chars\@:
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.endm
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