From 300fd29dd3e24d9dbddbc1169d607ad9b70bbe6b Mon Sep 17 00:00:00 2001 From: IanSB Date: Wed, 30 Sep 2020 16:08:19 +0100 Subject: [PATCH] Update 24Mhz CPLD to V7.6 --- vhdl/RGBtoHDMI.vhdl | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/vhdl/RGBtoHDMI.vhdl b/vhdl/RGBtoHDMI.vhdl index 5fc44337..03e35d0c 100644 --- a/vhdl/RGBtoHDMI.vhdl +++ b/vhdl/RGBtoHDMI.vhdl @@ -64,8 +64,8 @@ architecture Behavorial of RGBtoHDMI is -- 4 = RGB CPLD (TTL) -- C = RGB CPLD (Analog) constant VERSION_NUM_BBC : std_logic_vector(11 downto 0) := x"066"; - constant VERSION_NUM_RGB_TTL : std_logic_vector(11 downto 0) := x"475"; - constant VERSION_NUM_RGB_ANALOG : std_logic_vector(11 downto 0) := x"C75"; + constant VERSION_NUM_RGB_TTL : std_logic_vector(11 downto 0) := x"476"; + constant VERSION_NUM_RGB_ANALOG : std_logic_vector(11 downto 0) := x"C76"; -- Sampling points constant INIT_SAMPLING_POINTS : std_logic_vector(23 downto 0) := "000000011011011011011011"; @@ -146,8 +146,6 @@ architecture Behavorial of RGBtoHDMI is begin old_mux <= mux when not(SupportAnalog) else '0'; - mode7 <= mode7_in when not(SupportAnalog) else rate(1) or not(rate(0)); - R <= R1 when old_mux = '1' else R0; G <= G1 when old_mux = '1' else G0; B <= B1 when old_mux = '1' else B0; @@ -161,7 +159,8 @@ begin half <= sp_reg(18); delay <= unsigned(sp_reg(20 downto 19)); rate <= sp_reg(22 downto 21); - invert <= sp_reg(23); + invert <= sp_reg(23) when not(SupportAnalog) else '0'; + mode7 <= mode7_in when not(SupportAnalog) else sp_reg(23); -- Shift the bits in LSB first process(sp_clk)