Alternative CPLD: de-glitch csync (needs to be low for 2 samples)

Change-Id: I010ac23689357444587944994f64cc6b8c04a7d4

vhdl_alt/RGBtoHDMI.vhdl

@@ -94,6 +94,7 @@ architecture Behavorial of RGBtoHDMI is
     signal shift_B  : std_logic_vector(3 downto 0);
 
     signal csync1   : std_logic;
+    signal csync2   : std_logic;
 
     -- The sampling counter runs at 96MHz
     -- - In modes 0..6 it is 6x  the pixel clock
@@ -186,9 +187,10 @@ begin
 
             -- synchronize CSYNC to the sampling clock
             csync1 <= S;
+            csync2 <= csync1;
 
             -- Counter is used to find sampling point for first pixel
-            if csync1 = '0' then
+            if csync1 = '0' and csync2 = '0' then
                 if mode7 = '1' then
                     if half = '1' then
                         counter <= mode7_offset_A;
@@ -211,7 +213,7 @@ begin
             end if;
 
             -- Sample point offset index
-            if csync1 = '0' then
+            if counter(11) = '1' then
                 index <= "000";
             else
                 -- so index offset changes at the same time counter wraps 7->0
@@ -322,6 +324,6 @@ begin
         end if;
     end process;
 
-    csync  <= S;      -- pass through, as clock might not be running
+    csync  <= csync1; -- output the registered version to save a macro-cell
 
 end Behavorial;

vhdl_alt/fitting.notes

@@ -268,3 +268,38 @@ FB3          18/18*      31/54       62/90       9/ 9*
 FB4          18/18*      49/54       71/90       6/ 7
              -----       -----       -----      -----
              72/72      140/216     216/360     28/34
+
+22. Final pinout changes - remove LED1 and LED2 as outputs
+
+(actually there was no change here, as the assignments to LED1/2 were always commented out)
+
+Function    Mcells      FB Inps     Pterms      IO
+Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot
+FB1          18/18*      33/54       45/90       6/ 9
+FB2          18/18*      27/54       38/90       8/ 9
+FB3          18/18*      31/54       62/90       9/ 9*
+FB4          18/18*      49/54       71/90       5/ 7
+             -----       -----       -----      -----
+             72/72      140/216     216/360     28/34
+
+23. Made csync output registered
+
+Function    Mcells      FB Inps     Pterms      IO
+Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot
+FB1          18/18*      33/54       45/90       6/ 9
+FB2          18/18*      27/54       38/90       8/ 9
+FB3          18/18*      31/54       62/90       9/ 9*
+FB4          17/18       49/54       70/90       5/ 7
+             -----       -----       -----      -----
+             71/72      140/216     215/360     28/34
+
+24. De-glitch csync (one additional register)
+
+Function    Mcells      FB Inps     Pterms      IO
+Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot
+FB1          18/18*      32/54       43/90       6/ 9
+FB2          18/18*      27/54       38/90       8/ 9
+FB3          18/18*      29/54       76/90       9/ 9*
+FB4          18/18*      49/54       75/90       5/ 7
+             -----       -----       -----      -----
+             72/72      137/216     232/360     28/34