kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Update simple mode menus
rodzic
851d7c65b1
commit
19c70aefa7
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@ -8,6 +8,7 @@
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typedef struct {
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int cpld_setup_mode;
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int all_offsets;
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int sp_offset[NUM_OFFSETS];
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int half_px_delay; // 0 = off, 1 = on, all modes
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int divider; // cpld divider, 6 or 8
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@ -96,7 +97,7 @@ enum {
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static const char *cpld_setup_names[] = {
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"Normal",
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"Set Delay"
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"Set Pixel H Offset"
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};
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static const char *edge_names[] = {
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@ -125,16 +126,16 @@ enum {
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static param_t params[] = {
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{ CPLD_SETUP_MODE, "Setup Mode", "setup_mode", 0,NUM_CPLD_SETUP-1, 1 },
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{ ALL_OFFSETS, "All Offsets", "all_offsets", 0, 7, 1 },
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{ A_OFFSET, "A Offset", "a_offset", 0, 7, 1 },
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{ B_OFFSET, "B Offset", "b_offset", 0, 7, 1 },
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{ C_OFFSET, "C Offset", "c_offset", 0, 7, 1 },
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{ D_OFFSET, "D Offset", "d_offset", 0, 7, 1 },
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{ E_OFFSET, "E Offset", "e_offset", 0, 7, 1 },
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{ F_OFFSET, "F Offset", "f_offset", 0, 7, 1 },
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{ HALF, "Half", "half", 0, 1, 1 },
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{ DIVIDER, "Divider", "divider", 6, 8, 2 },
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{ DELAY, "Delay", "delay", 0, 15, 1 },
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{ ALL_OFFSETS, "Sample Phase", "all_offsets", 0, 0, 1 },
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{ A_OFFSET, "A Phase", "a_offset", 0, 0, 1 },
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{ B_OFFSET, "B Phase", "b_offset", 0, 0, 1 },
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{ C_OFFSET, "C Phase", "c_offset", 0, 0, 1 },
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{ D_OFFSET, "D Phase", "d_offset", 0, 0, 1 },
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{ E_OFFSET, "E Phase", "e_offset", 0, 0, 1 },
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{ F_OFFSET, "F Phase", "f_offset", 0, 0, 1 },
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{ HALF, "Half Pixel Shift", "half", 0, 1, 1 },
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{ DIVIDER, "Clock Multiplier", "divider", 0, 3, 1 },
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{ DELAY, "Pixel H Offset", "delay", 0, 15, 1 },
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//block of hidden YUV options for file compatibility
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{ FILTER_L, "Filter Y", "l_filter", 0, 1, 1 },
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{ SUB_C, "Subsample UV", "sub_c", 0, 1, 1 },
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@ -252,7 +253,7 @@ static int cpld_get_value(int num) {
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case CPLD_SETUP_MODE:
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return config->cpld_setup_mode;
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case ALL_OFFSETS:
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return config->sp_offset[0];
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return config->all_offsets;
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case A_OFFSET:
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return config->sp_offset[0];
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case B_OFFSET:
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@ -334,6 +335,7 @@ static void cpld_set_value(int num, int value) {
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set_setup_mode(value);
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break;
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case ALL_OFFSETS:
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config->all_offsets = value;
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config->sp_offset[0] = value;
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config->sp_offset[1] = value;
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config->sp_offset[2] = value;
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@ -1481,8 +1481,8 @@ static void cpld_init() {
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// have to set mux to 0 to allow analog detection to work
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// so clock out 32 bits of 0 into register chain as later CPLDs have mux as a register bit
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int sp = 0b00011000000000000000000000; //sets the rate bits to 12bit capture for testing simple mode with amiga
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for (int i = 0; i < 26; i++) {
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int sp = 0b0000001100000000000011000000; //sets the rate bits to 12bit capture for testing simple mode with amiga
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for (int i = 0; i < 27; i++) {
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RPI_SetGpioValue(SP_DATA_PIN, sp & 1);
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delay_in_arm_cycles_cpu_adjust(250);
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RPI_SetGpioValue(SP_CLKEN_PIN, 1);
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