kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Pi Firmware: Added cpld_atom specific line capture (4bpp and 8bpp)
Change-Id: I2cd1a929231bdcad063c5e9db39e36642777a009pull/11/head
David Banks
rodzic
a40367459c
commit
0af1234a65
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@ -64,6 +64,8 @@ file( GLOB core_files
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rgb_to_fb.S
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capture_line_default_4bpp.S
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capture_line_default_8bpp.S
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capture_line_atom_4bpp.S
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capture_line_atom_8bpp.S
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capture_line_mode7_4bpp.S
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defs.h
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arm-exception.c
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@ -0,0 +1,70 @@
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#include "rpi-base.h"
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#include "defs.h"
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#include "macros.S"
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.text
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.global capture_line_atom_4bpp
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// The capture line function is provided the following:
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// r0 = pointer to current line in frame buffer
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// r1 = number of 8-pixel blocks to capture (=param_chars_per_line)
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// r2 = frame buffer line pitch in bytes (=param_fb_pitch)
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// r3 = flags register
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// r4 = GPLEV0 constant
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// r5 = frame buffer height (=param_fb_height)
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// r6 = scan line count modulo 10
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//
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// All registers are available as scratch registers (i.e. nothing needs to be preserved)
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capture_line_atom_4bpp:
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push {lr}
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mov r12, r0 // pointer to the line in the frame buffer
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mov r6, r1 // number of 8-bit characters per line
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loop:
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WAIT_FOR_PSYNC_10 // expects GPLEV0 in r4, result in r8
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// Pixel 0 in GPIO 4..2 -> 2..0
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// Pixel 1 in GPIO 8..6 -> 10..8
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and r10, r8, #(7 << PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 4))
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mov r10, r10, lsr #(PIXEL_BASE)
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orr r10, r10, r9, lsl #(8 - (4 + PIXEL_BASE))
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WAIT_FOR_PSYNC_01 // expects GPLEV0 in r4, result in r8
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// Pixel 0 in GPIO 4..2 -> 18..16
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// Pixel 1 in GPIO 8..6 -> 26..24
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and r9, r8, #(7 << PIXEL_BASE)
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and r14, r8, #(7 << (PIXEL_BASE + 4))
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orr r10, r10, r9, lsl #(16 - PIXEL_BASE)
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orr r10, r10, r14, lsl #(24 - (PIXEL_BASE + 4))
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// Now pixel double
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orr r10, r10, r10, lsl #4
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// Orr in the VSync indicator
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ldr r8, =0x11111111
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tst r3, #BIT_VSYNC_MARKER
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orrne r10, r10, r8
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// Line double always in Modes 0-6 regardless of interlace
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// On the multi core Pi this introduces stalling artefacts
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#ifndef HAS_MULTICORE
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tst r3, #BIT_SCANLINES
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movne r0, #0
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moveq r0, r10
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str r0, [r12, r2]
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#endif
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str r10, [r12], #4
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subs r6, r6, #1
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bne loop
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pop {pc}
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@ -0,0 +1,81 @@
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#include "rpi-base.h"
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#include "defs.h"
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#include "macros.S"
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.text
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.global capture_line_atom_8bpp
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.macro CAPTURE_BITS
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// Pixel 0 in GPIO 5.. 2 -> 15.. 8 and 7.. 0
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// Pixel 1 in GPIO 9.. 6 -> 31..24 and 23..16
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and r10, r8, #(15 << PIXEL_BASE)
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and r9, r8, #(15 << (PIXEL_BASE + 4))
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mov r10, r10, lsr #(PIXEL_BASE)
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orr r10, r10, r9, lsl #(16 - (PIXEL_BASE + 4))
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orr r10, r10, r10, lsl #8
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.endm
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// The capture line function is provided the following:
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// r0 = pointer to current line in frame buffer
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// r1 = number of 8-pixel blocks to capture (=param_chars_per_line)
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// r2 = frame buffer line pitch in bytes (=param_fb_pitch)
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// r3 = flags register
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// r4 = GPLEV0 constant
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// r5 = frame buffer height (=param_fb_height)
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// r6 = scan line count modulo 10
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//
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// All registers are available as scratch registers (i.e. nothing needs to be preserved)
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capture_line_atom_8bpp:
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push {lr}
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mov r12, r0 // pointer to the line in the frame buffer
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mov r6, r1 // number of 8-bit characters per line
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loop:
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WAIT_FOR_PSYNC_10
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CAPTURE_BITS
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// Orr in the VSync indicator
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ldr r8, =0x01010101
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tst r3, #BIT_VSYNC_MARKER
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orrne r10, r10, r8
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// Line double always in Modes 0-6 regardless of interlace
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// On the multi core Pi this introduces stalling artefacts
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#ifndef HAS_MULTICORE
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tst r3, #BIT_SCANLINES
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movne r0, #0
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moveq r0, r10
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str r0, [r12, r2]
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#endif
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str r10, [r12], #4
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WAIT_FOR_PSYNC_01
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CAPTURE_BITS
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// Orr in the VSync indicator
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ldr r8, =0x01010101
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tst r3, #BIT_VSYNC_MARKER
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orrne r10, r10, r8
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// Line double always in Modes 0-6 regardless of interlace
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// On the multi core Pi this introduces stalling artefacts
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#ifndef HAS_MULTICORE
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tst r3, #BIT_SCANLINES
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movne r0, #0
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moveq r0, r10
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str r0, [r12, r2]
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#endif
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str r10, [r12], #4
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subs r6, r6, #1
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bne loop
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exit:
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pop {pc}
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@ -7,6 +7,7 @@
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#include "cpld.h"
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#include "osd.h"
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#include "logging.h"
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#include "rgb_to_fb.h"
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#include "rpi-gpio.h"
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#define RANGE 16
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@ -173,6 +174,13 @@ static void cpld_calibrate(capture_info_t *capinfo, int elk) {
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static void cpld_set_mode(capture_info_t *capinfo, int mode) {
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write_config(config);
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if (capinfo) {
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if (capinfo->bpp == 8) {
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capinfo->capture_line = capture_line_atom_8bpp;
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} else {
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capinfo->capture_line = capture_line_atom_4bpp;
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}
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}
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}
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static param_t *cpld_get_params() {
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@ -53,7 +53,8 @@ static const char *palette_names[] = {
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"Just Blue",
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"Not Red",
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"Not Green",
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"Not Blue"
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"Not Blue",
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"Atom"
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};
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static const char *pllh_names[] = {
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@ -741,6 +742,12 @@ void osd_update_palette() {
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g = (i & 3) * 255 / 3;
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b = 0;
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break;
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case PALETTE_ATOM:
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// In the Atom CPLD, colour bit 3 indicates a half green
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if (i & 8) {
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g >>= 1;
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}
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break;
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}
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if (active) {
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if (i >= (num_colours >> 1)) {
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@ -30,6 +30,7 @@ enum {
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PALETTE_NOT_RED,
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PALETTE_NOT_GREEN,
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PALETTE_NOT_BLUE,
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PALETTE_ATOM,
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NUM_PALETTES
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};
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@ -15,6 +15,10 @@ extern int sw2counter;
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extern int sw3counter;
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extern int capture_line_atom_4bpp();
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extern int capture_line_atom_8bpp();
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extern int capture_line_default_4bpp();
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extern int capture_line_default_8bpp();
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@ -102,6 +102,7 @@
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# - 7 is Not Red
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# - 8 is Not Green
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# - 9 is Not Blue
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# - 10 is Atom
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#
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# deinterlace: algorithm used for mode 7 deinterlacing
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# - 0 is None
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@ -189,7 +190,7 @@ sampling06=3 sampling7=0,2,2,2,2,2,2,0,8,5 info=1 palette=0 deinterlace=5 scanli
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#sampling06=0,5,5,5,5,5,5,0 geometry06=24,16,76,240,608,480,4,85909091,5472,524 nbuffers=2 m7disable=1
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#
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# Here's an example that might work with an Atom (Atom CPLD)
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#sampling06=2 geometry06=19,11,76,240,608,480,4,57272720,3648,524 nbuffers=2 m7disable=1 keymap=1233232
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#sampling06=0 geometry06=19,11,76,240,608,480,8,57272720,3648,524 palette=10 nbuffers=2 m7disable=1 keymap=1233232
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#
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# Here's an example that might work with a ZX80/ZX81
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#sampling06=0,4,4,4,4,4,4,0 geometry06=9,18,84,270,672,540,4,78000000,4968,620 nbuffers=2 m7disable=1 keymap=1323232 return=0
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