kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Alternative CPLD: Copied latest code across from dev2 branch
Change-Id: I2e2523c40f2e67acf8cfcf9450e80fa85e882307issue_1022
David Banks
rodzic
9f37dafa12
commit
01bed22f12
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@ -2,6 +2,8 @@
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*~
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vhdl/iseconfig/
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vhdl/working/
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vhdl_alt/iseconfig/
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vhdl_alt/working/
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src/scripts/CMakeCache.txt
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src/scripts/CMakeFiles/
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@ -25,8 +25,8 @@ void RPI_SetGpioInput(rpi_gpio_pin_t gpio)
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rpi_gpio_value_t RPI_GetGpioValue(rpi_gpio_pin_t gpio)
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{
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rpi_gpio_value_t result = RPI_IO_UNKNOWN;
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uint32_t result;
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switch (gpio / 32)
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{
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case 0:
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@ -38,16 +38,15 @@ rpi_gpio_value_t RPI_GetGpioValue(rpi_gpio_pin_t gpio)
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break;
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default:
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return RPI_IO_UNKNOWN;
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break;
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}
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if (result != RPI_IO_UNKNOWN)
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{
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if (result)
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result = RPI_IO_HI;
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if (result) {
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return RPI_IO_HI;
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} else {
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return RPI_IO_LO;
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}
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return result;
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}
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void RPI_ToggleGpio(rpi_gpio_pin_t gpio)
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@ -0,0 +1,71 @@
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# Global Clock Nets
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NET "clk" BUFG=CLK;
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# Global Clock Nets
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NET "sp_clk" BUFG=CLK;
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# 96MHz clock domain
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NET "clk" TNM_NET = clk_period_grp_1;
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TIMESPEC TS_clk_period_1 = PERIOD "clk_period_grp_1" 10.4ns HIGH;
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# 10MHz clock domain
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#NET "sp_clk" TNM_NET = clk_period_grp_2;
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#TIMESPEC TS_clk_period_2 = PERIOD "clk_period_grp_2" 100ns HIGH;
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NET "clk" LOC = "P43"; # input gpio21
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NET "R0" LOC = "P33"; # input
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NET "G0" LOC = "P32"; # input
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NET "B0" LOC = "P31"; # input
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NET "R1" LOC = "P34"; # input
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NET "G1" LOC = "P36"; # input
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NET "B1" LOC = "P37"; # input
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NET "S" LOC = "P30"; # input
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NET "SW1" LOC = "P39"; # input gpio16
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NET "SW2" LOC = "P40"; # input gpio26
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NET "SW3" LOC = "P41"; # input gpio19
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NET "link" LOC = "P42"; # input gpio25 (connects to link / test point)
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NET "spare" LOC = "P3"; # input gpio12
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NET "mode7" LOC = "P19"; # input gpio22
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NET "elk" LOC = "P18"; # input gpio24
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NET "sp_clk" LOC = "P44"; # input gpio20
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NET "sp_data" LOC = "P20"; # input gpio23
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NET "sp_clken" LOC = "P1"; # input gpio13
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NET "quad(0)" LOC = "P7"; # output gpio0
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NET "quad(1)" LOC = "P6"; # output gpio1
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NET "quad(2)" LOC = "P29"; # output gpio2
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NET "quad(3)" LOC = "P28"; # output gpio3
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NET "quad(4)" LOC = "P27"; # output gpio4
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NET "quad(5)" LOC = "P5"; # output gpio5
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NET "quad(6)" LOC = "P2"; # output gpio6
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NET "quad(7)" LOC = "P8"; # output gpio7
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NET "quad(8)" LOC = "P12"; # output gpio8
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NET "quad(9)" LOC = "P14"; # output gpio9
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NET "quad(10)" LOC = "P16"; # output gpio10
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NET "quad(11)" LOC = "P13"; # output gpio11
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NET "psync" LOC = "P22"; # output gpio17
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NET "csync" LOC = "P23"; # output gpio18
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NET "LED1" LOC = "P21"; # output gpio27 (bidirectional, driven from Pi)
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NET "LED2" LOC = "P38"; # output to LED2 (used as mode 7 indicator)
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NET "quad(0)" SLOW;
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NET "quad(1)" SLOW;
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NET "quad(2)" SLOW;
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NET "quad(3)" SLOW;
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NET "quad(4)" SLOW;
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NET "quad(5)" SLOW;
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NET "quad(6)" SLOW;
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NET "quad(7)" SLOW;
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NET "quad(8)" SLOW;
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NET "quad(9)" SLOW;
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NET "quad(10)" SLOW;
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NET "quad(11)" SLOW;
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NET "psync" SLOW;
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NET "csync" SLOW;
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NET "LED1" SLOW;
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NET "LED2" SLOW;
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@ -0,0 +1,280 @@
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----------------------------------------------------------------------------------
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-- Engineer: David Banks
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--
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-- Create Date: 14/4/2017
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-- Module Name: RGBtoHDMI CPLD
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-- Project Name: RGBtoHDMI
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-- Target Devices: XC9572XL
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--
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-- Version: 0.50
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity RGBtoHDMI is
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Port (
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-- From Beeb RGB Connector
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R0: in std_logic;
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G0: in std_logic;
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B0: in std_logic;
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R1: in std_logic;
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G1: in std_logic;
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B1: in std_logic;
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S: in std_logic;
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-- From Pi
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clk: in std_logic;
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mode7: in std_logic;
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elk: in std_logic;
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sp_clk: in std_logic;
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sp_clken: in std_logic;
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sp_data: in std_logic;
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-- To PI GPIO
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quad: out std_logic_vector(11 downto 0);
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psync: out std_logic;
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csync: out std_logic;
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-- User interface
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SW1: in std_logic;
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SW2: in std_logic; -- currently unused
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SW3: in std_logic; -- currently unused
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spare: in std_logic; -- currently unused
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link: in std_logic; -- currently unused
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LED1: out std_logic;
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LED2: out std_logic
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);
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end RGBtoHDMI;
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architecture Behavorial of RGBtoHDMI is
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-- For Modes 0..6
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constant default_offset : unsigned(11 downto 0) := to_unsigned(4096 - 64 * 17 + 6, 12);
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-- For Mode 7
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constant mode7_offset : unsigned(11 downto 0) := to_unsigned(4096 - 96 * 12 + 4, 12);
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-- Sampling points
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constant INIT_SAMPLING_POINTS : std_logic_vector(20 downto 0) := "000000000000011011011";
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signal shift_R : std_logic_vector(3 downto 0);
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signal shift_G : std_logic_vector(3 downto 0);
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signal shift_B : std_logic_vector(3 downto 0);
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signal CSYNC1 : std_logic;
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-- The sampling counter runs at 96MHz
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-- - In modes 0..6 it is 6x the pixel clock
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-- - In mode 7 it is 8x the pixel clock
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--
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-- It serves several purposes:
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-- 1. Counts the 12us between the rising edge of nCSYNC and the first pixel
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-- 2. Counts within each pixel (bits 0, 1, 2)
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-- 3. Counts counts pixels within a quad pixel (bits 3 and 4)
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-- 4. Handles double buffering of alternative quad pixels (bit 5)
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--
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-- At the moment we don't count pixels with the line, the Pi does that
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signal counter : unsigned(11 downto 0);
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-- Sample point register;
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--
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-- In Modes 0..6 each pixel lasts 6 clocks (96MHz / 16MHz). The original
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-- pixel clock is a clean 16Mhz clock, so only one sample point is needed.
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--
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-- In Mode 7 each pixel lasts 8 clocks (96MHz / 12MHz). The original
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-- pixel clock is a regenerated 6Mhz clock, and both edges are used.
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-- Due to the way it is generated, there are three distinct phases,
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-- hence three sampling points are used.
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signal sp_reg : std_logic_vector(20 downto 0) := INIT_SAMPLING_POINTS;
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-- Break out of sp
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signal delay_R : std_logic_vector(2 downto 0);
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signal delay_G : std_logic_vector(2 downto 0);
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signal delay_B : std_logic_vector(2 downto 0);
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signal offset_A : std_logic_vector(1 downto 0);
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signal offset_B : std_logic_vector(1 downto 0);
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signal offset_C : std_logic_vector(1 downto 0);
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signal offset_D : std_logic_vector(1 downto 0);
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signal offset_E : std_logic_vector(1 downto 0);
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signal offset_F : std_logic_vector(1 downto 0);
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signal offset : std_logic_vector(1 downto 0);
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signal adjusted_counter : unsigned(2 downto 0);
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-- Index to allow cycling between A, B and C in Mode 7
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signal sp_index : std_logic_vector(2 downto 0);
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-- Sample pixel on next clock; pipelined to reduce the number of product terms
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signal sample_R : std_logic;
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signal sample_G : std_logic;
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signal sample_B : std_logic;
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signal R : std_logic;
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signal G : std_logic;
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signal B : std_logic;
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begin
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R <= R1 when elk = '1' else R0;
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G <= G1 when elk = '1' else G0;
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B <= B1 when elk = '1' else B0;
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delay_R <= sp_reg(2 downto 0);
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delay_G <= sp_reg(5 downto 3);
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delay_B <= sp_reg(8 downto 6);
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offset_A <= sp_reg(10 downto 9);
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offset_B <= sp_reg(12 downto 11);
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offset_C <= sp_reg(14 downto 13);
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offset_D <= sp_reg(16 downto 15);
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offset_E <= sp_reg(18 downto 17);
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offset_F <= sp_reg(20 downto 19);
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-- Shift the bits in LSB first
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process(sp_clk, SW1)
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begin
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if rising_edge(sp_clk) then
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if sp_clken = '1' then
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sp_reg <= sp_data & sp_reg(sp_reg'left downto sp_reg'right + 1);
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end if;
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end if;
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end process;
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process(clk)
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begin
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if rising_edge(clk) then
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-- synchronize CSYNC to the sampling clock
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CSYNC1 <= S;
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-- Counter is used to find sampling point for first pixel
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if CSYNC1 = '0' then
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if mode7 = '1' then
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counter <= mode7_offset;
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else
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counter <= default_offset;
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end if;
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elsif counter(11) = '1' then
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counter <= counter + 1;
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elsif mode7 = '1' or counter(2 downto 0) /= 5 then
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counter(5 downto 0) <= counter(5 downto 0) + 1;
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else
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counter(5 downto 0) <= counter(5 downto 0) + 3;
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end if;
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-- Sample point offset index
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if CSYNC1 = '0' then
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sp_index <= "000";
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else
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-- so index offset changes at the same time counter wraps 7->0
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if counter(2 downto 0) = 6 then
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case sp_index is
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when "000" =>
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sp_index <= "001";
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when "001" =>
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sp_index <= "010";
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when "010" =>
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sp_index <= "011";
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when "011" =>
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sp_index <= "100";
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when "100" =>
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sp_index <= "101";
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when others =>
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sp_index <= "000";
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end case;
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end if;
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end if;
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-- Sample point offset
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case sp_index is
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when "000" =>
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offset <= offset_B;
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when "001" =>
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offset <= offset_C;
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when "010" =>
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offset <= offset_D;
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when "011" =>
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offset <= offset_E;
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when "100" =>
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offset <= offset_F;
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when others =>
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offset <= offset_A;
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end case;
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-- Adjusted counter is the counter value with the offset added in
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--
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-- The offset is sign extended offset to 3 bits so values are:
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-- 00 -> 000 (0)
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-- 01 -> 001 (1)
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-- 10 -> 110 (-2)
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-- 11 -> 111 (-1)
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adjusted_counter <= counter(2 downto 0) + unsigned(offset(1) & offset(1 downto 0));
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-- R sample/shift control
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if counter(11) = '0' and adjusted_counter(2 downto 0) = unsigned(delay_R) then
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sample_R <= '1';
|
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else
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sample_R <= '0';
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end if;
|
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-- G sample/shift control
|
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if counter(11) = '0' and adjusted_counter(2 downto 0) = unsigned(delay_G) then
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sample_G <= '1';
|
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else
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sample_G <= '0';
|
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end if;
|
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|
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-- B sample/shift control
|
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if counter(11) = '0' and adjusted_counter(2 downto 0) = unsigned(delay_B) then
|
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sample_B <= '1';
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else
|
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sample_B <= '0';
|
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end if;
|
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|
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-- R Sample/shift register
|
||||
if sample_R = '1' then
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shift_R <= R & shift_R(3 downto 1);
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end if;
|
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|
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-- G Sample/shift register
|
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if sample_G = '1' then
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shift_G <= G & shift_G(3 downto 1);
|
||||
end if;
|
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|
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-- B Sample/shift register
|
||||
if sample_B = '1' then
|
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shift_B <= B & shift_B(3 downto 1);
|
||||
end if;
|
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|
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-- Output quad register
|
||||
if counter(11) = '0' then
|
||||
if counter(4 downto 0) = "00001" then
|
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quad(11) <= shift_B(3);
|
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quad(10) <= shift_G(3);
|
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quad(9) <= shift_R(3);
|
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quad(8) <= shift_B(2);
|
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quad(7) <= shift_G(2);
|
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quad(6) <= shift_R(2);
|
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quad(5) <= shift_B(1);
|
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quad(4) <= shift_G(1);
|
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quad(3) <= shift_R(1);
|
||||
quad(2) <= shift_B(0);
|
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quad(1) <= shift_G(0);
|
||||
quad(0) <= shift_R(0);
|
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psync <= counter(5);
|
||||
end if;
|
||||
else
|
||||
quad <= (others => '0');
|
||||
psync <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
csync <= S; -- pass through, as clock might not be running
|
||||
--LED1 <= 'Z'; -- allow this to be driven from the Pi
|
||||
--LED2 <= not(mode7);
|
||||
|
||||
end Behavorial;
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="RGBtoHDMI.vhdl" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="RGBtoHDMI.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="None" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|RGBtoHDMI|Behavorial" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../RGBtoHDMI.vhdl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/RGBtoHDMI" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="RGBtoHDMI" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="RGBtoHDMI_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="RGBtoHDMI_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="RGBtoHDMI_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="RGBtoHDMI_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="RGBtoHDMI" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Detail" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="RGBtoHDMI" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-04-24T12:02:15" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D441DEAB1BF331CCD57BEACA4EE893A0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -0,0 +1,248 @@
|
|||
1. Original design:
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 27/54 69/90 6/ 9
|
||||
FB2 18/18* 34/54 60/90 8/ 9
|
||||
FB3 18/18* 19/54 32/90 5/ 9
|
||||
FB4 18/18* 37/54 56/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
72/72 117/216 217/360 26/34
|
||||
|
||||
|
||||
2. New design, with RGB mux, switch pass throughs, etc commented out
|
||||
(failed to map sp_reg<9>, hence one less macrocell)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 26/54 51/90 7/ 9
|
||||
FB2 18/18* 25/54 33/90 6/ 9
|
||||
FB3 18/18* 35/54 61/90 8/ 9
|
||||
FB4 17/18 53/54 70/90 4/ 7
|
||||
----- ----- ----- -----
|
||||
71/72 139/216 215/360 25/34
|
||||
|
||||
|
||||
3. Change from csync=>S to csync=>CSYNC1 (as passthroughs still use up a macro cell).
|
||||
(now fits)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 17/18 33/54 64/90 7/ 9
|
||||
FB2 18/18* 25/54 33/90 6/ 9
|
||||
FB3 18/18* 35/54 61/90 8/ 9
|
||||
FB4 18/18* 37/54 58/90 4/ 7
|
||||
----- ----- ----- -----
|
||||
71/72 130/216 216/360 25/34
|
||||
|
||||
|
||||
4. Add in RGB mux:
|
||||
(still fits)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 17/18 33/54 64/90 7/ 9
|
||||
FB2 18/18* 25/54 33/90 9/ 9*
|
||||
FB3 18/18* 37/54 61/90 8/ 9
|
||||
FB4 18/18* 41/54 61/90 5/ 7
|
||||
----- ----- ----- -----
|
||||
71/72 136/216 219/360 29/34
|
||||
|
||||
5. Add in SW2out <= SW2:
|
||||
(still fits)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 28/54 62/90 8/ 9
|
||||
FB2 18/18* 25/54 33/90 9/ 9*
|
||||
FB3 18/18* 37/54 61/90 8/ 9
|
||||
FB4 18/18* 48/54 64/90 6/ 7
|
||||
----- ----- ----- -----
|
||||
72/72 138/216 220/360 31/34
|
||||
|
||||
6. Change to optimization effort normal->high:
|
||||
(no difference)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 28/54 62/90 8/ 9
|
||||
FB2 18/18* 25/54 33/90 9/ 9*
|
||||
FB3 18/18* 37/54 61/90 8/ 9
|
||||
FB4 18/18* 48/54 64/90 6/ 7
|
||||
----- ----- ----- -----
|
||||
72/72 138/216 220/360 31/34
|
||||
|
||||
7. Change to optimization effort speed->area:
|
||||
(no difference)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 28/54 62/90 8/ 9
|
||||
FB2 18/18* 25/54 33/90 9/ 9*
|
||||
FB3 18/18* 37/54 61/90 8/ 9
|
||||
FB4 18/18* 48/54 64/90 6/ 7
|
||||
----- ----- ----- -----
|
||||
72/72 138/216 220/360 31/34
|
||||
|
||||
8. Fitter Implmenetation Template: Optimize Balance-> Optimize Speed:
|
||||
(no difference)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 28/54 62/90 8/ 9
|
||||
FB2 18/18* 25/54 33/90 9/ 9*
|
||||
FB3 18/18* 37/54 61/90 8/ 9
|
||||
FB4 18/18* 48/54 64/90 6/ 7
|
||||
----- ----- ----- -----
|
||||
72/72 138/216 220/360 31/34
|
||||
|
||||
|
||||
9. Fitter Implmenetation Template: Optimize Speed -> Optimize Density:
|
||||
(no difference)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 28/54 62/90 8/ 9
|
||||
FB2 18/18* 25/54 33/90 9/ 9*
|
||||
FB3 18/18* 37/54 61/90 8/ 9
|
||||
FB4 18/18* 48/54 64/90 6/ 7
|
||||
----- ----- ----- -----
|
||||
72/72 138/216 220/360 31/34
|
||||
|
||||
10. Reverted to original .xise file
|
||||
Cleaned up design to remove SW2/3 pass throughs
|
||||
Used gpio22/23 for mode7 / sp_data
|
||||
Used gpio19/26 for sw2/3 (not via cpld)
|
||||
(same result as 4 above)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 17/18 33/54 64/90 5/ 9
|
||||
FB2 18/18* 25/54 33/90 9/ 9*
|
||||
FB3 18/18* 37/54 61/90 8/ 9
|
||||
FB4 18/18* 41/54 61/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
71/72 136/216 219/360 29/34
|
||||
|
||||
11. Final design on 5/6/2018
|
||||
|
||||
(Added SW2, SW3, Link as unused inputs)
|
||||
(Added LED1 as output, driven to Z, still uses one macro cell)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 27/54 61/90 5/ 9
|
||||
FB2 18/18* 25/54 33/90 9/ 9*
|
||||
FB3 18/18* 37/54 61/90 9/ 9*
|
||||
FB4 18/18* 48/54 64/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
72/72 137/216 219/360 30/34
|
||||
|
||||
12. Minor changes 1.15pm on 5/5/2018
|
||||
|
||||
(Removed SW1Out passthrough)
|
||||
(csync output is back to being passthrough)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 25/54 35/90 4/ 9
|
||||
FB2 18/18* 34/54 65/90 9/ 9*
|
||||
FB3 18/18* 37/54 61/90 9/ 9*
|
||||
FB4 18/18* 39/54 58/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
72/72 135/216 219/360 29/34
|
||||
|
||||
13. Removed SW1 from sp_reg assignment block
|
||||
|
||||
(the is prone to noise on the prototype, as it clamped at 2V by an LED)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 25/54 35/90 3/ 9
|
||||
FB2 18/18* 34/54 65/90 9/ 9*
|
||||
FB3 18/18* 37/54 61/90 9/ 9*
|
||||
FB4 18/18* 39/54 58/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
72/72 135/216 219/360 28/34
|
||||
|
||||
14. Added sp_clken and spare
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 30/54 63/90 5/ 9
|
||||
FB2 18/18* 26/54 46/90 9/ 9*
|
||||
FB3 18/18* 35/54 60/90 8/ 9
|
||||
FB4 18/18* 47/54 71/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
72/72 138/216 240/360 29/34
|
||||
|
||||
15. Replaced counter2(5..3) with load saving two registers
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 40/54 72/90 5/ 9
|
||||
FB2 17/18 24/54 49/90 9/ 9*
|
||||
FB3 18/18* 34/54 60/90 8/ 9
|
||||
FB4 17/18 35/54 63/90 7/ 7*
|
||||
----- ----- ----- -----
|
||||
70/72 133/216 244/360 29/34
|
||||
|
||||
16. Alternative design
|
||||
(after lots of messing to get it to route)
|
||||
(timing rubbush, 18ns)
|
||||
(68 registers)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 34/54 53/90 4/ 9
|
||||
FB2 18/18* 26/54 36/90 8/ 9
|
||||
FB3 18/18* 30/54 50/90 9/ 9*
|
||||
FB4 16/18 38/54 86/90 6/ 7
|
||||
----- ----- ----- -----
|
||||
70/72 128/216 225/360 27/34
|
||||
|
||||
17. Repipelined offset and alternative_counter to improve timing
|
||||
|
||||
(note big reduction in product term usage)
|
||||
(70 registers)
|
||||
(11.0ns)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 35/54 45/90 4/ 9
|
||||
FB2 17/18 25/54 35/90 8/ 9
|
||||
FB3 18/18* 30/54 50/90 9/ 9*
|
||||
FB4 18/18* 42/54 66/90 6/ 7
|
||||
----- ----- ----- -----
|
||||
71/72 132/216 196/360 27/34
|
||||
|
||||
18. Sign extended offset to 3-bits
|
||||
|
||||
(surprisingly no change in resource usage)
|
||||
(70 registers)
|
||||
(11.0ns)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 35/54 45/90 4/ 9
|
||||
FB2 17/18 25/54 35/90 8/ 9
|
||||
FB3 18/18* 30/54 50/90 9/ 9*
|
||||
FB4 18/18* 42/54 66/90 6/ 7
|
||||
----- ----- ----- -----
|
||||
71/72 132/216 196/360 27/34
|
||||
|
||||
19. Adjust pipelining timing
|
||||
|
||||
(sp_index when counter = 6 rather than 7)
|
||||
(load when counter = 1 rather than 1)
|
||||
(70 registers)
|
||||
(11.0ns)
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 35/54 45/90 4/ 9
|
||||
FB2 17/18 25/54 35/90 8/ 9
|
||||
FB3 18/18* 30/54 50/90 9/ 9*
|
||||
FB4 18/18* 42/54 66/90 6/ 7
|
||||
----- ----- ----- -----
|
||||
71/72 132/216 196/360 27/34
|
||||
Ładowanie…
Reference in New Issue