kopia lustrzana https://github.com/roncarr880/QRP_LABS_WSPR
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@ -16,8 +16,6 @@
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// R dividers in the SI5351. Dividers 1 - rx and 4 - tx will cover 1mhz to 30mhz
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// Dividers 16 - rx and 64 - tx will cover 40 khz to 2 mhz
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#include <Wire.h>
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#include <FreqCount.h> // one UNO I have does not work correctly with this library, another one does
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#include <EEPROM.h>
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@ -117,8 +115,8 @@ uint8_t frame_sec; // frame timer counts 0 to 120
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int frame_msec;
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// long before the wwvb gets a complete decode, the clock syncs up to the signal. Use this to remove the
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// drift in the time keeping.
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#define FF -4 // precalculated constant offset, -14?
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// drift in the time keeping. lose gain
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#define FF -7 // precalculated constant offset, -14 -9 | -4
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int cal_ff; // calibrate fudge factor
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int cal_vals[16];
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uint8_t cal_i;
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@ -160,8 +158,7 @@ void setup() {
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uint8_t i;
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Serial.begin(1200); // TenTec Argo V baud rate
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Wire.begin();
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// Wire.setClock(400000); // should work but clock 1 starts on the wrong frequency
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i2init();
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ee_restore(); // get default freq for frame mode from eeprom
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@ -261,6 +258,7 @@ void loop() {
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static unsigned long ms;
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if( Serial.availableForWrite() > 20 ) radio_control();
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i2poll();
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if( ms != millis()){ // run once each ms
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ms = millis();
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@ -473,9 +471,13 @@ uint8_t i;
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// else clock_freq += 100; // but may toggle because of the jitter
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// si_pll_x(PLLB,cal_freq,cal_divider,0); // calibrate frequency on clock 2
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// si_pll_x(PLLA,Rdiv*4*freq,divider,0); // receiver 4x clock
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frame_sec = 60; // set seconds to the correct time
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frame_msec = 0;
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for( i = 0; i < 16; ++i ) cal_vals[i] = 0;
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if( frame_sec == 59 && frame_msec >= 500 ) ; // let it float
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else if( frame_sec == 60 && frame_msec < 500 ) ; // let it ride
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else{ // way off, reset to the correct time
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frame_sec = 60;
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frame_msec = 0;
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for( i = 0; i < 16; ++i ) cal_vals[i] = 0;
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}
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// }
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}
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@ -641,10 +643,11 @@ void tx_off(){
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void i2cd( unsigned char addr, unsigned char reg, unsigned char dat ){
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// direct register writes. A possible speed up could be realized if one were
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// to use the auto register inc feature of the SI5351
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Wire.beginTransmission(addr);
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Wire.write(reg);
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Wire.write(dat);
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Wire.endTransmission();
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i2start(addr);
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i2send(reg);
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i2send(dat);
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i2stop();
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}
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@ -936,5 +939,113 @@ char cmd2;
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}
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/***** non-blocking, write only, I2C functions ******/
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#define I2BUFSIZE 64
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int i2buf[I2BUFSIZE];
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uint8_t i2in, i2out;
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// use some upper bits in the buffer for control
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#define ISTART 0x100
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#define ISTOP 0x200
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void i2init()
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{
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TWBR = 72; // 12 400k for 16 meg clock. 72 100k ((F_CPU/freq)-16)/2
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TWSR = 0;
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TWDR = 0xFF;
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PRR = 0;
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}
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void i2start( unsigned char adr ){
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int dat;
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// shift the address over and add the start flag
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dat = ( adr << 1 ) | ISTART;
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i2send( dat );
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}
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void i2send( int data ){ // just save stuff in the buffer
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uint8_t t;
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// but check for space first
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t = ( i2in + 1 ) & (I2BUFSIZE - 1);
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while( t == i2out ) i2poll(); // wait for space
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i2buf[i2in++] = data;
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i2in &= (I2BUFSIZE - 1);
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}
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void i2stop( ){
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i2send( ISTOP ); // que a stop condition
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}
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/*
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void i2flush(){ // call poll to empty out the buffer.
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while( i2poll() );
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}
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*/
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uint8_t i2poll(){ // everything happens here. Call this from loop.
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static uint8_t state = 0;
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static int data;
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static uint8_t delay_counter;
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// the library code has a delay after loading the transmit buffer
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// and before the status bits are tested for transmit active
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if( delay_counter ){
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--delay_counter;
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return (16 + delay_counter);
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}
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switch( state ){
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case 0: // idle state or between characters
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if( i2in != i2out ){ // get next character
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data = i2buf[i2out++];
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i2out &= (I2BUFSIZE - 1 );
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if( data & ISTART ){ // start
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data &= 0xff;
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// set start condition
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TWCR = (1<<TWINT) | (1<<TWSTA) | (1<<TWEN);
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state = 1;
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}
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else if( data & ISTOP ){ // stop
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// set stop condition
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TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO);
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state = 3;
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}
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else{ // just data to send
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TWDR = data;
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TWCR = (1<<TWINT) | (1<<TWEN);
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delay_counter = 10; // delay for transmit active to come true
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state = 2;
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}
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}
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break;
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case 1: // wait for start to clear, send saved data which has the address
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if( (TWCR & (1<<TWINT)) ){
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state = 2;
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TWDR = data;
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TWCR = (1<<TWINT) | (1<<TWEN);
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delay_counter = 10;
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}
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break;
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case 2: // wait for ack/nack done and tbuffer empty, blind to success or fail
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if( (TWCR & (1<<TWINT)) ){
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state = 0;
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}
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break;
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case 3: // wait for stop to clear
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if( (TWCR & (1<<TWSTO)) == 0 ){
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state = 0;
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delay_counter = 10; // a little delay at the end of a sequence
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}
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break;
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}
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if( i2in != i2out ) return (state + 8);
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else return state;
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}
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