kopia lustrzana https://github.com/roncarr880/QRP_LABS_WSPR
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@ -37,6 +37,12 @@
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#define MUTE A1 // receiver module T/R switch pin
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#define MUTE A1 // receiver module T/R switch pin
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#define START_CLOCK_FREQ 2700446600 // *100 for setting fractional frequency
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#define START_CLOCK_FREQ 2700446600 // *100 for setting fractional frequency
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// master clock update period and amount to change. Update based upon WWVB sync on falling edge routine.
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// values of 10 and 16 will change the clock about 1hz per hour.
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// values of 10 and 1 will change about 1hz per 16 hours.
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#define CLK_UPDATE_MIN 10
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#define CLK_UPDATE_AMT 1
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#define stage(c) Serial.write(c)
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#define stage(c) Serial.write(c)
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@ -552,16 +558,16 @@ static int8_t time_trend; // a change of +-100 is 1hz change
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uint8_t changed;
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uint8_t changed;
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static uint8_t holdoff;
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static uint8_t holdoff;
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if( holdoff < 180 ){
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if( holdoff < 180 ){ // inhibit correction when 1st starting
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++holdoff;
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++holdoff;
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return;
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return;
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}
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}
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if( wspr_tx_enable ) return; // ignore this when transmitting
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if( wspr_tx_enable ) return; // ignore this when transmitting
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changed = 0;
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changed = 0;
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time_trend -= val; // !!! val : add or sub for correct correction?
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time_trend -= val;
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if( time_trend > 10 ) clock_freq -= 16, changed = 1; // 10,16 gives max 1hz/hr change
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if( time_trend > CLK_UPDATE_MIN ) clock_freq -= CLK_UPDATE_AMT, changed = 1;
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if( time_trend < -10 ) clock_freq += 16, changed = 1;
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if( time_trend < -CLK_UPDATE_MIN ) clock_freq += CLK_UPDATE_AMT, changed = 1;
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if( changed ){ // set new dividers for the new master clock freq value to take effect
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if( changed ){ // set new dividers for the new master clock freq value to take effect
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time_trend = 0;
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time_trend = 0;
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