kopia lustrzana https://github.com/roncarr880/QRP_LABS_WSPR
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@ -9,45 +9,49 @@
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// Tune to one of the magic WSPR frequencies and toggle TX (tune in wsjt will work).
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// The new frequency will be stored in EEPROM.
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// If using the band hopping feature of WSJT, disable the EEPROM writes, function ee_save().
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//
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// A 4:1 frequency relationship between the tx freq and the rx clock is maintained using the
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// post dividers aka R dividers in the SI5351. Dividers 1 - rx and 4 - tx will cover 1mhz to 30mhz
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// Dividers 16 - rx and 64 - tx will cover 40 khz to 2 mhz
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// To Do:
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// !!! extend lower freq limit down to 60 khz for wwvb
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#include <Wire.h>
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#include <FreqCount.h> // one UNO I have does not work correctly with this library, another one does
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#include <EEPROM.h>
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#define SI5351 0x60 // i2c address
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#define PLLA 26 // register address offsets for PLL's
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#define PLLA 26 // register address offsets for PLL's
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#define PLLB 34
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#define CLK0_EN 1
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#define CLK1_EN 2
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#define CLK2_EN 4
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// the starting frequency will be read out of EEPROM except the 1st time when EEPROM is blank
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#define FREQ 7038600 // starting freq when EEPROM is blank
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#define DIV 14 // starting divider for 4*freq*RDIV
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#define RDIV 2 // starting sub divider ( 13 meg breakpoint for div = 1 )
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#define DIV 28 // starting divider for 4*freq*RDIV
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#define RDIV 1 // starting sub divider. 1 will cover less than 1mhz to > 30mhz.
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// 16 will cover 37khz to 2.3 mhz ( with the 4x factor it is 64 when transmitting )
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#define CAT_MODE 0 // computer control of TX
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#define FRAME_MODE 1 // or self timed frame (stand alone mode)
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#define MUTE A1 // receiver module T/R switch pin
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#define stage(c) Serial.write(c)
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// use even dividers between 6 and 254 for lower jitter
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// using even dividers between 6 and 254 for lower jitter
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// freq range 2 to 150 without using the post dividers
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// we are using the post dividers
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// we are using the post dividers and can receive down to 40khz
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// vco 600 to 900
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uint64_t clock_freq = 2700452200;// 2700465300;// * 100 to enable setting fractional frequency
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uint32_t freq = FREQ; // ssb vfo freq
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uint64_t clock_freq = 2700452200; // * 100 to enable setting fractional frequency
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uint32_t freq = FREQ; // ssb vfo freq
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const uint32_t cal_freq = 3000000; // calibrate frequency
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const uint32_t cal_divider = 200;
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uint32_t divider = DIV; // 7 mhz with Rdiv of 8, 28 mhz with Rdiv of 2
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uint32_t audio_freq = 1538; // wspr 1400 to 1600 offset from base vfo freq
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uint32_t divider = DIV;
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uint32_t audio_freq = 1538; // wspr 1400 to 1600 offset from base vfo freq
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uint8_t Rdiv = RDIV;
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uint8_t operate_mode = FRAME_MODE; // start in stand alone timing mode
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uint8_t wspr_tx_enable; // transmit enable
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uint8_t wspr_tx_cancel; // CAT control RX command
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uint8_t operate_mode = FRAME_MODE; // start in stand alone timing mode
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uint8_t wspr_tx_enable; // transmit enable
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uint8_t wspr_tx_cancel; // CAT control RX command cancels tx
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uint8_t cal_enable;
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long tm_correct_count = 10753; // add or sub one ms for time correction per this many ms
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int8_t tm_correction = 0; // 0, 1 or -1 time correction
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@ -79,10 +83,20 @@ struct BAND {
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// relay board was jumpered to NOT have filter 1 always in line and antenna connects to the bnc
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// on the arduino shield. ( otherwise highest freq would need to be in position 1 and output would
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// be from the relay board )
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//struct BAND band_info[6] = { // filter
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// { 7, 40000, 600000 }, // 630m
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// { A0, 600000, 2500000 }, // 160m
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// { 10, 2500000, 5000000 }, // 80m
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// { 11, 5000000, 11500000 }, // 30m
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// { 12,11500000, 20000000 }, // 17m
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// { A3,20000000, 30000000 } // 10m
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//};
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// I don't have a 160m filter yet, so this is a modified table
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struct BAND band_info[6] = { // filter
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{ 7, 40000, 600000 }, // 630m
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{ A0, 600000, 2500000 }, // 160m
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{ 10, 2500000, 5000000 }, // 80m
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{ A0, 600000, 600001 }, // 160m
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{ 10, 600001, 5000000 }, // 80m
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{ 11, 5000000, 11500000 }, // 30m
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{ 12,11500000, 20000000 }, // 17m
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{ A3,20000000, 30000000 } // 10m
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@ -129,6 +143,9 @@ uint8_t i;
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ee_restore(); // get default freq for frame mode from eeprom
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pinMode(MUTE,OUTPUT); // receiver t/r switch
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digitalWrite(MUTE,LOW); // enable the receiver
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// set up the relay pins, exercise the relays, delay is 1.2 seconds, so reset at 59 seconds odd minute to be on time
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for( i = 0; i < 6; ++i ){
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pinMode(band_info[i].pin,OUTPUT);
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@ -161,7 +178,7 @@ uint8_t i;
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// i2cd(SI5351,3,0xff ^ (CLK0_EN + CLK1_EN + CLK2_EN)); // testing only all on, remove tx PWR
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digitalWrite(band_info[band].pin,LOW); // in case this turns out to be the correct relay
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band_change(); // select the correct relay
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band_change(); // select the correct relay
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}
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uint8_t band_change(){
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@ -191,16 +208,16 @@ static uint32_t old_freq = FREQ;
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freq = new_freq;
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if( band_change() ) divf = 1; // check the proper relay is selected
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// force freq above a lower limit, will need more Rdiv to actually get this low.
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// force freq above a lower limit
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if( freq < 40000 ) freq = 40000;
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if( freq >= 13000000 && Rdiv == 2 ) Rdiv = 1, divf = 1;
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if( freq < 13000000 && Rdiv == 1 ) Rdiv = 2, divf = 1;
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if( freq > 2000000 && Rdiv != 1 ) Rdiv = 1, divf = 1; // tx Rdiv is 4
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if( freq < 1000000 && Rdiv != 16 ) Rdiv = 16, divf = 1; // tx Rdiv is 64
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f4 = Rdiv * 4 * freq;
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f4 = f4 / 100000; // divide by zero next line if go below 100k on 4x vfo
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if( divf ) divider = 7500 / f4;
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if( divider & 1) divider += 1; // make it even
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if( divf ) divider = 7500 / f4; // else we are using the current divider
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if( divider & 1) divider += 1; // make it even
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if( divider > 254 ) divider = 254;
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if( divider < 6 ) divider = 6;
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@ -315,17 +332,17 @@ static uint8_t mod;
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void tx_on(){
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// !!! digital write the rx mute pin high
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i2cd(SI5351,3,0xff ^ (CLK0_EN)); // other clocks off during tx
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digitalWrite(MUTE,HIGH);
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i2cd(SI5351,3,0xff ^ (CLK0_EN)); // tx clock on, other clocks off during tx
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}
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void tx_off(){
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i2cd(SI5351,3,0xff ^ (CLK1_EN + CLK2_EN) ); // turn off tx, turn on rx and cal clocks
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si_pll_x(PLLA,Rdiv*4*freq,divider,0); // return to RX frequency
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// !!! unmute the RX with digital write
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digitalWrite(MUTE,LOW); // enable receiver
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ee_save(); // save this as the default band
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ee_save(); // save this freq to use during stand alone mode(FRAME MODE).
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}
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@ -360,7 +377,7 @@ void si_pll_x(unsigned char pll, uint32_t freq, uint32_t out_divider, uint32_t
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bc128 = (128 * r)/ clock_freq;
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P1 = 128 * a + bc128 - 512;
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P2 = 128 * b - c * bc128;
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if( P2 > c ) P2 = 0; // ? avoid negative numbers
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if( P2 > c ) P2 = 0; // avoid negative numbers
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P3 = c;
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i2cd(SI5351, pll + 0, (P3 & 0x0000FF00) >> 8);
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