kopia lustrzana https://github.com/Wren6991/PicoDVI
Delete unfinished HyperRAM code, it can be resurrected from the history at some point
Luke Wren
rodzic
14c27eaeae
commit
6895447bfd
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@ -22,7 +22,6 @@ include_directories(
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)
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add_subdirectory(libdvi)
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add_subdirectory(libhyperram)
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add_subdirectory(libsprite)
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add_subdirectory(apps)
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@ -2,7 +2,6 @@ add_subdirectory(bad_apple)
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add_subdirectory(dht_logging)
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add_subdirectory(dual_display)
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add_subdirectory(hello_dvi)
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add_subdirectory(hyperram_test)
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add_subdirectory(mandelbrot)
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add_subdirectory(moon)
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add_subdirectory(sprite_bounce)
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@ -1,10 +0,0 @@
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add_executable(hyperram_test
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main.c
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)
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target_link_libraries(hyperram_test
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pico_stdlib
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libhyperram
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)
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pico_add_extra_outputs(hyperram_test)
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@ -1,67 +0,0 @@
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#include <stdio.h>
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#include "pico/stdlib.h"
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#include "hardware/pio.h"
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#include "hardware/vreg.h"
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#include "hardware/clocks.h"
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#include "hyperram.h"
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#include "hyperram.pio.h"
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void printdata(const uint8_t *data, uint len) {
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for (int i = 0; i < len; ++i)
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printf("%02x%c", data[i], i % 16 == 15 ? '\n' : ' ');
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if (len % 16 != 15)
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printf("\n");
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}
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#define TESTLEN 256
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int main() {
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vreg_set_voltage(VREG_VOLTAGE_1_20);
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sleep_ms(1);
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set_sys_clock_khz(252 * 1000, true);
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setup_default_uart();
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hyperram_inst_t hram = {
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.pio = pio0,
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.sm = 3,
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.dq_base_pin = 22,
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.ctrl_base_pin = 0,
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.rst_n_pin = 4
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};
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printf("Loading program\n");
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hram.prog_offset = pio_add_program(hram.pio, &hyperram_program);
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printf("Initialising state machine\n");
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hyperram_pio_init(&hram);
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pio_sm_set_clkdiv(hram.pio, hram.sm, 50.f);
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const uint16_t cfgreg_init =
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(0x1u << 15) | // Power on (no DPDn)
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(0x0u << 12) | // Default drive strength (34R)
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(0xeu << 4) | // 3 latency cycles (in bias -5 format)
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(0x1u << 3); // Fixed 2x latency mode
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// Don't care about wrap modes, we're always linear
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printf("Writing %04x to CR0 register\n", cfgreg_init);
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hyperram_cfgreg_write(&hram, cfgreg_init);
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for (int clkdiv = 10; clkdiv > 0; --clkdiv) {
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printf("\nSetting clock divisor to %d\n", clkdiv);
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pio_sm_set_clkdiv(hram.pio, hram.sm, clkdiv);
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printf("Writing:\n");
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uint8_t testdata[TESTLEN];
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// Clear, then write test pattern
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for (int i = 0; i < TESTLEN; ++i)
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testdata[i] = 0;
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hyperram_write_blocking(&hram, 0x1234, (const uint32_t*)testdata, TESTLEN / sizeof(uint32_t));
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for (int i = 0; i < TESTLEN; ++i)
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testdata[i] = i & 0xff;
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// printdata(testdata, TESTLEN);
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hyperram_write_blocking(&hram, 0x1234, (const uint32_t*)testdata, TESTLEN / sizeof(uint32_t));
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printf("Reading back:\n");
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hyperram_read_blocking(&hram, 0x1234, (uint32_t*)testdata, TESTLEN / sizeof(uint32_t));
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printdata(testdata, TESTLEN);
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}
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}
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@ -1,18 +0,0 @@
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# Note we are using INTERFACE so that the library can be configured per-app
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# with compile-time defines
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add_library(libhyperram INTERFACE)
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target_sources(libhyperram INTERFACE
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${CMAKE_CURRENT_LIST_DIR}/hyperram.c
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${CMAKE_CURRENT_LIST_DIR}/hyperram.h
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)
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target_include_directories(libhyperram INTERFACE ${CMAKE_CURRENT_LIST_DIR})
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target_link_libraries(libhyperram INTERFACE
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pico_base_headers
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hardware_dma
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hardware_pio
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)
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pico_generate_pio_header(libhyperram ${CMAKE_CURRENT_LIST_DIR}/hyperram.pio)
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@ -1,156 +0,0 @@
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#include "hardware/pio.h"
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#include "hyperram.h"
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#include "hyperram.pio.h"
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#define CTRL_PIN_CS 0
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#define CTRL_PIN_RWDS 1
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#define CTRL_PIN_CK 2
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void hyperram_pio_init(const hyperram_inst_t *inst) {
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// Make sure HyperRAM is in reset before we futz with the GPIOs
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gpio_init(inst->rst_n_pin);
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gpio_put(inst->rst_n_pin, 0);
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gpio_set_dir(inst->rst_n_pin, GPIO_OUT);
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for (uint i = inst->dq_base_pin; i < inst->dq_base_pin + 8; ++i) {
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// Setting both pull bits enables bus-keep function
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gpio_set_pulls(i, true, true);
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pio_gpio_init(inst->pio, i);
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}
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hw_clear_bits(&inst->pio->input_sync_bypass, 0xffu << inst->dq_base_pin);
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for (uint i = inst->ctrl_base_pin; i < inst->ctrl_base_pin + 3; ++i)
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pio_gpio_init(inst->pio, i);
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gpio_pull_down(inst->ctrl_base_pin + CTRL_PIN_RWDS);
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// All controls low except CSn
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pio_sm_set_pins_with_mask(inst->pio, inst->sm,
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(1u << CTRL_PIN_CS) << inst->ctrl_base_pin,
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0x7u << inst->ctrl_base_pin
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);
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// All controls output except RWDS (DQs will sort themselves out later)
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pio_sm_set_pindirs_with_mask(inst->pio, inst->sm,
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(1u << CTRL_PIN_CS | 1u << CTRL_PIN_CK) << inst->ctrl_base_pin,
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0x7u << inst->ctrl_base_pin
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);
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pio_sm_config c = hyperram_program_get_default_config(inst->prog_offset);
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sm_config_set_out_pins(&c, inst->dq_base_pin, 8);
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sm_config_set_in_pins(&c, inst->dq_base_pin);
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sm_config_set_set_pins(&c, inst->ctrl_base_pin + CTRL_PIN_RWDS, 1);
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sm_config_set_sideset_pins(&c, inst->ctrl_base_pin);
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// Use shift-to-left (this means we write to memory in the wrong endianness,
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// but we hide this by requiring word-aligned addresses)
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sm_config_set_in_shift(&c, false, true, 32);
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sm_config_set_out_shift(&c, false, true, 32);
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// Should be removed: slow everything down to an easy speed to probe
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sm_config_set_clkdiv(&c, 10.f);
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pio_sm_init(inst->pio, inst->sm, inst->prog_offset, &c);
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pio_sm_set_enabled(inst->pio, inst->sm, true);
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gpio_put(inst->rst_n_pin, 1);
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}
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// 12-byte command packet to push to the PIO SM. After pushing the packet, can
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// either push write data, or wait for read data.
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typedef struct {
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uint32_t len;
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uint32_t cmd0;
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uint32_t cmd1_dir_jmp;
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} hyperram_cmd_t;
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typedef enum {
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HRAM_CMD_READ = 0x5,
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HRAM_CMD_WRITE = 0x1,
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HRAM_CMD_REGWRITE = 0x6
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} hyperram_cmd_flags;
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// HyperRAM command format from S27KL0641 datasheet:
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// ------+------------------------------+------------------------------------+
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// Bits | Name | Description |
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// ------+------------------------------+------------------------------------+
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// 47 | R/W# | 1 for read, 0 for write |
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// | | |
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// 46 | AS | 0 for memory address space, 1 for |
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// | | register space (write only) |
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// | | |
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// 45 | Burst | 0 for wrapped, 1 for linear |
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// | | |
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// 44:16 | Row and upper column address | Address bits 31:3, irrelevant bits |
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// | | should be 0s |
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// | | |
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// 15:3 | Reserved | Set to 0 |
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// | | |
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// 2:0 | Lower column address | Address bits 2:0 |
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// ------+------------------------------+------------------------------------+
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static inline void _hyperram_cmd_init(hyperram_cmd_t *cmd, hyperram_cmd_flags flags, uint32_t addr, uint len) {
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// HyperBus uses halfword addresses, not byte addresses. Additionally we
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// require addresses to be word-aligned, to hide the fact we screw up
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// endianness.
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addr = (addr >> 1) & ~0x1u;
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uint32_t addr_l = addr & 0x7u;
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uint32_t addr_h = addr >> 3;
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// First byte is always 0xff (to set DQs to output), then 24-bit length in same FIFO word.
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// Length is number of halfwords, minus one.
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cmd->len = (0xffu << 24) | ((len * 2 - 1) & ((1u << 24) - 1));
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cmd->cmd0 = (flags << 29) | addr_h;
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cmd->cmd1_dir_jmp = addr_l << 16;
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}
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void __not_in_flash_func(hyperram_read_blocking)(const hyperram_inst_t *inst, uint32_t addr, uint32_t *dst, uint len) {
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hyperram_cmd_t cmd;
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_hyperram_cmd_init(&cmd, HRAM_CMD_READ, addr, len);
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cmd.cmd1_dir_jmp |= inst->prog_offset + hyperram_offset_read;
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pio_sm_put_blocking(inst->pio, inst->sm, cmd.len);
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pio_sm_put_blocking(inst->pio, inst->sm, cmd.cmd0);
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pio_sm_put_blocking(inst->pio, inst->sm, cmd.cmd1_dir_jmp);
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for (uint i = 0; i < len; ++i)
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dst[i] = pio_sm_get_blocking(inst->pio, inst->sm);
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}
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void __not_in_flash_func(hyperram_write_blocking)(const hyperram_inst_t *inst, uint32_t addr, const uint32_t *src, uint len) {
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hyperram_cmd_t cmd;
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_hyperram_cmd_init(&cmd, HRAM_CMD_WRITE, addr, len);
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cmd.cmd1_dir_jmp |= (0xffu << 8) | (inst->prog_offset + hyperram_offset_write);
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pio_sm_put_blocking(inst->pio, inst->sm, cmd.len);
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pio_sm_put_blocking(inst->pio, inst->sm, cmd.cmd0);
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pio_sm_put_blocking(inst->pio, inst->sm, cmd.cmd1_dir_jmp);
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for (uint i = 0; i < len; ++i)
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pio_sm_put_blocking(inst->pio, inst->sm, src[i]);
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}
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// Note these are *byte* addresses, so are off by a factor of 2 from those given in datasheet
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enum {
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HRAM_REG_ID0 = 0u << 12 | 0u << 1,
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HRAM_REG_ID1 = 0u << 12 | 1u << 1,
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HRAM_REG_CFG0 = 1u << 12 | 0u << 1,
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HRAM_REG_CFG1 = 1u << 12 | 1u << 1
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};
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// We are using an awful hack here to reuse the data write loop for sending a
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// command packet followed immediately by a halfword of data. No worries about
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// efficiency, because generally you only write to the config register once.
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void hyperram_cfgreg_write(const hyperram_inst_t *inst, uint16_t wdata) {
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hyperram_cmd_t cmd;
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_hyperram_cmd_init(&cmd, HRAM_CMD_REGWRITE, HRAM_REG_CFG0, 0);
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// Make sure SM has bottomed out on TX empty, because we're about to mess
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// with its control flow
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uint32_t txstall_mask = 1u << (PIO_FDEBUG_TXSTALL_LSB + inst->sm);
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inst->pio->fdebug = txstall_mask;
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while (!(inst->pio->fdebug & txstall_mask))
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;
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// Set DQs to output (note that this uses exec(), so asserts CSn as a result,
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// as it doesn't set delay/sideset bits)
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pio_sm_set_consecutive_pindirs(inst->pio, inst->sm, inst->dq_base_pin, 8, true);
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// Preload Y register for the data loop (number of halfwords - 1)
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pio_sm_exec(inst->pio, inst->sm, pio_encode_set(pio_y, 3));
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// Note the difference between offset_write and offset_write_loop is whether
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// RWDS is asserted first (only true for write)
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pio_sm_exec(inst->pio, inst->sm, pio_encode_jmp(
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inst->prog_offset + hyperram_offset_write_loop
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));
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pio_sm_put(inst->pio, inst->sm, cmd.cmd0);
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pio_sm_put(inst->pio, inst->sm, cmd.cmd1_dir_jmp | wdata);
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}
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@ -1,23 +0,0 @@
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#ifndef _HYPERRAM_H
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#define _HYPERRAM_H
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#include "hardware/pio.h"
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typedef struct {
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PIO pio;
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uint sm;
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uint prog_offset;
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// DQ0->DQ7 starting here:
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uint dq_base_pin;
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// CSn, RWDS, CK, starting here:
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uint ctrl_base_pin;
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uint rst_n_pin;
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} hyperram_inst_t;
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void hyperram_pio_init(const hyperram_inst_t *inst);
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void hyperram_read_blocking(const hyperram_inst_t *inst, uint32_t addr, uint32_t *dst, uint len);
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void hyperram_write_blocking(const hyperram_inst_t *inst, uint32_t addr, const uint32_t *src, uint len);
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void hyperram_cfgreg_write(const hyperram_inst_t *inst, uint16_t wdata);
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#endif
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@ -1,74 +0,0 @@
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.program hyperram
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; HyperRAM interface. HyperBus clock is clk_sys/4 at maximum.
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; - out/in pins are mapped to DQx
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; - set pin is mapped to RWDS
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; - sideset pins are mapped to {CK, RWDS, CSn} (RWDS needn't be here except I
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; screwed up making the dev boards)
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; - If variable-latency support is added, map jmp pin to RWDS
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;
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; Command format (all little-endian in FIFO words):
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; - 1-byte initial DQ direction (always 0xff)
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; - 3-byte transfer length (number of halfwords transferred - 1)
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; (total transfer must be a multiple of 4 bytes)
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; - 6-byte command packet, as per HyperRAM datasheet
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; - 1 byte to set DQ directions
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; - 1 byte jump vector, to dispatch to read/write routine
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;
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; For writes, the data follows the command immediately in the TX FIFO. For
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; reads, data should be popped from RX FIFO.
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.side_set 3
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.define LATENCY 9
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; /-------- CK
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; |/------- RWDS
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; ||/------ CSn
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start: ; |||
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out pindirs, 8 side 0b001 [1] ; Set pins to output. Stall with CSn deasserted
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out y, 24 side 0b001 [1] ; Get data count
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do_cmd:
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set x, 2 side 0b000 [1] ; Always 6 bytes in command packet
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cmd_loop:
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out pins, 8 side 0b000
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nop side 0b100 ; Clock edge equidistant between data transitions
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out pins, 8 side 0b100
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jmp x-- cmd_loop side 0b000
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set x, LATENCY side 0b000
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delay_loop:
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nop side 0b100 [1]
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jmp x-- delay_loop side 0b000 [1]
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out pindirs, 8 side 0b100 ; Set pin directions based on 10th byte of cmd packet
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out pc, 8 side 0b100 ; Dispatch to read/write routine based on 11th byte
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public read:
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nop side 0b000 [1]
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nop side 0b100 [1] ; RAM asserts first data on this edge
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read_loop:
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in pins, 8 side 0b000 [1] ; Always capture when the following edge is launched
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in pins, 8 side 0b100
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jmp y--, read_loop side 0b100
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jmp start side 0b000 [1] ; We end up with an extra clock pulse (harmless)
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public write:
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set pindirs, 1 side 0b000 ; Assert RWDS
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public write_loop:
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out pins, 8 side 0b000
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nop side 0b100
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out pins, 8 side 0b100
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jmp y--, write_loop side 0b000
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set pindirs, 0 side 0b000 ; Deassert RWDS, wrap back to start
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; This program ignores the toggling of RWDS during reads, so assumes that the
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; RAM is able to provide data continuously. This is liable to break if
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; transfers cross page or row boundaries, as the memory is allowed to hold
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; RWDS low to insert wait states (exact behaviour is implementation-defined).
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; Easiest way to fix this is to use a second state machine to handle the read
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; data.
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;
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; The S27KL0641 datasheet is not forthcoming, but close reading of the vendor
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; model shows that it does not use this wait state mechanism (which kind of
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; makes sense, because there is no corresponding mechanism to insert wait
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; states on write)
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