Add 720x480p 60Hz mode (270 MHz bit clock)

software/apps/colour_terminal/main.c

@@ -27,6 +27,7 @@
 
 // Pick one:
 #define MODE_640x480_60Hz
+// #define MODE_720x480_60Hz
 // #define MODE_800x600_60Hz
 // #define MODE_960x540p_60Hz
 // #define MODE_1280x720_30Hz
@@ -38,6 +39,13 @@
 #define VREG_VSEL VREG_VOLTAGE_1_20
 #define DVI_TIMING dvi_timing_640x480p_60hz
 
+#elif defined(MODE_720x480_60Hz)
+// DVDD 1.2V
+#define FRAME_WIDTH 720
+#define FRAME_HEIGHT 480
+#define VREG_VSEL VREG_VOLTAGE_1_20
+#define DVI_TIMING dvi_timing_720x480p_60hz
+
 #elif defined(MODE_800x600_60Hz)
 // DVDD 1.3V, going downhill with a tailwind
 #define FRAME_WIDTH 800
@@ -45,7 +53,6 @@
 #define VREG_VSEL VREG_VOLTAGE_1_30
 #define DVI_TIMING dvi_timing_800x600p_60hz
 
-
 #elif defined(MODE_960x540p_60Hz)
 // DVDD 1.25V (slower silicon may need the full 1.3, or just not work)
 #define FRAME_WIDTH 960

software/apps/terminal/main.c

@@ -26,6 +26,7 @@
 
 // Pick one:
 #define MODE_640x480_60Hz
+// #define MODE_720x480_60Hz
 // #define MODE_800x600_60Hz
 // #define MODE_960x540p_60Hz
 // #define MODE_1280x720_30Hz
@@ -37,6 +38,13 @@
 #define VREG_VSEL VREG_VOLTAGE_1_20
 #define DVI_TIMING dvi_timing_640x480p_60hz
 
+#elif defined(MODE_720x480_60Hz)
+// DVDD 1.2V
+#define FRAME_WIDTH 720
+#define FRAME_HEIGHT 480
+#define VREG_VSEL VREG_VOLTAGE_1_20
+#define DVI_TIMING dvi_timing_720x480p_60hz
+
 #elif defined(MODE_800x600_60Hz)
 // DVDD 1.3V, going downhill with a tailwind
 #define FRAME_WIDTH 800
@@ -44,7 +52,6 @@
 #define VREG_VSEL VREG_VOLTAGE_1_30
 #define DVI_TIMING dvi_timing_800x600p_60hz
 
-
 #elif defined(MODE_960x540p_60Hz)
 // DVDD 1.25V (slower silicon may need the full 1.3, or just not work)
 #define FRAME_WIDTH 960

software/libdvi/dvi_timing.c

@@ -28,6 +28,24 @@ const struct dvi_timing __dvi_const(dvi_timing_640x480p_60hz) = {
 	.bit_clk_khz       = 252000
 };
 
+// 720x480p 60 Hz -- Required by CEA for EDTV/HDTV displays. Convenient for
+// emulating NTSC machines with visible overscan and reasonable clk_sys (270 MHz).
+const struct dvi_timing __dvi_const(dvi_timing_720x480p_60hz) = {
+	.h_sync_polarity   = false,
+	.h_front_porch     = 16,
+	.h_sync_width      = 62,
+	.h_back_porch      = 60,
+	.h_active_pixels   = 720,
+
+	.v_sync_polarity   = false,
+	.v_front_porch     = 9,
+	.v_sync_width      = 6,
+	.v_back_porch      = 30,
+	.v_active_lines    = 480,
+
+	.bit_clk_khz       = 270000
+};
+
 // SVGA -- completely by-the-book but requires 400 MHz clk_sys
 const struct dvi_timing __dvi_const(dvi_timing_800x600p_60hz) = {
 	.h_sync_polarity   = false,
@@ -45,22 +63,6 @@ const struct dvi_timing __dvi_const(dvi_timing_800x600p_60hz) = {
 	.bit_clk_khz       = 400000
 };
 
-const struct dvi_timing __dvi_const(dvi_timing_720x480p_60hz) = {
-	.h_sync_polarity   = false,
-	.h_front_porch     = 16,
-	.h_sync_width      = 62,
-	.h_back_porch      = 60,
-	.h_active_pixels   = 720,
-
-	.v_sync_polarity   = false,
-	.v_front_porch     = 9,
-	.v_sync_width      = 6,
-	.v_back_porch      = 30,
-	.v_active_lines    = 480,
-
-	.bit_clk_khz       = 270000
-};
-
 // 720x576@50Hz - CEA timing
 const struct dvi_timing __dvi_const(dvi_timing_720x576p_50hz) = {
 	.h_sync_polarity   = false,