OpenRTX

Autor	SHA1	Wiadomość	Data
Silvano Seva	4b8685b853	Changed gain and added an offset at tx RRC stage only for Module 17 to compensate for an hardware bug	2022-05-27 21:48:47 +02:00
Silvano Seva	d1b4973cc9	Fixed reset of DC bias on stream stop in Module 17 output stream driver, made parametric the gain of the RRC at modulator side	2022-05-27 21:48:47 +02:00
Silvano Seva	94fdf44954	Biased Module 17 baseband DAC output to Vdd/2 when idle	2022-05-27 21:48:47 +02:00
Silvano Seva	628c341712	Small improvements to MDx and Module 17 output stream drivers	2022-05-27 21:48:47 +02:00
Silvano Seva	12dc186129	Fixed bug in Module 17 output stream driver causing outputStream_sync() to hang when a stream was opened for the second time	2022-05-27 21:48:47 +02:00
Silvano Seva	163a2ef06a	Updated Module 17 output stream driver to support also double buffered mode	2022-05-27 21:48:47 +02:00