From eb876f1b0c5ef0f38c0834a7900e72a623e81477 Mon Sep 17 00:00:00 2001 From: Silvano Seva Date: Fri, 13 Nov 2020 12:27:07 +0100 Subject: [PATCH] Fixed bad clock tree configuration for STM32F405 MCU --- meson.build | 2 +- .../mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meson.build b/meson.build index c18ab269..17249a7b 100644 --- a/meson.build +++ b/meson.build @@ -96,7 +96,7 @@ stm32f405_inc = ['platform/mcu/CMSIS/Include', 'rtos/uC-OS3/Ports/ARM-Cortex-M/ARMv7-M', 'rtos/uC-CPU/ARM-Cortex-M/ARMv7-M'] -stm32f405_def = {'STM32F40_41xxx': ''} +stm32f405_def = {'STM32F40_41xxx': '', 'HSE_VALUE':'8000000'} ## ## Platform specializations diff --git a/platform/mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c b/platform/mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c index 652b490a..051f7a32 100644 --- a/platform/mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c +++ b/platform/mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c @@ -316,7 +316,7 @@ static void SetSysClock(void) RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + RCC->PLLCFGR = PLL_M | (PLL_N << 5) | (((PLL_P >> 1) -1) << 16) | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); /* Enable the main PLL */