From a1bd2fe22bf6c2da762beca34302d5633c38f688 Mon Sep 17 00:00:00 2001 From: Silvano Seva Date: Wed, 3 Feb 2021 12:14:15 +0100 Subject: [PATCH] Fixed bug in PLL divider computation which leads to have VCO frequency 4.2MHz below the expected value. See #13 --- platform/drivers/baseband/SKY72310.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/platform/drivers/baseband/SKY72310.c b/platform/drivers/baseband/SKY72310.c index 779753c2..75299d9d 100644 --- a/platform/drivers/baseband/SKY72310.c +++ b/platform/drivers/baseband/SKY72310.c @@ -89,22 +89,13 @@ void SKY73210_setFrequency(float freq, uint8_t clkDiv) float Ndnd = round(262144*(K - Ndiv - 32.0)); /* - * With PLL in fractional mode, dividend range is [-131017 +131071]. If our - * computation gives a wrong result, we decrement the reference clock divider - * and redo the computations. - * - * TODO: better investigate on how to put PLL in unsigned dividend mode. + * With PLL in fractional mode, dividend range is [-131017 +131071]. + * When converting from float to uint32_t we have to cast the value to a + * signed 18-bit one and increment the divider by one if dividend is negative. */ - if(((uint32_t) Ndnd) >= 131070) - { - clkDiv -= 1; - K = freq/(REF_CLK/((float) clkDiv)); - Ndiv = floor(K) - 32.0; - Ndnd = round(262144*(K - Ndiv - 32.0)); + uint32_t dnd = ((uint32_t) Ndnd) & 0x03FFFF; + if(dnd & 0x20000) Ndiv += 1; - } - - uint32_t dnd = ((uint32_t) Ndnd); uint16_t dndMsb = dnd >> 8; uint16_t dndLsb = dnd & 0x00FF;