From 54d675155d52aeb038e2f3df2d488c44a9a4e24e Mon Sep 17 00:00:00 2001 From: Silvano Seva Date: Sat, 23 Nov 2024 17:24:45 +0100 Subject: [PATCH] STM32H7: set up PLL2 to have a 168MHz clock source --- platform/mcu/STM32H7xx/drivers/pll.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/platform/mcu/STM32H7xx/drivers/pll.cpp b/platform/mcu/STM32H7xx/drivers/pll.cpp index b285e0be..5d4311f7 100644 --- a/platform/mcu/STM32H7xx/drivers/pll.cpp +++ b/platform/mcu/STM32H7xx/drivers/pll.cpp @@ -88,4 +88,12 @@ void startPll() //Finally, increase frequency RCC->CFGR |= RCC_CFGR_SW_PLL1; while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL1) ; //Wait + + //Configure PLL2 to have 168MHz on P output + RCC->PLLCKSELR |= 25 << RCC_PLLCKSELR_DIVM2_Pos; // M=25, VCO input 1MHz + RCC->PLL2DIVR = (168-1); // N=168, P,Q,R = 1 + RCC->PLLCFGR |= RCC_PLLCFGR_PLL2VCOSEL // Medium VCO range + | RCC_PLLCFGR_DIVP2EN; + RCC->CR |= RCC_CR_PLL2ON; // Start PLL2 + while((RCC->CR & RCC_CR_PLL2RDY)==0) ; // Wait until ready }