kopia lustrzana https://github.com/open-ham/OpenGD77
348 wiersze
8.0 KiB
C
348 wiersze
8.0 KiB
C
/*
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* Copyright (C)2019 Kai Ludwig, DG4KLU and Roger Clark VK3KYY / G4KYF
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "drivers/fsl_port.h"
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#include "interfaces/hr-c6000_spi.h"
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const uint32_t SPI_0_BAUDRATE = 3000000U;
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const uint32_t SPI_1_BAUDRATE = 1000000U;
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volatile bool SPI0inUse = false;
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volatile bool SPI1inUse = false;
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void SPIInit(void)
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{
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/* PORTD0 is configured as SPI0_CS0 */
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PORT_SetPinMux(Port_SPI_CS_C6000_U, Pin_SPI_CS_C6000_U, kPORT_MuxAlt2);
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/* PORTD1 is configured as SPI0_SCK */
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PORT_SetPinMux(Port_SPI_CLK_C6000_U, Pin_SPI_CLK_C6000_U, kPORT_MuxAlt2);
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/* PORTD2 is configured as SPI0_SOUT */
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PORT_SetPinMux(Port_SPI_DI_C6000_U, Pin_SPI_DI_C6000_U, kPORT_MuxAlt2);
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/* PORTD3 is configured as SPI0_SIN */
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PORT_SetPinMux(Port_SPI_DO_C6000_U, Pin_SPI_DO_C6000_U, kPORT_MuxAlt2);
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/* PORTB10 is configured as SPI1_CS0 */
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PORT_SetPinMux(Port_SPI_CS_C6000_V, Pin_SPI_CS_C6000_V, kPORT_MuxAlt2);
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/* PORTB11 is configured as SPI1_SCK */
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PORT_SetPinMux(Port_SPI_CLK_C6000_V, Pin_SPI_CLK_C6000_V, kPORT_MuxAlt2);
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/* PORTB16 is configured as SPI1_SOUT */
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PORT_SetPinMux(Port_SPI_DI_C6000_V, Pin_SPI_DI_C6000_V, kPORT_MuxAlt2);
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/* PORTB17 is configured as SPI1_SIN */
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PORT_SetPinMux(Port_SPI_DO_C6000_V, Pin_SPI_DO_C6000_V, kPORT_MuxAlt2);
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NVIC_SetPriority(SPI0_IRQn, 3);
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NVIC_SetPriority(SPI1_IRQn, 3);
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SPI0Setup();
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SPI1Setup();
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}
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void SPI0Setup(void)
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{
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dspi_master_config_t config;
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config.whichCtar = kDSPI_Ctar0;
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config.ctarConfig.baudRate = SPI_0_BAUDRATE;
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config.ctarConfig.bitsPerFrame = 8;
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config.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
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config.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge;
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config.ctarConfig.direction = kDSPI_MsbFirst;
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config.ctarConfig.pcsToSckDelayInNanoSec = 2000;
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config.ctarConfig.lastSckToPcsDelayInNanoSec = 2000;
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config.ctarConfig.betweenTransferDelayInNanoSec = 1000;
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config.whichPcs = kDSPI_Pcs0;
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config.pcsActiveHighOrLow = kDSPI_PcsActiveLow;
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config.enableContinuousSCK = false;
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config.enableRxFifoOverWrite = false;
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config.enableModifiedTimingFormat = false;
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config.samplePoint = kDSPI_SckToSin0Clock;
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DSPI_MasterInit(SPI0, &config, CLOCK_GetFreq(DSPI0_CLK_SRC));
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}
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void SPI1Setup(void)
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{
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dspi_master_config_t config;
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config.whichCtar = kDSPI_Ctar0;
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config.ctarConfig.baudRate = SPI_1_BAUDRATE;
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config.ctarConfig.bitsPerFrame = 8;
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config.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
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config.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge;
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config.ctarConfig.direction = kDSPI_MsbFirst;
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config.ctarConfig.pcsToSckDelayInNanoSec = 2000;
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config.ctarConfig.lastSckToPcsDelayInNanoSec = 2000;
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config.ctarConfig.betweenTransferDelayInNanoSec = 1000;
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config.whichPcs = kDSPI_Pcs0;
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config.pcsActiveHighOrLow = kDSPI_PcsActiveLow;
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config.enableContinuousSCK = false;
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config.enableRxFifoOverWrite = false;
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config.enableModifiedTimingFormat = false;
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config.samplePoint = kDSPI_SckToSin0Clock;
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DSPI_MasterInit(SPI1, &config, CLOCK_GetFreq(DSPI1_CLK_SRC));
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}
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int SPI0WritePageRegByte(uint8_t page, uint8_t reg, uint8_t val)
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{
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uint8_t txBuf[3];
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if (SPI0inUse)
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{
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return -1;
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}
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SPI0inUse = true;
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dspi_transfer_t masterXfer;
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status_t status;
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txBuf[0] = page;
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txBuf[1] = reg;
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txBuf[2] = val;
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/*Start master transfer*/
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masterXfer.txData = txBuf;
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masterXfer.rxData = NULL;
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masterXfer.dataSize = 3;
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masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
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status = DSPI_MasterTransferBlocking(SPI0, &masterXfer);
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SPI0inUse = false;
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return status;
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}
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int SPI0ReadPageRegByte(uint8_t page, uint8_t reg, volatile uint8_t *val)
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{
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uint8_t rxBuf[3];
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uint8_t RxBuf[3];
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if (SPI0inUse)
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{
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return -1;
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}
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SPI0inUse = true;
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dspi_transfer_t masterXfer;
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status_t status;
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RxBuf[0] = page | 0x80;
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RxBuf[1] = reg;
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RxBuf[2] = 0xFF;
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/*Start master transfer*/
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masterXfer.txData = RxBuf;
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masterXfer.rxData = rxBuf;
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masterXfer.dataSize = 3;
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masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
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status = DSPI_MasterTransferBlocking(SPI0, &masterXfer);
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if (status == kStatus_Success)
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{
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*val = rxBuf[2];
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}
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SPI0inUse = false;
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return status;
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}
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int SPI0SeClearPageRegByteWithMask(uint8_t page, uint8_t reg, uint8_t mask, uint8_t val)
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{
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status_t status;
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uint8_t tmp_val;
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status = SPI0ReadPageRegByte(page, reg, &tmp_val);
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if (status == kStatus_Success)
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{
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tmp_val = val | (tmp_val & mask);
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status = SPI0WritePageRegByte(page, reg, tmp_val);
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}
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return status;
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}
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int SPI0WritePageRegByteArray(uint8_t page, uint8_t reg, const uint8_t *values, uint8_t length)
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{
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const int SPI0_PAGE_WRITE_BUFFER_SIZE = 128 + 2;
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uint8_t txBuf[SPI0_PAGE_WRITE_BUFFER_SIZE + 2];
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if (length > SPI0_PAGE_WRITE_BUFFER_SIZE)
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{
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return kStatus_InvalidArgument;
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}
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if (SPI0inUse)
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{
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return -1;
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}
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SPI0inUse = true;
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dspi_transfer_t masterXfer;
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status_t status;
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txBuf[0] = page;
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txBuf[1] = reg;
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memcpy(txBuf + 2, values, length);
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/*Start master transfer*/
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masterXfer.txData = txBuf;
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masterXfer.rxData = NULL;
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masterXfer.dataSize = length + 2;
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masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
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status = DSPI_MasterTransferBlocking(SPI0, &masterXfer);
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SPI0inUse = false;
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return status;
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}
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int SPI0ReadPageRegBytAarray(uint8_t page, uint8_t reg, volatile uint8_t *values, uint8_t length)
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{
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uint8_t rxBuf[0x60 + 2];
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uint8_t txBuf[0x60 + 2];
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if (length > 0x60)
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{
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return kStatus_InvalidArgument;
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}
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if (SPI0inUse)
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{
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return -1;
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}
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SPI0inUse = true;
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dspi_transfer_t masterXfer;
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status_t status;
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txBuf[0] = page | 0x80;
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txBuf[1] = reg;
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/*Start master transfer*/
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masterXfer.txData = txBuf;
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masterXfer.rxData = rxBuf;
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masterXfer.dataSize = length + 2;
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masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
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status = DSPI_MasterTransferBlocking(SPI0, &masterXfer);
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if (status == kStatus_Success)
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{
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for (int i = 0; i < length; i++)
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{
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values[i] = rxBuf[i + 2];
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}
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}
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SPI0inUse = false;
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return status;
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}
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int SPI1WritePageRegByteArray(uint8_t page, uint8_t reg, const uint8_t *values, uint8_t length)
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{
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uint8_t txBuf[32 + 2];
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if (length > 32)
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{
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return kStatus_InvalidArgument;
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}
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if (SPI1inUse)
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{
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return -1;
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}
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SPI1inUse = true;
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dspi_transfer_t masterXfer;
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status_t status;
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txBuf[0] = page;
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txBuf[1] = reg;
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memcpy(txBuf + 2, values, length);
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/*Start master transfer*/
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masterXfer.txData = txBuf;
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masterXfer.rxData = NULL;
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masterXfer.dataSize = length + 2;
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masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
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status = DSPI_MasterTransferBlocking(SPI1, &masterXfer);
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SPI1inUse = false;
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return status;
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}
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int SPI1ReadPageRegByteArray(uint8_t page, uint8_t reg, volatile uint8_t *values, uint8_t length)
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{
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uint8_t rxBuf[32 + 2];
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uint8_t txBuf[32 + 2];
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if (length > 32)
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{
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return kStatus_InvalidArgument;
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}
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if (SPI1inUse)
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{
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return -1;
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}
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SPI1inUse = true;
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dspi_transfer_t masterXfer;
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status_t status;
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txBuf[0] = page | 0x80;
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txBuf[1] = reg;
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/*Start master transfer*/
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masterXfer.txData = txBuf;
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masterXfer.rxData = rxBuf;
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masterXfer.dataSize = length + 2;
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masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
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status = DSPI_MasterTransferBlocking(SPI1, &masterXfer);
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if (status == kStatus_Success)
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{
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for (int i = 0; i < length; i++)
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{
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values[i] = rxBuf[i + 2];
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}
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}
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SPI1inUse = false;
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return status;
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}
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