kopia lustrzana https://github.com/Jean-MarcHarvengt/MCUME
1289 wiersze
44 KiB
C
1289 wiersze
44 KiB
C
#include "shared.h"
|
|
|
|
#include "machdep/m68k.h"
|
|
#include "memory.h"
|
|
#include "custom.h"
|
|
#include "readcpu.h"
|
|
#include "newcpu.h"
|
|
#include "compiler.h"
|
|
#include "cputbl.h"
|
|
#if !defined (MEMFUNCS_DIRECT_REQUESTED) || defined (DIRECT_MEMFUNCS_SUCCESSFUL)
|
|
void REGPARAM2 CPU_OP_NAME(_9000)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s8 src = m68k_dreg(regs, srcreg);
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9010)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9018)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
{ m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9020)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ m68k_areg(regs, srcreg) -= areg_byteinc[srcreg];
|
|
{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9028)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)nextiword();
|
|
uae_s8 src = get_byte(srca);
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9030)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = get_disp_ea(m68k_areg(regs, srcreg));
|
|
{ uae_s8 src = get_byte(srca);
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9038)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = (uae_s32)(uae_s16)nextiword();
|
|
uae_s8 src = get_byte(srca);
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9039)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = nextilong();
|
|
uae_s8 src = get_byte(srca);
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_903a)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_getpc();
|
|
srca += (uae_s32)(uae_s16)nextiword();
|
|
{ uae_s8 src = get_byte(srca);
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_903b)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = get_disp_ea(m68k_getpc());
|
|
{ uae_s8 src = get_byte(srca);
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_903c)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s8 src = nextibyte();
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9040)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s16 src = m68k_dreg(regs, srcreg);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9048)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s16 src = m68k_areg(regs, srcreg);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9050)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9058)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
{ m68k_areg(regs, srcreg) += 2;
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9060)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ m68k_areg(regs, srcreg) -= 2;
|
|
{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9068)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)nextiword();
|
|
uae_s16 src = get_word(srca);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9070)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = get_disp_ea(m68k_areg(regs, srcreg));
|
|
{ uae_s16 src = get_word(srca);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9078)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = (uae_s32)(uae_s16)nextiword();
|
|
uae_s16 src = get_word(srca);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9079)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = nextilong();
|
|
uae_s16 src = get_word(srca);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_907a)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_getpc();
|
|
srca += (uae_s32)(uae_s16)nextiword();
|
|
{ uae_s16 src = get_word(srca);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_907b)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = get_disp_ea(m68k_getpc());
|
|
{ uae_s16 src = get_word(srca);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_907c)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s16 src = nextiword();
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9080)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s32 src = m68k_dreg(regs, srcreg);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9088)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s32 src = m68k_areg(regs, srcreg);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9090)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9098)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
{ m68k_areg(regs, srcreg) += 4;
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90a0)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ m68k_areg(regs, srcreg) -= 4;
|
|
{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90a8)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)nextiword();
|
|
uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90b0)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = get_disp_ea(m68k_areg(regs, srcreg));
|
|
{ uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90b8)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = (uae_s32)(uae_s16)nextiword();
|
|
uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90b9)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = nextilong();
|
|
uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90ba)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_getpc();
|
|
srca += (uae_s32)(uae_s16)nextiword();
|
|
{ uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90bb)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = get_disp_ea(m68k_getpc());
|
|
{ uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90bc)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s32 src = nextilong();
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90c0)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s16 src = m68k_dreg(regs, srcreg);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90c8)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s16 src = m68k_areg(regs, srcreg);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90d0)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90d8)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
{ m68k_areg(regs, srcreg) += 2;
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90e0)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ m68k_areg(regs, srcreg) -= 2;
|
|
{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90e8)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)nextiword();
|
|
uae_s16 src = get_word(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90f0)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = get_disp_ea(m68k_areg(regs, srcreg));
|
|
{ uae_s16 src = get_word(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90f8)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = (uae_s32)(uae_s16)nextiword();
|
|
uae_s16 src = get_word(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90f9)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = nextilong();
|
|
uae_s16 src = get_word(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90fa)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_getpc();
|
|
srca += (uae_s32)(uae_s16)nextiword();
|
|
{ uae_s16 src = get_word(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90fb)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = get_disp_ea(m68k_getpc());
|
|
{ uae_s16 src = get_word(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_90fc)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s16 src = nextiword();
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9100)(uae_u32 opcode) /* SUBX */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s8 src = m68k_dreg(regs, srcreg);
|
|
{ uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src - (XFLG ? 1 : 0);
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
VFLG = (!flgs && flgo && !flgn) || (flgs && !flgo && flgn);
|
|
XFLG = CFLG = (flgs && !flgo) || (flgn && (!flgo || flgs));
|
|
if (((uae_s8)(newv)) != 0) ZFLG = 0;
|
|
NFLG = ((uae_s8)(newv)) < 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9108)(uae_u32 opcode) /* SUBX */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ m68k_areg(regs, srcreg) -= areg_byteinc[srcreg];
|
|
{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
{ m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
{ uae_u32 newv = dst - src - (XFLG ? 1 : 0);
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
VFLG = (!flgs && flgo && !flgn) || (flgs && !flgo && flgn);
|
|
XFLG = CFLG = (flgs && !flgo) || (flgn && (!flgo || flgs));
|
|
if (((uae_s8)(newv)) != 0) ZFLG = 0;
|
|
NFLG = ((uae_s8)(newv)) < 0;
|
|
put_byte(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9110)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s8 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
put_byte(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9118)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s8 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
{ m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
put_byte(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9120)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s8 src = m68k_dreg(regs, srcreg);
|
|
{ m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
put_byte(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9128)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s8 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)nextiword();
|
|
uae_s8 dst = get_byte(dsta);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
put_byte(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9130)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s8 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = get_disp_ea(m68k_areg(regs, dstreg));
|
|
{ uae_s8 dst = get_byte(dsta);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
put_byte(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9138)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
{{ uae_s8 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = (uae_s32)(uae_s16)nextiword();
|
|
uae_s8 dst = get_byte(dsta);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
put_byte(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9139)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
{{ uae_s8 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = nextilong();
|
|
uae_s8 dst = get_byte(dsta);
|
|
{{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
|
|
{ int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
ZFLG = ((uae_s8)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u8)(src)) > ((uae_u8)(dst));
|
|
NFLG = flgn != 0;
|
|
put_byte(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9140)(uae_u32 opcode) /* SUBX */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s16 src = m68k_dreg(regs, srcreg);
|
|
{ uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src - (XFLG ? 1 : 0);
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
VFLG = (!flgs && flgo && !flgn) || (flgs && !flgo && flgn);
|
|
XFLG = CFLG = (flgs && !flgo) || (flgn && (!flgo || flgs));
|
|
if (((uae_s16)(newv)) != 0) ZFLG = 0;
|
|
NFLG = ((uae_s16)(newv)) < 0;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9148)(uae_u32 opcode) /* SUBX */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ m68k_areg(regs, srcreg) -= 2;
|
|
{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
{ m68k_areg(regs, dstreg) -= 2;
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
{ uae_u32 newv = dst - src - (XFLG ? 1 : 0);
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
VFLG = (!flgs && flgo && !flgn) || (flgs && !flgo && flgn);
|
|
XFLG = CFLG = (flgs && !flgo) || (flgn && (!flgo || flgs));
|
|
if (((uae_s16)(newv)) != 0) ZFLG = 0;
|
|
NFLG = ((uae_s16)(newv)) < 0;
|
|
put_word(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9150)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s16 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
put_word(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9158)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s16 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
{ m68k_areg(regs, dstreg) += 2;
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
put_word(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9160)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s16 src = m68k_dreg(regs, srcreg);
|
|
{ m68k_areg(regs, dstreg) -= 2;
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
put_word(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9168)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s16 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)nextiword();
|
|
uae_s16 dst = get_word(dsta);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
put_word(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9170)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s16 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = get_disp_ea(m68k_areg(regs, dstreg));
|
|
{ uae_s16 dst = get_word(dsta);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
put_word(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9178)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
{{ uae_s16 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = (uae_s32)(uae_s16)nextiword();
|
|
uae_s16 dst = get_word(dsta);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
put_word(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9179)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
{{ uae_s16 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = nextilong();
|
|
uae_s16 dst = get_word(dsta);
|
|
{{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
|
|
{ int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
ZFLG = ((uae_s16)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u16)(src)) > ((uae_u16)(dst));
|
|
NFLG = flgn != 0;
|
|
put_word(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9180)(uae_u32 opcode) /* SUBX */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s32 src = m68k_dreg(regs, srcreg);
|
|
{ uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src - (XFLG ? 1 : 0);
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
VFLG = (!flgs && flgo && !flgn) || (flgs && !flgo && flgn);
|
|
XFLG = CFLG = (flgs && !flgo) || (flgn && (!flgo || flgs));
|
|
if (((uae_s32)(newv)) != 0) ZFLG = 0;
|
|
NFLG = ((uae_s32)(newv)) < 0;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9188)(uae_u32 opcode) /* SUBX */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ m68k_areg(regs, srcreg) -= 4;
|
|
{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
{ m68k_areg(regs, dstreg) -= 4;
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
{ uae_u32 newv = dst - src - (XFLG ? 1 : 0);
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
VFLG = (!flgs && flgo && !flgn) || (flgs && !flgo && flgn);
|
|
XFLG = CFLG = (flgs && !flgo) || (flgn && (!flgo || flgs));
|
|
if (((uae_s32)(newv)) != 0) ZFLG = 0;
|
|
NFLG = ((uae_s32)(newv)) < 0;
|
|
put_long(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9190)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s32 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
put_long(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_9198)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s32 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
{ m68k_areg(regs, dstreg) += 4;
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
put_long(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91a0)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s32 src = m68k_dreg(regs, srcreg);
|
|
{ m68k_areg(regs, dstreg) -= 4;
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
put_long(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91a8)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s32 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)nextiword();
|
|
uae_s32 dst = get_long(dsta);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
put_long(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91b0)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
uae_u32 dstreg = opcode & 7;
|
|
{{ uae_s32 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = get_disp_ea(m68k_areg(regs, dstreg));
|
|
{ uae_s32 dst = get_long(dsta);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
put_long(dsta,newv);
|
|
}}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91b8)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
{{ uae_s32 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = (uae_s32)(uae_s16)nextiword();
|
|
uae_s32 dst = get_long(dsta);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
put_long(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91b9)(uae_u32 opcode) /* SUB */
|
|
{
|
|
uae_u32 srcreg = ((opcode >> 9) & 7);
|
|
{{ uae_s32 src = m68k_dreg(regs, srcreg);
|
|
{ uaecptr dsta = nextilong();
|
|
uae_s32 dst = get_long(dsta);
|
|
{{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
|
|
{ int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
ZFLG = ((uae_s32)(newv)) == 0;
|
|
VFLG = (flgs != flgo) && (flgn != flgo);
|
|
CFLG = XFLG = ((uae_u32)(src)) > ((uae_u32)(dst));
|
|
NFLG = flgn != 0;
|
|
put_long(dsta,newv);
|
|
}}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91c0)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s32 src = m68k_dreg(regs, srcreg);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91c8)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s32 src = m68k_areg(regs, srcreg);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91d0)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91d8)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
{ m68k_areg(regs, srcreg) += 4;
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91e0)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ m68k_areg(regs, srcreg) -= 4;
|
|
{ uaecptr srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91e8)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)nextiword();
|
|
uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91f0)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 srcreg = (opcode & 7);
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = get_disp_ea(m68k_areg(regs, srcreg));
|
|
{ uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91f8)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = (uae_s32)(uae_s16)nextiword();
|
|
uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91f9)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = nextilong();
|
|
uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91fa)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = m68k_getpc();
|
|
srca += (uae_s32)(uae_s16)nextiword();
|
|
{ uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91fb)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uaecptr srca = get_disp_ea(m68k_getpc());
|
|
{ uae_s32 src = get_long(srca);
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}}
|
|
void REGPARAM2 CPU_OP_NAME(_91fc)(uae_u32 opcode) /* SUBA */
|
|
{
|
|
uae_u32 dstreg = (opcode >> 9) & 7;
|
|
{{ uae_s32 src = nextilong();
|
|
{ uae_s32 dst = m68k_areg(regs, dstreg);
|
|
{ uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
}}}}}
|
|
#endif
|
|
|