kopia lustrzana https://github.com/Jean-MarcHarvengt/MCUME
540 wiersze
12 KiB
C
540 wiersze
12 KiB
C
/*****************************************************************************\
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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This file is licensed under the Snes9x License.
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For further information, consult the LICENSE file in the root directory.
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\*****************************************************************************/
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#ifndef _MEMORY_H_
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#define _MEMORY_H_
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#define MEMMAP_BLOCK_SIZE (0x1000)
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#define MEMMAP_NUM_BLOCKS (0x1000000 / MEMMAP_BLOCK_SIZE)
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#define MEMMAP_SHIFT (12)
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#define MEMMAP_MASK (MEMMAP_BLOCK_SIZE - 1)
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enum
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{
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MAP_TYPE_I_O,
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MAP_TYPE_ROM,
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MAP_TYPE_RAM
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};
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enum
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{
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MAP_CPU,
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MAP_PPU,
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MAP_LOROM_SRAM,
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MAP_HIROM_SRAM,
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MAP_DSP,
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MAP_RONLY_SRAM,
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MAP_NONE,
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MAP_LAST
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};
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typedef enum
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{
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WRAP_NONE,
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WRAP_BANK,
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WRAP_PAGE
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} s9xwrap_t;
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typedef enum
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{
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WRITE_01,
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WRITE_10
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} s9xwriteorder_t;
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typedef struct
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{
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uint8 CPU_IO[0x400];
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uint8 PPU_IO[0x200];
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uint8 *RAM;
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uint8 *ROM;
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uint8 *SRAM;
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uint8 *VRAM;
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#if RETRO_COMBINED_MEMORY_MAP
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union {
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uint8 *ReadMap[MEMMAP_NUM_BLOCKS];
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uint8 *WriteMap[MEMMAP_NUM_BLOCKS];
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};
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#else
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uint8 *ReadMap[MEMMAP_NUM_BLOCKS];
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uint8 *WriteMap[MEMMAP_NUM_BLOCKS];
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#endif
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char ROMName[ROM_NAME_LEN];
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char ROMId[5];
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uint8 ROMRegion;
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uint8 ROMSpeed;
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uint8 ROMType;
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uint8 ROMSize;
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uint32 ROMChecksum;
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uint32 ROMComplementChecksum;
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uint32 ROMCRC32;
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bool8 ROMIsPatched;
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bool8 HiROM;
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bool8 LoROM;
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uint32 SRAMSize;
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uint32 SRAMBytes;
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uint32 SRAMMask;
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uint32 CalculatedSize;
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uint32 CalculatedChecksum;
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// uint32 ROM_BLOCKS[ROM_MAX_SIZE / ROM_BLOCK_SIZE];
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uint32 ROM_MAX_SIZE;
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uint32 ROM_SIZE;
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} CMemory;
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extern CMemory Memory;
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extern uint32 OpenBus;
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bool8 S9xLoadROMMem (const uint8 *);
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bool8 S9xLoadROM (const char *);
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bool8 S9xMemoryInit (void);
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void S9xMemoryDeinit (void);
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#include "cpu.h"
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#include "dsp.h"
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#if RETRO_LESS_ACCURATE_MEM
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#define addCyclesInMemoryAccess \
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if (!CPU.InDMAorHDMA) \
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{ \
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CPU.Cycles += speed; \
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}
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#define addCyclesInMemoryAccess_x2 \
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if (!CPU.InDMAorHDMA) \
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{ \
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CPU.Cycles += speed << 1; \
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}
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#else
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#define addCyclesInMemoryAccess \
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if (!CPU.InDMAorHDMA) \
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{ \
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CPU.Cycles += speed; \
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if (CPU.Cycles >= CPU.NextEvent) \
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S9xDoHEventProcessing(); \
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}
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#define addCyclesInMemoryAccess_x2 \
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if (!CPU.InDMAorHDMA) \
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{ \
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CPU.Cycles += speed << 1; \
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if (CPU.Cycles >= CPU.NextEvent) \
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S9xDoHEventProcessing(); \
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}
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#endif
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// This is just to track where ROM memory access occurs. If the trapping isn't too costly, this info
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// will eventually be used it to handle large roms through esp_himem_*
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#define CHECK_ROM_MAPPING(a) // if ((a) >= Memory.ROM && (a) - Memory.ROM < Memory.ROM_MAX_SIZE) { printf("ROM in %s at %p\n", __func__, (a)); }
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static inline int32 memory_speed (uint32 address)
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{
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if (address & 0x408000)
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{
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if (address & 0x800000)
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return (CPU.FastROMSpeed);
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return (SLOW_ONE_CYCLE);
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}
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if ((address + 0x6000) & 0x4000)
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return (SLOW_ONE_CYCLE);
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if ((address - 0x4000) & 0x7e00)
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return (ONE_CYCLE);
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return (TWO_CYCLES);
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}
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inline uint8 S9xGetByte (uint32 Address)
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{
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uint8 *GetAddress = Memory.ReadMap[(Address & 0xffffff) >> MEMMAP_SHIFT];
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uint32 speed = memory_speed(Address);
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uint32 byte;
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if (GetAddress >= (uint8 *) MAP_LAST)
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{
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CHECK_ROM_MAPPING(GetAddress + (Address & 0xffff));
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byte = *(GetAddress + (Address & 0xffff));
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addCyclesInMemoryAccess;
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return (byte);
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}
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switch ((pint) GetAddress)
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{
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case MAP_CPU:
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byte = S9xGetCPU(Address & 0xffff);
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addCyclesInMemoryAccess;
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return (byte);
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case MAP_PPU:
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if (CPU.InDMAorHDMA && (Address & 0xff00) == 0x2100)
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return (OpenBus);
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byte = S9xGetPPU(Address & 0xffff);
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addCyclesInMemoryAccess;
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return (byte);
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case MAP_LOROM_SRAM:
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// Address & 0x7fff : offset into bank
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// Address & 0xff0000 : bank
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// bank >> 1 | offset : SRAM address, unbound
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// unbound & SRAMMask : SRAM offset
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byte = *(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask));
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addCyclesInMemoryAccess;
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return (byte);
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case MAP_HIROM_SRAM:
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case MAP_RONLY_SRAM:
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byte = *(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask));
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addCyclesInMemoryAccess;
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return (byte);
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case MAP_DSP:
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byte = S9xGetDSP(Address & 0xffff);
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addCyclesInMemoryAccess;
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return (byte);
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case MAP_NONE:
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default:
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byte = OpenBus;
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addCyclesInMemoryAccess;
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return (byte);
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}
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}
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inline uint16 S9xGetWord (uint32 Address, s9xwrap_t w = WRAP_NONE)
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{
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uint32 mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
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uint32 word;
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if ((Address & mask) == mask)
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{
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PC_t a;
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word = OpenBus = S9xGetByte(Address);
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switch (w)
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{
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case WRAP_PAGE:
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a.xPBPC = Address;
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a.B.xPCl++;
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return (word | (S9xGetByte(a.xPBPC) << 8));
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case WRAP_BANK:
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a.xPBPC = Address;
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a.W.xPC++;
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return (word | (S9xGetByte(a.xPBPC) << 8));
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case WRAP_NONE:
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default:
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return (word | (S9xGetByte(Address + 1) << 8));
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}
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}
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uint8 *GetAddress = Memory.ReadMap[(Address & 0xffffff) >> MEMMAP_SHIFT];
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uint32 speed = memory_speed(Address);
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if (GetAddress >= (uint8 *) MAP_LAST)
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{
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CHECK_ROM_MAPPING(GetAddress + (Address & 0xffff));
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word = READ_WORD(GetAddress + (Address & 0xffff));
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addCyclesInMemoryAccess_x2;
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return (word);
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}
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switch ((pint) GetAddress)
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{
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case MAP_CPU:
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word = S9xGetCPU(Address & 0xffff);
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word |= S9xGetCPU((Address + 1) & 0xffff) << 8;
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addCyclesInMemoryAccess_x2;
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return (word);
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case MAP_PPU:
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if (CPU.InDMAorHDMA)
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{
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word = OpenBus = S9xGetByte(Address);
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return (word | (S9xGetByte(Address + 1) << 8));
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}
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word = S9xGetPPU(Address & 0xffff);
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word |= S9xGetPPU((Address + 1) & 0xffff) << 8;
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addCyclesInMemoryAccess_x2;
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return (word);
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case MAP_LOROM_SRAM:
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if (Memory.SRAMMask >= MEMMAP_MASK)
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word = READ_WORD(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask));
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else
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word = (*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask))) |
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((*(Memory.SRAM + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask))) << 8);
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addCyclesInMemoryAccess_x2;
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return (word);
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case MAP_HIROM_SRAM:
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case MAP_RONLY_SRAM:
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if (Memory.SRAMMask >= MEMMAP_MASK)
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word = READ_WORD(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask));
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else
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word = (*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) |
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(*(Memory.SRAM + ((((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask)) << 8));
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addCyclesInMemoryAccess_x2;
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return (word);
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case MAP_DSP:
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word = S9xGetDSP(Address & 0xffff);
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word |= S9xGetDSP((Address + 1) & 0xffff) << 8;
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addCyclesInMemoryAccess_x2;
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return (word);
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case MAP_NONE:
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default:
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word = OpenBus | (OpenBus << 8);
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addCyclesInMemoryAccess_x2;
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return (word);
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}
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}
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inline void S9xSetByte (uint8 Byte, uint32 Address)
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{
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uint8 *SetAddress = Memory.WriteMap[(Address & 0xffffff) >> MEMMAP_SHIFT];
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uint32 speed = memory_speed(Address);
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if (SetAddress >= (uint8 *) MAP_LAST)
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{
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*(SetAddress + (Address & 0xffff)) = Byte;
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addCyclesInMemoryAccess;
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return;
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}
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switch ((pint) SetAddress)
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{
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case MAP_CPU:
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S9xSetCPU(Byte, Address & 0xffff);
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addCyclesInMemoryAccess;
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return;
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case MAP_PPU:
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if (CPU.InDMAorHDMA && (Address & 0xff00) == 0x2100)
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return;
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S9xSetPPU(Byte, Address & 0xffff);
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addCyclesInMemoryAccess;
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return;
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case MAP_LOROM_SRAM:
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if (Memory.SRAMMask)
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{
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*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)) = Byte;
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CPU.SRAMModified = TRUE;
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}
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addCyclesInMemoryAccess;
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return;
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case MAP_HIROM_SRAM:
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if (Memory.SRAMMask)
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{
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*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) = Byte;
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CPU.SRAMModified = TRUE;
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}
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addCyclesInMemoryAccess;
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return;
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case MAP_DSP:
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S9xSetDSP(Byte, Address & 0xffff);
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addCyclesInMemoryAccess;
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return;
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case MAP_NONE:
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default:
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addCyclesInMemoryAccess;
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return;
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}
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}
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inline void S9xSetWord (uint16 Word, uint32 Address, s9xwrap_t w, s9xwriteorder_t o)
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{
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uint32 mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
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if ((Address & mask) == mask)
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{
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PC_t a;
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if (!o)
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S9xSetByte((uint8) Word, Address);
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switch (w)
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{
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case WRAP_PAGE:
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a.xPBPC = Address;
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a.B.xPCl++;
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S9xSetByte(Word >> 8, a.xPBPC);
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break;
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case WRAP_BANK:
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a.xPBPC = Address;
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a.W.xPC++;
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S9xSetByte(Word >> 8, a.xPBPC);
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break;
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case WRAP_NONE:
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default:
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S9xSetByte(Word >> 8, Address + 1);
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break;
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}
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if (o)
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S9xSetByte((uint8) Word, Address);
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return;
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}
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uint8 *SetAddress = Memory.WriteMap[(Address & 0xffffff) >> MEMMAP_SHIFT];
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uint32 speed = memory_speed(Address);
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if (SetAddress >= (uint8 *) MAP_LAST)
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{
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WRITE_WORD(SetAddress + (Address & 0xffff), Word);
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addCyclesInMemoryAccess_x2;
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return;
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}
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switch ((pint) SetAddress)
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{
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case MAP_CPU:
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if (o)
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{
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S9xSetCPU(Word >> 8, (Address + 1) & 0xffff);
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S9xSetCPU((uint8) Word, Address & 0xffff);
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}
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else
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{
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S9xSetCPU((uint8) Word, Address & 0xffff);
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S9xSetCPU(Word >> 8, (Address + 1) & 0xffff);
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}
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addCyclesInMemoryAccess_x2;
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return;
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case MAP_PPU:
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if (CPU.InDMAorHDMA)
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{
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if ((Address & 0xff00) != 0x2100)
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S9xSetPPU((uint8) Word, Address & 0xffff);
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if (((Address + 1) & 0xff00) != 0x2100)
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S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
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return;
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}
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if (o)
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{
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S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
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S9xSetPPU((uint8) Word, Address & 0xffff);
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}
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else
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{
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S9xSetPPU((uint8) Word, Address & 0xffff);
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S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
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}
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addCyclesInMemoryAccess_x2;
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return;
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case MAP_LOROM_SRAM:
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if (Memory.SRAMMask)
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{
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if (Memory.SRAMMask >= MEMMAP_MASK)
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WRITE_WORD(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask), Word);
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else
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{
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*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)) = (uint8) Word;
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*(Memory.SRAM + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask)) = Word >> 8;
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}
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CPU.SRAMModified = TRUE;
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}
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addCyclesInMemoryAccess_x2;
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return;
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case MAP_HIROM_SRAM:
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if (Memory.SRAMMask)
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{
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if (Memory.SRAMMask >= MEMMAP_MASK)
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WRITE_WORD(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask), Word);
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else
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{
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*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) = (uint8) Word;
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*(Memory.SRAM + ((((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask)) = Word >> 8;
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}
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CPU.SRAMModified = TRUE;
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}
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addCyclesInMemoryAccess_x2;
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return;
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case MAP_DSP:
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if (o)
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{
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S9xSetDSP(Word >> 8, (Address + 1) & 0xffff);
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S9xSetDSP((uint8) Word, Address & 0xffff);
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}
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else
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{
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S9xSetDSP((uint8) Word, Address & 0xffff);
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S9xSetDSP(Word >> 8, (Address + 1) & 0xffff);
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}
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addCyclesInMemoryAccess_x2;
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return;
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case MAP_NONE:
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default:
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addCyclesInMemoryAccess_x2;
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return;
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}
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}
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inline uint8 * S9xGetBasePointer (uint32 Address)
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{
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uint8 *GetAddress = Memory.ReadMap[(Address & 0xffffff) >> MEMMAP_SHIFT];
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if ((pint) GetAddress >= MAP_LAST)
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{
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CHECK_ROM_MAPPING(GetAddress);
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return (GetAddress);
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}
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else if ((pint) GetAddress == MAP_LOROM_SRAM)
|
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{
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if ((Memory.SRAMMask & MEMMAP_MASK) == MEMMAP_MASK)
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return (Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff));
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}
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else if ((pint) GetAddress == MAP_HIROM_SRAM)
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{
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if ((Memory.SRAMMask & MEMMAP_MASK) == MEMMAP_MASK)
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return (Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff));
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}
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return (NULL);
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}
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|
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inline void S9xSetPCBase (uint32 Address)
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{
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Registers.PBPC = Address & 0xffffff;
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ICPU.ShiftedPB = Address & 0xff0000;
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|
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CPU.MemSpeed = memory_speed(Address);
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CPU.MemSpeedx2 = CPU.MemSpeed << 1;
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CPU.PCBase = S9xGetBasePointer(Address);
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}
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#endif
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