kopia lustrzana https://github.com/Jean-MarcHarvengt/MCUME
433 wiersze
9.9 KiB
C++
433 wiersze
9.9 KiB
C++
/*****************************************************************************\
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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This file is licensed under the Snes9x License.
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For further information, consult the LICENSE file in the root directory.
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\*****************************************************************************/
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#include "snes9x.h"
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#include "memory.h"
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#include "dma.h"
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#include "apu.h"
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//#include "snapshot.h"
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#include "cpuops.h"
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#ifdef DEBUGGER
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#include "debug.h"
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#endif
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struct SCPUState CPU;
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struct SICPU ICPU;
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struct SRegisters Registers;
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IRAM_ATTR void S9xMainLoop (void)
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{
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uint32 loops = 0;
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// uint32 slow = 0;
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uint32 Op = 0;
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CPU.Flags &= ~SCAN_KEYS_FLAG;
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#define CHECK_FOR_IRQ_CHANGE() \
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if (CPU.IRQFlagChanging) \
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{ \
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if (CPU.IRQFlagChanging & IRQ_TRIGGER_NMI) \
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{ \
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CPU.NMIPending = TRUE; \
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CPU.NMITriggerPos = CPU.Cycles + 6; \
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} \
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if (CPU.IRQFlagChanging & IRQ_CLEAR_FLAG) \
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ClearIRQ(); \
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else if (CPU.IRQFlagChanging & IRQ_SET_FLAG) \
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SetIRQ(); \
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CPU.IRQFlagChanging = IRQ_NONE; \
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}
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for (;;)
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{
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#if (RETRO_LESS_ACCURATE_CPU || RETRO_LESS_ACCURATE_MEM)
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// Only check for interrupts every 15 loops. More than that breaks too many games
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// This is temporary until we improve speed elsewhere...
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if (loops--)
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goto run_opcode;
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else
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loops = 20;
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if (CPU.Cycles >= CPU.NextEvent)
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S9xDoHEventProcessing();
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#endif
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if (CPU.NMIPending)
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{
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#ifdef DEBUGGER
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if (Settings.TraceHCEvent)
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S9xTraceFormattedMessage ("Comparing %d to %d\n", CPU.NMITriggerPos, CPU.Cycles);
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#endif
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if (CPU.NMITriggerPos <= CPU.Cycles)
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{
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CPU.NMIPending = FALSE;
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CPU.NMITriggerPos = 0xffff;
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if (CPU.WaitingForInterrupt)
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{
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CPU.WaitingForInterrupt = FALSE;
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Registers.PCw++;
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CPU.Cycles += TWO_CYCLES + ONE_DOT_CYCLE / 2;
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if (CPU.Cycles >= CPU.NextEvent)
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S9xDoHEventProcessing();
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}
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CHECK_FOR_IRQ_CHANGE();
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S9xOpcode_NMI();
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}
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}
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if (CPU.Cycles >= CPU.NextIRQTimer)
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{
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#ifdef DEBUGGER
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S9xTraceMessage ("Timer triggered\n");
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#endif
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S9xUpdateIRQPositions(false);
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CPU.IRQLine = TRUE;
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}
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if (CPU.IRQLine)
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{
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if (CPU.WaitingForInterrupt)
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{
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CPU.WaitingForInterrupt = FALSE;
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Registers.PCw++;
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CPU.Cycles += TWO_CYCLES + ONE_DOT_CYCLE / 2;
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if (CPU.Cycles >= CPU.NextEvent)
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S9xDoHEventProcessing();
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}
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if (!CheckFlag(IRQ))
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{
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/* The flag pushed onto the stack is the new value */
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CHECK_FOR_IRQ_CHANGE();
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S9xOpcode_IRQ();
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}
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}
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/* Change IRQ flag for instructions that set it only on last cycle */
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CHECK_FOR_IRQ_CHANGE();
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#ifdef DEBUGGER
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if ((CPU.Flags & BREAK_FLAG) && !(CPU.Flags & SINGLE_STEP_FLAG))
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{
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for (int Break = 0; Break != 6; Break++)
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{
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if (S9xBreakpoint[Break].Enabled &&
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S9xBreakpoint[Break].Bank == Registers.PB &&
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S9xBreakpoint[Break].Address == Registers.PCw)
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{
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if (S9xBreakpoint[Break].Enabled == 2)
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S9xBreakpoint[Break].Enabled = TRUE;
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else
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CPU.Flags |= DEBUG_MODE_FLAG;
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}
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}
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}
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if (CPU.Flags & DEBUG_MODE_FLAG)
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break;
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if (CPU.Flags & TRACE_FLAG)
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S9xTrace();
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if (CPU.Flags & SINGLE_STEP_FLAG)
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{
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CPU.Flags &= ~SINGLE_STEP_FLAG;
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CPU.Flags |= DEBUG_MODE_FLAG;
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}
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#endif
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if (CPU.Flags & SCAN_KEYS_FLAG)
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{
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#ifdef DEBUGGER
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if (!(CPU.Flags & FRAME_ADVANCE_FLAG))
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#endif
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{
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// S9xSyncSpeed();
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}
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break;
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}
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run_opcode:
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// If we're crossing a page or PCBase isn't set then we must use the slow route!
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if (CPU.PCBase == NULL || (Registers.PCw & MEMMAP_MASK) + 4 >= MEMMAP_BLOCK_SIZE)
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{
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Op = S9xGetByte(Registers.PBPC);
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OpenBus = Op;
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Registers.PCw++;
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(S9xOpcodesSlow[Op])();
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// slow++;
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}
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else
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{
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Op = CPU.PCBase[Registers.PCw];
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CPU.Cycles += CPU.MemSpeed;
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Registers.PCw++;
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(ICPU.S9xOpcodes[Op])();
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}
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}
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// printf("fast: %d / slow: %d\n", loops - slow, slow);
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}
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IRAM_ATTR void S9xDoHEventProcessing (void)
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{
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#ifdef DEBUGGER
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const char eventname[7][32] =
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{
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"",
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"HC_HBLANK_START_EVENT",
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"HC_HDMA_START_EVENT ",
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"HC_HCOUNTER_MAX_EVENT",
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"HC_HDMA_INIT_EVENT ",
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"HC_RENDER_EVENT ",
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"HC_WRAM_REFRESH_EVENT"
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};
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#endif
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do
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{
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#ifdef DEBUGGER
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if (Settings.TraceHCEvent)
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S9xTraceFormattedMessage("--- HC event processing (%s) expected HC:%04d executed HC:%04d VC:%04d",
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eventname[CPU.WhichEvent], CPU.NextEvent, CPU.Cycles, CPU.V_Counter);
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#endif
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switch (CPU.WhichEvent)
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{
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case HC_HBLANK_START_EVENT:
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CPU.WhichEvent = HC_HDMA_START_EVENT;
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CPU.NextEvent = SNES_HDMA_START_HC;
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break;
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case HC_HDMA_START_EVENT:
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CPU.WhichEvent = HC_HCOUNTER_MAX_EVENT;
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CPU.NextEvent = SNES_CYCLES_PER_SCANLINE;
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if (PPU.HDMA && CPU.V_Counter <= PPU.ScreenHeight)
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{
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#ifdef DEBUGGER
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S9xTraceFormattedMessage("*** HDMA Transfer HC:%04d, Channel:%02x", CPU.Cycles, PPU.HDMA);
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#endif
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PPU.HDMA = S9xDoHDMA(PPU.HDMA);
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}
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break;
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case HC_HCOUNTER_MAX_EVENT:
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S9xAPUEndScanline();
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CPU.Cycles -= SNES_CYCLES_PER_SCANLINE;
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if (CPU.NMITriggerPos != 0xffff)
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CPU.NMITriggerPos -= SNES_CYCLES_PER_SCANLINE;
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if (CPU.NextIRQTimer != 0x0fffffff)
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CPU.NextIRQTimer -= SNES_CYCLES_PER_SCANLINE;
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S9xAPUSetReferenceTime(CPU.Cycles);
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CPU.V_Counter++;
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if (CPU.V_Counter >= SNES_MAX_VCOUNTER) // V ranges from 0 to MAX_VCOUNTER - 1
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{
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CPU.V_Counter = 0;
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Memory.PPU_IO[0x13F] ^= 0x80;
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PPU.RangeTimeOver = 0;
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// FIXME: reading $4210 will wait 2 cycles, then perform reading, then wait 4 more cycles.
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Memory.CPU_IO[0x210] = 2;
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ICPU.Frame++;
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PPU.HVBeamCounterLatched = 0;
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}
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if (CPU.V_Counter == PPU.ScreenHeight + FIRST_VISIBLE_LINE) // VBlank starts from V=225(240).
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{
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S9xEndScreenRefresh();
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CPU.Flags |= SCAN_KEYS_FLAG;
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PPU.HDMA = 0;
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// Bits 7 and 6 of $4212 are computed when read in S9xGetPPU.
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IPPU.MaxBrightness = PPU.Brightness;
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PPU.ForcedBlanking = (Memory.PPU_IO[0x100] >> 7) & 1;
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if (!PPU.ForcedBlanking)
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{
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PPU.OAMAddr = PPU.SavedOAMAddr;
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uint8 tmp = 0;
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if (PPU.OAMPriorityRotation)
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tmp = (PPU.OAMAddr & 0xFE) >> 1;
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if ((PPU.OAMFlip & 1) || PPU.FirstSprite != tmp)
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{
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PPU.FirstSprite = tmp;
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IPPU.OBJChanged = TRUE;
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}
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PPU.OAMFlip = 0;
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}
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// FIXME: writing to $4210 will wait 6 cycles.
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Memory.CPU_IO[0x210] = 0x80 | 2;
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if (Memory.CPU_IO[0x200] & 0x80)
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{
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#ifdef DEBUGGER
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if (Settings.TraceHCEvent)
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S9xTraceFormattedMessage ("NMI Scheduled for next scanline.");
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#endif
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// FIXME: triggered at HC=6, checked just before the final CPU cycle,
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// then, when to call S9xOpcode_NMI()?
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CPU.NMIPending = TRUE;
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CPU.NMITriggerPos = 6 + 6;
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}
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}
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if (CPU.V_Counter == PPU.ScreenHeight + 3) // FIXME: not true
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{
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if (Memory.CPU_IO[0x200] & 1)
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S9xDoAutoJoypad();
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}
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if (CPU.V_Counter == FIRST_VISIBLE_LINE) // V=1
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S9xStartScreenRefresh();
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CPU.WhichEvent = HC_HDMA_INIT_EVENT;
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CPU.NextEvent = SNES_HDMA_INIT_HC;
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break;
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case HC_HDMA_INIT_EVENT:
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CPU.WhichEvent = HC_RENDER_EVENT;
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CPU.NextEvent = SNES_RENDER_START_HC;
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if (CPU.V_Counter == 0)
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{
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#ifdef DEBUGGER
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S9xTraceFormattedMessage("*** HDMA Init HC:%04d, Channel:%02x", CPU.Cycles, PPU.HDMA);
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#endif
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S9xStartHDMA();
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}
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break;
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case HC_RENDER_EVENT:
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if (CPU.V_Counter >= FIRST_VISIBLE_LINE && CPU.V_Counter <= PPU.ScreenHeight)
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S9xRenderLine((uint8) (CPU.V_Counter - FIRST_VISIBLE_LINE));
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CPU.WhichEvent = HC_WRAM_REFRESH_EVENT;
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CPU.NextEvent = SNES_WRAM_REFRESH_HC;
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break;
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case HC_WRAM_REFRESH_EVENT:
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#ifdef DEBUGGER
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S9xTraceFormattedMessage("*** WRAM Refresh HC:%04d", CPU.Cycles);
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#endif
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CPU.Cycles += SNES_WRAM_REFRESH_CYCLES;
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CPU.WhichEvent = HC_HBLANK_START_EVENT;
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CPU.NextEvent = SNES_HBLANK_START_HC;
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break;
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}
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#ifdef DEBUGGER
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if (Settings.TraceHCEvent)
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S9xTraceFormattedMessage("--- HC event rescheduled (%s) expected HC:%04d current HC:%04d",
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eventname[CPU.WhichEvent], CPU.NextEvent, CPU.Cycles);
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#endif
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} while (CPU.Cycles >= CPU.NextEvent);
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}
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static void S9xSoftResetCPU (void)
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{
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CPU.Cycles = 182; // Or 188. This is the cycle count just after the jump to the Reset Vector.
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CPU.V_Counter = 0;
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CPU.Flags = CPU.Flags & (DEBUG_MODE_FLAG | TRACE_FLAG);
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CPU.PCBase = NULL;
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CPU.NMIPending = FALSE;
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CPU.IRQLine = FALSE;
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CPU.MemSpeed = SLOW_ONE_CYCLE;
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CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
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CPU.FastROMSpeed = SLOW_ONE_CYCLE;
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CPU.InDMA = FALSE;
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CPU.InHDMA = FALSE;
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CPU.InDMAorHDMA = FALSE;
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CPU.InWRAMDMAorHDMA = FALSE;
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CPU.HDMARanInDMA = 0;
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CPU.CurrentDMAorHDMAChannel = -1;
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CPU.WhichEvent = HC_RENDER_EVENT;
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CPU.NextEvent = SNES_RENDER_START_HC;
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CPU.WaitingForInterrupt = FALSE;
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CPU.AutoSaveTimer = 0;
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CPU.SRAMModified = FALSE;
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Registers.PBPC = 0;
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Registers.PB = 0;
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Registers.PCw = S9xGetWord(0xfffc);
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OpenBus = Registers.PCh;
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Registers.D.W = 0;
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Registers.DB = 0;
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Registers.SH = 1;
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Registers.SL -= 3;
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Registers.XH = 0;
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Registers.YH = 0;
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ICPU.ShiftedPB = 0;
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ICPU.ShiftedDB = 0;
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SetFlags(MemoryFlag | IndexFlag | IRQ | Emulation);
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ClearFlags(Decimal);
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CPU.NMITriggerPos = 0xffff;
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CPU.NextIRQTimer = 0x0fffffff;
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CPU.IRQFlagChanging = IRQ_NONE;
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S9xSetPCBase(Registers.PBPC);
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S9xFixCycles();
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}
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static void S9xResetCPU (void)
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{
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S9xSoftResetCPU();
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Registers.SL = 0xff;
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Registers.P.W = 0;
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Registers.A.W = 0;
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Registers.X.W = 0;
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Registers.Y.W = 0;
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SetFlags(MemoryFlag | IndexFlag | IRQ | Emulation);
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ClearFlags(Decimal);
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}
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void S9xReset (void)
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{
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memset(Memory.RAM, 0x55, 0x20000);
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memset(Memory.VRAM, 0x00, 0x10000);
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memset(Memory.CPU_IO, 0, 0x400);
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S9xResetCPU();
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S9xResetPPU();
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S9xResetDMA();
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S9xResetAPU();
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if (Settings.DSP)
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S9xResetDSP();
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}
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void S9xSoftReset (void)
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{
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memset(Memory.CPU_IO, 0, 0x400);
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S9xSoftResetCPU();
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S9xSoftResetPPU();
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S9xResetDMA();
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S9xSoftResetAPU();
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if (Settings.DSP)
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S9xResetDSP();
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}
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