kopia lustrzana https://github.com/Jean-MarcHarvengt/MCUME
196 wiersze
6.4 KiB
C
196 wiersze
6.4 KiB
C
/** EMULib Emulation Library *********************************/
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/** **/
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/** I8251.c **/
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/** **/
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/** This file contains emulation for the Intel 8251 UART **/
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/** chip and the 8253 timer chip implementing a generic **/
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/** RS232 interface. **/
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/** **/
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/** Copyright (C) Marat Fayzullin 2004-2005 **/
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/** Maarten ter Huurne 2000 **/
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/** You are not allowed to distribute this software **/
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/** commercially. Please, notify me, if you make any **/
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/** changes to this file. **/
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/*************************************************************/
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#include "I8251.h"
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/** Reset8251 ************************************************/
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/** Reset 8251 chip, assigning In and Out to the input and **/
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/** output streams. **/
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/*************************************************************/
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void Reset8251(register I8251 *D,FILE *In,FILE *Out)
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{
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D->IRQMask = 0x0F; /* All interrupts on */
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D->IRQs = 0x00; /* No interrupts yet */
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D->Mode = 1; /* Setting mode next */
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D->Flow = 0x00; /* Flow control off */
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D->NextChr = -1; /* No data yet */
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/* Assign input and output streams */
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D->In = In? In:stdin;
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D->Out = Out? Out:stdout;
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}
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/** Rd8251 ***************************************************/
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/** Read a byte from a given 8251 register. All values of R **/
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/** will be truncated to 3 bits as there are only 8 regs. **/
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/*************************************************************/
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byte Rd8251(register I8251 *D,register byte R)
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{
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register int J;
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/* We only have 8 addressable ports */
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R&=0x07;
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switch(R)
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{
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case 0: /* Data */
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if(D->Flow)
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{
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if(D->NextChr<0) D->NextChr=fgetc(D->In);
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J=D->NextChr;
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D->NextChr=-1;
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return((J<0? 0xFF:J)&((0x20<<((D->Control&0x0C)>>2))-1));
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}
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return(0xFF);
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case 1: /* Status */
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if(D->NextChr<0) D->NextChr=fgetc(D->In);
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return(D->Flow&&(D->NextChr>=0)? 0x87:0x85);
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/*
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76543210
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1....... data set ready (dsr)
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.1...... sync detect, sync only
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..1..... framing error (fe), async only
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...1.... overrun error (oe)
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....1... parity error (pe)
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.....1.. transmitter empty
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......1. receiver ready
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.......1 transmitter ready
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D->Flow is checked first, so that stdin input doesn't block
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fMSX until it's actually being read by the emulated MSX.
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*/
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case 0x82: /* Status of CTS, timer/counter 2, RI and CD */
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return(0x7F);
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/*
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76543210
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1....... CTS (Clear To Send) 0=asserted
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.1...... timer/counter output-2 from 8253
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..XXXX.. reserved
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......1. RI (Ring Indicator) 0=asserted
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.......1 CD (Carrier Detect) 0=asserted
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RI and CD are optional. If only one of them is implemented,
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it must be CD. Implemented like this:
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- CTS always returns 0 (asserted)
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- Everything else is not implemented
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*/
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}
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/* Other RS232 ports:
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3: not standardised - unused
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4: 8253 counter 0 - not implemented
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5: 8253 counter 1 - not implemented
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6: 8253 counter 2 - not implemented
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7: 8253 mode register - write only
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*/
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return(0xFF);
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}
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/** Wr8251 ***************************************************/
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/** Write a byte to a given 8251 register. All values of R **/
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/** will be truncated to 3 bits as there are only 8 regs. **/
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/*************************************************************/
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void Wr8251(register I8251 *D,register byte R,register byte V)
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{
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/* We only have 8 addressable ports */
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R&=0x07;
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switch(R)
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{
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case 0: /* Data */
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fputc(V&((0x20<<((D->Control&0x0C)>>2))-1),D->Out);
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fflush(D->Out);
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return;
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/*
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TODO: Flush the stream at appropriate intervals, instead of
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flushing for every single character. If flushing after every
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character remains, make the stream unbuffered.
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*/
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case 1: /* Command */
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if(D->Mode)
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{
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D->Control=V;
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D->Mode=0;
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/* Set mode:
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......00 sync mode
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......01 async, baud rate factor is 1
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......10 async, baud rate factor is 16
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......11 async, baud rate factor is 64
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....00.. character length is 5 bits
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....01.. character length is 6 bits
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....10.. character length is 7 bits
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....11.. character length is 8 bits
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...1.... parity enable
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..1..... even/odd parity
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.1...... sync: external sync detect (syndet) is an input/output
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1....... sync: single/double character sync
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00...... async: invalid
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01...... async: 1 stop bit
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10...... async: 1.5 stop bits
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11...... async: 2 stop bits
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*/
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}
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else
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{
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D->Mode=V&0x40;
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D->Flow=(V>>4)&0x02;
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/* Execute command:
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76543210
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1....... enter hunt mode (enable search for sync characters)
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.1...... internal reset
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..1..... request to send (rts)
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...1.... reset error flags (pe,oe,fe)
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....1... send break character
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.....1.. receive enable
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......1. data terminal ready (dtr)
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.......1 transmit enable
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Only RESET (bit6) and DTR (bit2) are implemented.
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*/
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}
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return;
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case 2: /* Interrupt mask register */
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D->IRQMask=V;
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return;
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/*
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76543210
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XXXX.... reserved
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....1... timer interrupt from 8253 channel-2 (0=enable int)
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.....1.. sync character detect/break detect (0=enable int)
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......1. transmit data ready (TxReady) (0=enable int)
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.......1 receive data ready (RxReady) (0=enable int)
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Initially all interrupts are disabled. RxReady interrupt must be
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implemented, the others are optional.
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However, currently no interrupt at all is implemented. The result
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is that only one character is read per VDP interrupt, so serial
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communication is 50/60 baud.
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*/
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}
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/* Other RS232 ports:
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3: not standardised - unused
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4: 8253 counter 0 - not implemented
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5: 8253 counter 1 - not implemented
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6: 8253 counter 2 - not implemented
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7: 8253 mode register - not implemented
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*/
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} |