kopia lustrzana https://github.com/Jean-MarcHarvengt/MCUME
558 wiersze
17 KiB
C
558 wiersze
17 KiB
C
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#include "shared.h"
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#include "vcnt.h"
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#include "hcnt.h"
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#include "hvc.h"
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/* Pack and unpack CRAM data */
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#define PACK_CRAM(d) ((((d)&0xE00)>>9)|(((d)&0x0E0)>>2)|(((d)&0x00E)<<5))
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#define UNPACK_CRAM(d) ((((d)&0x1C0)>>5)|((d)&0x038)<<2|(((d)&0x007)<<9))
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/* Mark a pattern as dirty */
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#define MARK_BG_DIRTY(addr) \
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{ \
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int name = (addr >> 5) & 0x7FF; \
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if(bg_name_dirty[name] == 0) \
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{ \
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bg_name_list[bg_list_index] = name; \
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bg_list_index += 1; \
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} \
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bg_name_dirty[name] |= (1 << ((addr >> 2) & 0x07)); \
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}
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/* Tables that define the playfield layout */
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uint8 shift_table[] = {6, 7, 0, 8};
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uint8 col_mask_table[] = {0x1F, 0x3F, 0x1F, 0x7F};
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uint16 row_mask_table[] = {0x0FF, 0x1FF, 0x2FF, 0x3FF};
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uint32 y_mask_table[] = {0x1FC0, 0x1FC0, 0x1F80, 0x1F00};
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uint8 sat[0x400]; /* Internal copy of sprite attribute table */
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//uint8 vram[0x10000]; /* Video RAM (64Kx8) */
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uint8 cram[0x80]; /* On-chip color RAM (64x9) */
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uint8 vsram[0x80]; /* On-chip vertical scroll RAM (40x11) */
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uint8 reg[0x20]; /* Internal VDP registers (23x8) */
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uint16 addr; /* Address register */
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uint16 addr_latch; /* Latched A15, A14 of address */
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uint8 code; /* Code register */
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uint8 pending; /* Pending write flag */
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uint16 buffer; /* Read buffer */
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uint16 status; /* VDP status flags */
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uint16 ntab; /* Name table A base address */
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uint16 ntbb; /* Name table B base address */
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uint16 ntwb; /* Name table W base address */
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uint16 satb; /* Sprite attribute table base address */
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uint16 hscb; /* Horizontal scroll table base address */
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uint16 sat_base_mask; /* Base bits of SAT */
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uint16 sat_addr_mask; /* Index bits of SAT */
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uint8 is_color_dirty; /* 1= One or more colors have changed */
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uint8 color_dirty[0x40]; /* 1= This color is dirty */
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uint8 border; /* Border color index */
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uint8 is_border_dirty; /* 1= The border color has changed */
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//uint8 bg_name_dirty[0x800]; /* 1= This pattern is dirty */
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//uint16 bg_name_list[0x800]; /* List of modified pattern indices */
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uint16 bg_list_index; /* # of modified patterns in list */
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//uint8 bg_pattern_cache[0x80000];/* Cached and flipped patterns */
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uint8 playfield_shift; /* Width of planes A, B (in bits) */
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uint8 playfield_col_mask; /* Vertical scroll mask */
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uint16 playfield_row_mask; /* Horizontal scroll mask */
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uint32 y_mask; /* Name table Y-index bits mask */
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int hint_pending; /* 0= Line interrupt is pending */
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int vint_pending; /* 1= Frame interrupt is pending */
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int counter; /* Raster counter */
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int dma_fill; /* 1= DMA fill has been requested */
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int im2_flag; /* 1= Interlace mode 2 is being used */
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int frame_end; /* End-of-frame (IRQ line) */
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int v_counter; /* VDP scan line counter */
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int v_update; /* 1= VC was updated by a ctrl or HV read */
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void (*color_update)(int index, uint16 data);
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/*--------------------------------------------------------------------------*/
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/* Init, reset, shutdown functions */
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/*--------------------------------------------------------------------------*/
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void vdp_init(void)
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{
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}
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void vdp_reset(void)
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{
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memset(sat, 0, sizeof(sat));
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memset(vram, 0, VRAM_SIZE);
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memset(cram, 0, sizeof(cram));
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memset(vsram, 0, sizeof(vsram));
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memset(reg, 0, sizeof(reg));
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addr = addr_latch = code = pending = buffer = status = 0;
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ntab = ntbb = ntwb = satb = hscb = 0;
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sat_base_mask = 0xFE00;
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sat_addr_mask = 0x01FF;
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/* Mark all colors as dirty to force a palette update */
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is_color_dirty = 1;
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memset(color_dirty, 1, 0x40);
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border = 0x00;
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is_border_dirty = 1;
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memset(bg_name_dirty, 0, BGNAMEDIRTY_SIZE);
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memset(bg_name_list, 0, BGNAME_SIZE);
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bg_list_index = 0;
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memset(bg_pattern_cache, 0, BGPATTERN_CACH_SIZE);
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playfield_shift = 6;
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playfield_col_mask = 0x1F;
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playfield_row_mask = 0x0FF;
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y_mask = 0x1FC0;
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hint_pending = vint_pending = 0;
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counter = 0;
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frame_end = 0xE0;
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v_counter = v_update = 0;
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/* Initialize viewport */
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gbitmap.viewport.x = 0x20;
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gbitmap.viewport.y = 0x20;
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gbitmap.viewport.w = 256;
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gbitmap.viewport.h = 224;
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gbitmap.viewport.oh = 256;
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gbitmap.viewport.ow = 224;
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gbitmap.viewport.changed = 1;
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}
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void vdp_shutdown(void)
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{
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}
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/*--------------------------------------------------------------------------*/
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/* Memory access functions */
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/*--------------------------------------------------------------------------*/
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void vdp_ctrl_w(uint16 data)
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{
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if(pending == 0)
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{
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if((data & 0xC000) == 0x8000)
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{
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uint8 r = (data >> 8) & 0x1F;
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uint8 d = (data >> 0) & 0xFF;
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vdp_reg_w(r, d);
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}
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else
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{
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pending = 1;
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}
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addr = ((addr_latch & 0xC000) | (data & 0x3FFF)) & 0xFFFF;
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code = ((code & 0x3C) | ((data >> 14) & 0x03)) & 0x3F;
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}
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else
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{
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/* Clear pending flag */
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pending = 0;
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/* Update address and code registers */
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addr = ((addr & 0x3FFF) | ((data & 3) << 14)) & 0xFFFF;
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code = ((code & 0x03) | ((data >> 2) & 0x3C)) & 0x3F;
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/* Save address bits A15 and A14 */
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addr_latch = (addr & 0xC000);
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if((code & 0x20) && (reg[1] & 0x10))
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{
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switch(reg[23] & 0xC0)
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{
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case 0x00: /* V bus to VDP DMA */
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case 0x40: /* V bus to VDP DMA */
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dma_vbus();
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break;
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case 0x80: /* VRAM fill */
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dma_fill = 1;
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break;
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case 0xC0: /* VRAM copy */
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dma_copy();
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break;
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}
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}
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}
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}
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uint16 vdp_ctrl_r(void)
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{
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#if 0
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int cycles = m68k_cycles_run();
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uint16 temp = status;
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/* Clear pending flag */
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pending = 0;
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/* VBlank flag is set when the screen is disabled */
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if((reg[1] & 0x40) == 0x00)
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{
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temp |= 0x0008;
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}
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/* Clear collision flag on reads */
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status &= ~0x0020;
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/* Set HBlank flag based on H counter */
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if(reg[12] & 1)
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{
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int hc = cycle2hc40[(cycles % 487)];
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if((hc >= 0xB6) && (hc <= 0xFF)) temp |= 0x0004;
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}
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else
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{
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int hc = cycle2hc32[(cycles % 487)];
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if((hc >= 0x93) && (hc <= 0xFF)) temp |= 0x0004;
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}
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/* Flag FIFO as empty */
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temp |= 0x0200;
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/* Clear unused bits */
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temp &= 0x03FF;
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return (temp);
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#else
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uint16 temp = (0x4e71 & 0xFC00);
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pending = 0;
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status &= ~0x0020; // clear sprite hit flag on reads
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status |= 0x0200; // fifo empty
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status ^= 0x0004; /* hack (red zone) */
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temp |= (status & 0x03BF); // clear spr over
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return (temp);
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#endif
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}
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void vdp_data_w(uint16 data)
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{
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/* Clear pending flag */
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pending = 0;
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switch(code & 0x0F)
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{
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case 0x01: /* VRAM */
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/* Byte-swap data if A0 is set */
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if(addr & 1) data = (data >> 8) | (data << 8);
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/* Copy SAT data to the internal SAT */
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if((addr & sat_base_mask) == satb)
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{
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*(uint16 *)&sat[addr & sat_addr_mask] = data;
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}
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/* Only write unique data to VRAM */
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if(data != *(uint16 *)&vram[addr & 0xFFFE])
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{
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/* Write data to VRAM */
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*(uint16 *)&vram[addr & 0xFFFE] = data;
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/* Update the pattern cache */
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MARK_BG_DIRTY(addr);
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}
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break;
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case 0x03: /* CRAM */
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{
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uint16 *p = (uint16 *)&cram[(addr & 0x7E)];
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data &= 0x0EEE;
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if(data != *p)
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{
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int index = (addr >> 1) & 0x3F;
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*p = PACK_CRAM(data);
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if((index & 0x0F) != 0x00)
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{
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color_dirty[index] = is_color_dirty = 1;
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}
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if(index == border)
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{
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is_border_dirty = 1;
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if(color_update)
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{
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color_update(0x00, *p);
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color_update(0x40, *p);
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color_update(0x80, *p);
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}
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}
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if(color_update) color_update(index, *p);
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}
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}
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break;
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case 0x05: /* VSRAM */
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*(uint16 *)&vsram[(addr & 0x7E)] = data;
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break;
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}
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/* Bump address register */
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addr += reg[15];
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if(dma_fill)
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{
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int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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if(!length) length = 0x10000;
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do {
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vram[(addr & 0xFFFF)] = (data >> 8) & 0xFF;
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MARK_BG_DIRTY(addr);
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addr += reg[15];
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} while(--length);
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dma_fill = 0;
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}
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}
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uint16 vdp_data_r(void)
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{
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uint16 temp = 0;
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/* Clear pending flag */
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pending = 0;
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switch(code & 0x0F)
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{
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case 0x00: /* VRAM */
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temp = *(uint16 *)&vram[(addr & 0xFFFE)];
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break;
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case 0x08: /* CRAM */
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temp = *(uint16 *)&cram[(addr & 0x7E)];
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temp = UNPACK_CRAM(temp);
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break;
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case 0x04: /* VSRAM */
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temp = *(uint16 *)&vsram[(addr & 0x7E)];
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break;
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}
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/* Bump address register */
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addr += reg[15];
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/* return data */
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return (temp);
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}
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/*
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The reg[] array is updated at the *end* of this function, so the new
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register data can be compared with the previous data.
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*/
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void vdp_reg_w(uint8 r, uint8 d)
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{
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switch(r)
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{
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case 0x00: /* CTRL #1 */
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if(hint_pending)
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{
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if(d & 0x10)
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{
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m68k_set_irq(4);
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}
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else
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{
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/* Cancel pending level 4 interrupt */
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m68k_set_irq(0);
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}
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}
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break;
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case 0x01: /* CTRL #2 */
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if(vint_pending)
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{
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if(d & 0x20)
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{
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m68k_set_irq(6);
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}
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else
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{
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/* Cancel pending level 6 interrupt */
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m68k_set_irq(0);
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}
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}
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/* Change the frame timing */
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frame_end = (d & 8) ? 0xF0 : 0xE0;
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/* Check if the viewport height has actually been changed */
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if((reg[1] & 8) != (d & 8))
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{
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/* Update the height of the viewport */
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gbitmap.viewport.oh = gbitmap.viewport.h;
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gbitmap.viewport.h = (d & 8) ? 240 : 224;
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gbitmap.viewport.changed = 1;
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}
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break;
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case 0x02: /* NTAB */
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ntab = (d << 10) & 0xE000;
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break;
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case 0x03: /* NTWB */
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ntwb = (d << 10) & 0xF800;
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if(reg[12] & 1) ntwb &= 0xF000;
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break;
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case 0x04: /* NTBB */
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ntbb = (d << 13) & 0xE000;
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break;
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case 0x05: /* SATB */
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sat_base_mask = (reg[12] & 1) ? 0xFC00 : 0xFE00;
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sat_addr_mask = (reg[12] & 1) ? 0x03FF : 0x01FF;
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satb = (d << 9) & sat_base_mask;
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break;
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case 0x07:
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d &= 0x3F;
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/* Check if the border color has actually changed */
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if(border != d)
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{
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/* Mark the border color as modified */
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border = d;
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is_border_dirty = 1;
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if(color_update)
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{
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color_update(0x00, *(uint16 *)&cram[(border << 1)]);
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color_update(0x40, *(uint16 *)&cram[(border << 1)]);
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color_update(0x80, *(uint16 *)&cram[(border << 1)]);
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}
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}
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break;
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case 0x0C:
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/* Check if the viewport width has actually been changed */
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if((reg[0x0C] & 1) != (d & 1))
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{
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/* Update the width of the viewport */
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gbitmap.viewport.ow = gbitmap.viewport.w;
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gbitmap.viewport.w = (d & 1) ? 320 : 256;
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gbitmap.viewport.changed = 1;
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}
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/* See if the S/TE mode bit has changed */
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if((reg[0x0C] & 8) != (d & 8))
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{
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int i;
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reg[0x0C] = d;
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/* Update colors */
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if(color_update)
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{
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for(i = 0; i < 0x40; i += 1)
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{
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color_update(i, *(uint16 *)&cram[i << 1]);
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}
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color_update(0x00, *(uint16 *)&cram[border << 1]);
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color_update(0x40, *(uint16 *)&cram[border << 1]);
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color_update(0x80, *(uint16 *)&cram[border << 1]);
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}
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/* Flush palette */
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is_color_dirty = is_border_dirty = 1;
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memset(color_dirty, 1, 0x40);
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}
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/* Check interlace mode 2 setting */
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im2_flag = ((d & 0x06) == 0x06) ? 1 : 0;
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/* The following register updates check this value */
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reg[0x0C] = d;
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/* Update display-dependant registers */
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vdp_reg_w(0x03, reg[0x03]);
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vdp_reg_w(0x05, reg[0x05]);
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break;
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case 0x0D: /* HSCB */
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hscb = (d << 10) & 0xFC00;
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break;
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case 0x10: /* Playfield size */
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playfield_shift = shift_table[(d & 3)];
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playfield_col_mask = col_mask_table[(d & 3)];
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playfield_row_mask = row_mask_table[(d >> 4) & 3];
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y_mask = y_mask_table[(d & 3)];
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break;
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}
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/* Write new register value */
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reg[r] = d;
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}
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uint16 vdp_hvc_r(void)
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{
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int cycles = m68k_cycles_run();
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uint8 *hctab = (reg[12] & 1) ? cycle2hc40 : cycle2hc32;
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int vc = vc28[v_counter];
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int hc = hctab[(cycles % 487)];
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return (vc << 8 | hc);
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}
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/*
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VRAM to VRAM copy
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Read byte from VRAM (source), write to VRAM (addr),
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bump source and add r15 to addr.
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- see how source addr is affected
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(can it make high source byte inc?)
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*/
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void dma_copy(void)
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{
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int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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int source = (reg[22] << 8 | reg[21]) & 0xFFFF;
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if(!length) length = 0x10000;
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do {
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uint8 temp = vram[source];
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vram[addr] = temp;
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MARK_BG_DIRTY(addr);
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source = (source + 1) & 0xFFFF;
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addr = (addr + reg[15]) & 0xFFFF;
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} while (--length);
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reg[19] = (length >> 0) & 0xFF;
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reg[20] = (length >> 8) & 0xFF;
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}
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void dma_vbus(void)
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{
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uint32 base, source = ((reg[23] & 0x7F) << 17 | reg[22] << 9 | reg[21] << 1) & 0xFFFFFE;
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uint32 length = (reg[20] << 8 | reg[19]) & 0xFFFF;
|
|
|
|
if(!length) length = 0x10000;
|
|
base = source;
|
|
|
|
do {
|
|
uint16 temp = vdp_dma_r(source);
|
|
source += 2;
|
|
source = ((base & 0xFE0000) | (source & 0x1FFFF));
|
|
vdp_data_w(temp);
|
|
} while (--length);
|
|
|
|
reg[19] = (length >> 0) & 0xFF;
|
|
reg[20] = (length >> 8) & 0xFF;
|
|
|
|
reg[21] = (source >> 1) & 0xFF;
|
|
reg[22] = (source >> 9) & 0xFF;
|
|
reg[23] = (reg[23] & 0x80) | ((source >> 17) & 0x7F);
|
|
}
|
|
|
|
|
|
void vdp_test_w(uint16 value)
|
|
{
|
|
}
|
|
|
|
|