kopia lustrzana https://github.com/Jean-MarcHarvengt/MCUME
952 wiersze
18 KiB
C
Executable File
952 wiersze
18 KiB
C
Executable File
#include <stdio.h>
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#include "e6809.h"
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#include "vecx.h"
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#include "osint.h"
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#include "e8910.h"
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#define einline __inline
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//unsigned char rom[8192];
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#include "rom.h"
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unsigned char cart[32768];
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static unsigned char ram[1024];
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/* the sound chip registers */
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unsigned snd_regs[16];
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static unsigned snd_select;
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/* the via 6522 registers */
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static unsigned via_ora;
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static unsigned via_orb;
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static unsigned via_ddra;
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static unsigned via_ddrb;
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static unsigned via_t1on; /* is timer 1 on? */
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static unsigned via_t1int; /* are timer 1 interrupts allowed? */
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static unsigned via_t1c;
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static unsigned via_t1ll;
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static unsigned via_t1lh;
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static unsigned via_t1pb7; /* timer 1 controlled version of pb7 */
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static unsigned via_t2on; /* is timer 2 on? */
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static unsigned via_t2int; /* are timer 2 interrupts allowed? */
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static unsigned via_t2c;
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static unsigned via_t2ll;
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static unsigned via_sr;
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static unsigned via_srb; /* number of bits shifted so far */
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static unsigned via_src; /* shift counter */
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static unsigned via_srclk;
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static unsigned via_acr;
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static unsigned via_pcr;
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static unsigned via_ifr;
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static unsigned via_ier;
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static unsigned via_ca2;
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static unsigned via_cb2h; /* basic handshake version of cb2 */
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static unsigned via_cb2s; /* version of cb2 controlled by the shift register */
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/* analog devices */
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static unsigned alg_rsh; /* zero ref sample and hold */
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static unsigned alg_xsh; /* x sample and hold */
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static unsigned alg_ysh; /* y sample and hold */
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static unsigned alg_zsh; /* z sample and hold */
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unsigned alg_jch0; /* joystick direction channel 0 */
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unsigned alg_jch1; /* joystick direction channel 1 */
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unsigned alg_jch2; /* joystick direction channel 2 */
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unsigned alg_jch3; /* joystick direction channel 3 */
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static unsigned alg_jsh; /* joystick sample and hold */
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static unsigned alg_compare;
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static long alg_dx; /* delta x */
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static long alg_dy; /* delta y */
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static long alg_curr_x; /* current x position */
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static long alg_curr_y; /* current y position */
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static unsigned alg_vectoring; /* are we drawing a vector right now? */
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static long alg_vector_x0;
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static long alg_vector_y0;
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static long alg_vector_x1;
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static long alg_vector_y1;
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static long alg_vector_dx;
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static long alg_vector_dy;
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static unsigned char alg_vector_color;
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long vector_draw_cnt;
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long vector_erse_cnt;
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vector_t * vectors_set; //[2 * VECTOR_CNT];
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vector_t *vectors_draw;
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vector_t *vectors_erse;
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//static long vector_hash[VECTOR_HASH];
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long * vector_hash;
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static long fcycles;
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/* update the snd chips internal registers when via_ora/via_orb changes */
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static einline void snd_update (void)
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{
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switch (via_orb & 0x18) {
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case 0x00:
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/* the sound chip is disabled */
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break;
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case 0x08:
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/* the sound chip is sending data */
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break;
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case 0x10:
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/* the sound chip is recieving data */
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if (snd_select != 14) {
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snd_regs[snd_select] = via_ora;
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e8910_write(snd_select, via_ora);
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}
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break;
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case 0x18:
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/* the sound chip is latching an address */
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if ((via_ora & 0xf0) == 0x00) {
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snd_select = via_ora & 0x0f;
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}
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break;
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}
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}
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/* update the various analog values when orb is written. */
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static einline void alg_update (void)
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{
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switch (via_orb & 0x06) {
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case 0x00:
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alg_jsh = alg_jch0;
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if ((via_orb & 0x01) == 0x00) {
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/* demultiplexor is on */
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alg_ysh = alg_xsh;
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}
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break;
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case 0x02:
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alg_jsh = alg_jch1;
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if ((via_orb & 0x01) == 0x00) {
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/* demultiplexor is on */
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alg_rsh = alg_xsh;
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}
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break;
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case 0x04:
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alg_jsh = alg_jch2;
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if ((via_orb & 0x01) == 0x00) {
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/* demultiplexor is on */
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if (alg_xsh > 0x80) {
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alg_zsh = alg_xsh - 0x80;
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} else {
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alg_zsh = 0;
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}
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}
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break;
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case 0x06:
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/* sound output line */
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alg_jsh = alg_jch3;
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break;
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}
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/* compare the current joystick direction with a reference */
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if (alg_jsh > alg_xsh) {
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alg_compare = 0x20;
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} else {
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alg_compare = 0;
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}
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/* compute the new "deltas" */
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alg_dx = (long) alg_xsh - (long) alg_rsh;
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alg_dy = (long) alg_rsh - (long) alg_ysh;
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}
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/* update IRQ and bit-7 of the ifr register after making an adjustment to
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* ifr.
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*/
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static einline void int_update (void)
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{
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if ((via_ifr & 0x7f) & (via_ier & 0x7f)) {
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via_ifr |= 0x80;
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} else {
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via_ifr &= 0x7f;
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}
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}
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unsigned char read8 (unsigned address)
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{
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unsigned char data;
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if ((address & 0xe000) == 0xe000) {
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/* rom */
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data = rom[address & 0x1fff];
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} else if ((address & 0xe000) == 0xc000) {
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if (address & 0x800) {
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/* ram */
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data = ram[address & 0x3ff];
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} else if (address & 0x1000) {
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/* io */
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switch (address & 0xf) {
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case 0x0:
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/* compare signal is an input so the value does not come from
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* via_orb.
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*/
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if (via_acr & 0x80) {
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/* timer 1 has control of bit 7 */
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data = (unsigned char) ((via_orb & 0x5f) | via_t1pb7 | alg_compare);
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} else {
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/* bit 7 is being driven by via_orb */
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data = (unsigned char) ((via_orb & 0xdf) | alg_compare);
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}
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break;
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case 0x1:
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/* register 1 also performs handshakes if necessary */
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if ((via_pcr & 0x0e) == 0x08) {
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/* if ca2 is in pulse mode or handshake mode, then it
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* goes low whenever ira is read.
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*/
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via_ca2 = 0;
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}
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/* fall through */
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case 0xf:
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if ((via_orb & 0x18) == 0x08) {
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/* the snd chip is driving port a */
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data = (unsigned char) snd_regs[snd_select];
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} else {
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data = (unsigned char) via_ora;
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}
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break;
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case 0x2:
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data = (unsigned char) via_ddrb;
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break;
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case 0x3:
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data = (unsigned char) via_ddra;
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break;
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case 0x4:
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/* T1 low order counter */
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data = (unsigned char) via_t1c;
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via_ifr &= 0xbf; /* remove timer 1 interrupt flag */
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via_t1on = 0; /* timer 1 is stopped */
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via_t1int = 0;
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via_t1pb7 = 0x80;
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int_update ();
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break;
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case 0x5:
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/* T1 high order counter */
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data = (unsigned char) (via_t1c >> 8);
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break;
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case 0x6:
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/* T1 low order latch */
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data = (unsigned char) via_t1ll;
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break;
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case 0x7:
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/* T1 high order latch */
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data = (unsigned char) via_t1lh;
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break;
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case 0x8:
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/* T2 low order counter */
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data = (unsigned char) via_t2c;
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via_ifr &= 0xdf; /* remove timer 2 interrupt flag */
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via_t2on = 0; /* timer 2 is stopped */
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via_t2int = 0;
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int_update ();
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break;
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case 0x9:
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/* T2 high order counter */
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data = (unsigned char) (via_t2c >> 8);
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break;
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case 0xa:
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data = (unsigned char) via_sr;
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via_ifr &= 0xfb; /* remove shift register interrupt flag */
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via_srb = 0;
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via_srclk = 1;
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int_update ();
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break;
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case 0xb:
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data = (unsigned char) via_acr;
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break;
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case 0xc:
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data = (unsigned char) via_pcr;
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break;
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case 0xd:
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/* interrupt flag register */
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data = (unsigned char) via_ifr;
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break;
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case 0xe:
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/* interrupt enable register */
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data = (unsigned char) (via_ier | 0x80);
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break;
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}
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}
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} else if (address < 0x8000) {
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/* cartridge */
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data = cart[address];
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} else {
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data = 0xff;
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}
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return data;
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}
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void write8 (unsigned address, unsigned char data)
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{
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if ((address & 0xe000) == 0xe000) {
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/* rom */
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} else if ((address & 0xe000) == 0xc000) {
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/* it is possible for both ram and io to be written at the same! */
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if (address & 0x800) {
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ram[address & 0x3ff] = data;
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}
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if (address & 0x1000) {
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switch (address & 0xf) {
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case 0x0:
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via_orb = data;
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snd_update ();
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alg_update ();
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if ((via_pcr & 0xe0) == 0x80) {
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/* if cb2 is in pulse mode or handshake mode, then it
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* goes low whenever orb is written.
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*/
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via_cb2h = 0;
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}
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break;
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case 0x1:
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/* register 1 also performs handshakes if necessary */
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if ((via_pcr & 0x0e) == 0x08) {
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/* if ca2 is in pulse mode or handshake mode, then it
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* goes low whenever ora is written.
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*/
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via_ca2 = 0;
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}
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/* fall through */
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case 0xf:
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via_ora = data;
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snd_update ();
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/* output of port a feeds directly into the dac which then
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* feeds the x axis sample and hold.
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*/
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alg_xsh = data ^ 0x80;
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alg_update ();
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break;
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case 0x2:
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via_ddrb = data;
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break;
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case 0x3:
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via_ddra = data;
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break;
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case 0x4:
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/* T1 low order counter */
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via_t1ll = data;
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break;
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case 0x5:
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/* T1 high order counter */
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via_t1lh = data;
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via_t1c = (via_t1lh << 8) | via_t1ll;
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via_ifr &= 0xbf; /* remove timer 1 interrupt flag */
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via_t1on = 1; /* timer 1 starts running */
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via_t1int = 1;
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via_t1pb7 = 0;
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int_update ();
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break;
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case 0x6:
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/* T1 low order latch */
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via_t1ll = data;
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break;
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case 0x7:
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/* T1 high order latch */
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via_t1lh = data;
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break;
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case 0x8:
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/* T2 low order latch */
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via_t2ll = data;
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break;
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case 0x9:
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/* T2 high order latch/counter */
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via_t2c = (data << 8) | via_t2ll;
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via_ifr &= 0xdf;
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via_t2on = 1; /* timer 2 starts running */
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via_t2int = 1;
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int_update ();
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break;
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case 0xa:
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via_sr = data;
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via_ifr &= 0xfb; /* remove shift register interrupt flag */
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via_srb = 0;
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via_srclk = 1;
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int_update ();
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break;
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case 0xb:
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via_acr = data;
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break;
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case 0xc:
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via_pcr = data;
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if ((via_pcr & 0x0e) == 0x0c) {
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/* ca2 is outputting low */
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via_ca2 = 0;
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} else {
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/* ca2 is disabled or in pulse mode or is
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* outputting high.
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*/
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via_ca2 = 1;
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}
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if ((via_pcr & 0xe0) == 0xc0) {
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/* cb2 is outputting low */
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via_cb2h = 0;
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} else {
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/* cb2 is disabled or is in pulse mode or is
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* outputting high.
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*/
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via_cb2h = 1;
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}
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break;
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case 0xd:
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/* interrupt flag register */
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via_ifr &= ~(data & 0x7f);
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int_update ();
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break;
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case 0xe:
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/* interrupt enable register */
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if (data & 0x80) {
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via_ier |= data & 0x7f;
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} else {
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via_ier &= ~(data & 0x7f);
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}
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int_update ();
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break;
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}
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}
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} else if (address < 0x8000) {
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/* cartridge */
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}
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}
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void vecx_reset (void)
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{
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unsigned r;
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/* ram */
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for (r = 0; r < 1024; r++) {
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ram[r] = r & 0xff;
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}
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for (r = 0; r < 16; r++) {
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snd_regs[r] = 0;
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e8910_write(r, 0);
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}
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/* input buttons */
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snd_regs[14] = 0xff;
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e8910_write(14, 0xff);
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snd_select = 0;
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via_ora = 0;
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via_orb = 0;
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via_ddra = 0;
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via_ddrb = 0;
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via_t1on = 0;
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via_t1int = 0;
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via_t1c = 0;
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via_t1ll = 0;
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via_t1lh = 0;
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via_t1pb7 = 0x80;
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via_t2on = 0;
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via_t2int = 0;
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via_t2c = 0;
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via_t2ll = 0;
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via_sr = 0;
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via_srb = 8;
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via_src = 0;
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via_srclk = 0;
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via_acr = 0;
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via_pcr = 0;
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via_ifr = 0;
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via_ier = 0;
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via_ca2 = 1;
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via_cb2h = 1;
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via_cb2s = 0;
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alg_rsh = 128;
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alg_xsh = 128;
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alg_ysh = 128;
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alg_zsh = 0;
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alg_jch0 = 128;
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alg_jch1 = 128;
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alg_jch2 = 128;
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alg_jch3 = 128;
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alg_jsh = 128;
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alg_compare = 0; /* check this */
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alg_dx = 0;
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alg_dy = 0;
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alg_curr_x = ALG_MAX_X / 2;
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alg_curr_y = ALG_MAX_Y / 2;
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alg_vectoring = 0;
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vector_draw_cnt = 0;
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vector_erse_cnt = 0;
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vectors_draw = vectors_set;
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vectors_erse = vectors_set + VECTOR_CNT;
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fcycles = FCYCLES_INIT;
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e6809_read8 = read8;
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e6809_write8 = write8;
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e6809_reset ();
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}
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/* perform a single cycle worth of via emulation.
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* via_sstep0 is the first postion of the emulation.
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*/
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static einline void via_sstep0 (void)
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{
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unsigned t2shift;
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if (via_t1on) {
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via_t1c--;
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if ((via_t1c & 0xffff) == 0xffff) {
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/* counter just rolled over */
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if (via_acr & 0x40) {
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/* continuous interrupt mode */
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|
|
via_ifr |= 0x40;
|
|
int_update ();
|
|
via_t1pb7 = 0x80 - via_t1pb7;
|
|
|
|
/* reload counter */
|
|
|
|
via_t1c = (via_t1lh << 8) | via_t1ll;
|
|
} else {
|
|
/* one shot mode */
|
|
|
|
if (via_t1int) {
|
|
via_ifr |= 0x40;
|
|
int_update ();
|
|
via_t1pb7 = 0x80;
|
|
via_t1int = 0;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (via_t2on && (via_acr & 0x20) == 0x00) {
|
|
via_t2c--;
|
|
|
|
if ((via_t2c & 0xffff) == 0xffff) {
|
|
/* one shot mode */
|
|
|
|
if (via_t2int) {
|
|
via_ifr |= 0x20;
|
|
int_update ();
|
|
via_t2int = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* shift counter */
|
|
|
|
via_src--;
|
|
|
|
if ((via_src & 0xff) == 0xff) {
|
|
via_src = via_t2ll;
|
|
|
|
if (via_srclk) {
|
|
t2shift = 1;
|
|
via_srclk = 0;
|
|
} else {
|
|
t2shift = 0;
|
|
via_srclk = 1;
|
|
}
|
|
} else {
|
|
t2shift = 0;
|
|
}
|
|
|
|
if (via_srb < 8) {
|
|
switch (via_acr & 0x1c) {
|
|
case 0x00:
|
|
/* disabled */
|
|
break;
|
|
case 0x04:
|
|
/* shift in under control of t2 */
|
|
|
|
if (t2shift) {
|
|
/* shifting in 0s since cb2 is always an output */
|
|
|
|
via_sr <<= 1;
|
|
via_srb++;
|
|
}
|
|
|
|
break;
|
|
case 0x08:
|
|
/* shift in under system clk control */
|
|
|
|
via_sr <<= 1;
|
|
via_srb++;
|
|
|
|
break;
|
|
case 0x0c:
|
|
/* shift in under cb1 control */
|
|
break;
|
|
case 0x10:
|
|
/* shift out under t2 control (free run) */
|
|
|
|
if (t2shift) {
|
|
via_cb2s = (via_sr >> 7) & 1;
|
|
|
|
via_sr <<= 1;
|
|
via_sr |= via_cb2s;
|
|
}
|
|
|
|
break;
|
|
case 0x14:
|
|
/* shift out under t2 control */
|
|
|
|
if (t2shift) {
|
|
via_cb2s = (via_sr >> 7) & 1;
|
|
|
|
via_sr <<= 1;
|
|
via_sr |= via_cb2s;
|
|
via_srb++;
|
|
}
|
|
|
|
break;
|
|
case 0x18:
|
|
/* shift out under system clock control */
|
|
|
|
via_cb2s = (via_sr >> 7) & 1;
|
|
|
|
via_sr <<= 1;
|
|
via_sr |= via_cb2s;
|
|
via_srb++;
|
|
|
|
break;
|
|
case 0x1c:
|
|
/* shift out under cb1 control */
|
|
break;
|
|
}
|
|
|
|
if (via_srb == 8) {
|
|
via_ifr |= 0x04;
|
|
int_update ();
|
|
}
|
|
}
|
|
}
|
|
|
|
/* perform the second part of the via emulation */
|
|
|
|
static einline void via_sstep1 (void)
|
|
{
|
|
if ((via_pcr & 0x0e) == 0x0a) {
|
|
/* if ca2 is in pulse mode, then make sure
|
|
* it gets restored to '1' after the pulse.
|
|
*/
|
|
|
|
via_ca2 = 1;
|
|
}
|
|
|
|
if ((via_pcr & 0xe0) == 0xa0) {
|
|
/* if cb2 is in pulse mode, then make sure
|
|
* it gets restored to '1' after the pulse.
|
|
*/
|
|
|
|
via_cb2h = 1;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static einline void alg_addline (long xx0, long yy0, long xx1, long yy1, unsigned char color)
|
|
{
|
|
unsigned long key;
|
|
long index;
|
|
|
|
unsigned char x0=(xx0*7)/1024, x1=(xx1*7)/1024, y0=((yy0/128-32)*900)/1024, y1=((yy1/128-32)*900)/1024;
|
|
// long x0=xx0/128, x1=xx1/128, y0=yy0/128, y1=yy1/128;
|
|
|
|
|
|
key = (unsigned long) x0;
|
|
key = key * 31 + (unsigned long) y0;
|
|
key = key * 31 + (unsigned long) x1;
|
|
key = key * 31 + (unsigned long) y1;
|
|
key %= VECTOR_HASH;
|
|
|
|
/* first check if the line to be drawn is in the current draw list.
|
|
* if it is, then it is not added again.
|
|
*/
|
|
|
|
index = vector_hash[key];
|
|
|
|
if (index >= 0 && index < vector_draw_cnt &&
|
|
x0 == vectors_draw[index].x0 &&
|
|
y0 == vectors_draw[index].y0 &&
|
|
x1 == vectors_draw[index].x1 &&
|
|
y1 == vectors_draw[index].y1) {
|
|
vectors_draw[index].color = color;
|
|
|
|
} else {
|
|
/* missed on the draw list, now check if the line to be drawn is in
|
|
* the erase list ... if it is, "invalidate" it on the erase list.
|
|
*/
|
|
|
|
if (index >= 0 && index < vector_erse_cnt &&
|
|
x0 == vectors_erse[index].x0 &&
|
|
y0 == vectors_erse[index].y0 &&
|
|
x1 == vectors_erse[index].x1 &&
|
|
y1 == vectors_erse[index].y1) {
|
|
vectors_erse[index].color = VECTREX_COLORS;
|
|
}
|
|
|
|
vectors_draw[vector_draw_cnt].x0 = x0;
|
|
vectors_draw[vector_draw_cnt].y0 = y0;
|
|
vectors_draw[vector_draw_cnt].x1 = x1;
|
|
vectors_draw[vector_draw_cnt].y1 = y1;
|
|
vectors_draw[vector_draw_cnt].color = color;
|
|
vector_hash[key] = vector_draw_cnt;
|
|
vector_draw_cnt++;
|
|
}
|
|
}
|
|
|
|
/* perform a single cycle worth of analog emulation */
|
|
|
|
static einline void alg_sstep (void)
|
|
{
|
|
long sig_dx, sig_dy;
|
|
unsigned sig_ramp;
|
|
unsigned sig_blank;
|
|
|
|
if ((via_acr & 0x10) == 0x10) {
|
|
sig_blank = via_cb2s;
|
|
} else {
|
|
sig_blank = via_cb2h;
|
|
}
|
|
|
|
if (via_ca2 == 0) {
|
|
/* need to force the current point to the 'orgin' so just
|
|
* calculate distance to origin and use that as dx,dy.
|
|
*/
|
|
|
|
sig_dx = ALG_MAX_X / 2 - alg_curr_x;
|
|
sig_dy = ALG_MAX_Y / 2 - alg_curr_y;
|
|
} else {
|
|
if (via_acr & 0x80) {
|
|
sig_ramp = via_t1pb7;
|
|
} else {
|
|
sig_ramp = via_orb & 0x80;
|
|
}
|
|
|
|
if (sig_ramp == 0) {
|
|
sig_dx = alg_dx;
|
|
sig_dy = alg_dy;
|
|
} else {
|
|
sig_dx = 0;
|
|
sig_dy = 0;
|
|
}
|
|
}
|
|
|
|
if (alg_vectoring == 0) {
|
|
if (sig_blank == 1 &&
|
|
alg_curr_x >= 0 && alg_curr_x < ALG_MAX_X &&
|
|
alg_curr_y >= 0 && alg_curr_y < ALG_MAX_Y) {
|
|
|
|
/* start a new vector */
|
|
|
|
alg_vectoring = 1;
|
|
alg_vector_x0 = alg_curr_x;
|
|
alg_vector_y0 = alg_curr_y;
|
|
alg_vector_x1 = alg_curr_x;
|
|
alg_vector_y1 = alg_curr_y;
|
|
alg_vector_dx = sig_dx;
|
|
alg_vector_dy = sig_dy;
|
|
alg_vector_color = (unsigned char) alg_zsh;
|
|
}
|
|
} else {
|
|
/* already drawing a vector ... check if we need to turn it off */
|
|
|
|
if (sig_blank == 0) {
|
|
/* blank just went on, vectoring turns off, and we've got a
|
|
* new line.
|
|
*/
|
|
|
|
alg_vectoring = 0;
|
|
|
|
alg_addline (alg_vector_x0, alg_vector_y0,
|
|
alg_vector_x1, alg_vector_y1,
|
|
alg_vector_color);
|
|
} else if (sig_dx != alg_vector_dx ||
|
|
sig_dy != alg_vector_dy ||
|
|
(unsigned char) alg_zsh != alg_vector_color) {
|
|
|
|
/* the parameters of the vectoring processing has changed.
|
|
* so end the current line.
|
|
*/
|
|
|
|
alg_addline (alg_vector_x0, alg_vector_y0,
|
|
alg_vector_x1, alg_vector_y1,
|
|
alg_vector_color);
|
|
|
|
/* we continue vectoring with a new set of parameters if the
|
|
* current point is not out of limits.
|
|
*/
|
|
|
|
if (alg_curr_x >= 0 && alg_curr_x < ALG_MAX_X &&
|
|
alg_curr_y >= 0 && alg_curr_y < ALG_MAX_Y) {
|
|
alg_vector_x0 = alg_curr_x;
|
|
alg_vector_y0 = alg_curr_y;
|
|
alg_vector_x1 = alg_curr_x;
|
|
alg_vector_y1 = alg_curr_y;
|
|
alg_vector_dx = sig_dx;
|
|
alg_vector_dy = sig_dy;
|
|
alg_vector_color = (unsigned char) alg_zsh;
|
|
} else {
|
|
alg_vectoring = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
alg_curr_x += sig_dx;
|
|
alg_curr_y += sig_dy;
|
|
|
|
if (alg_vectoring == 1 &&
|
|
alg_curr_x >= 0 && alg_curr_x < ALG_MAX_X &&
|
|
alg_curr_y >= 0 && alg_curr_y < ALG_MAX_Y) {
|
|
|
|
/* we're vectoring ... current point is still within limits so
|
|
* extend the current vector.
|
|
*/
|
|
|
|
alg_vector_x1 = alg_curr_x;
|
|
alg_vector_y1 = alg_curr_y;
|
|
}
|
|
}
|
|
|
|
void vecx_emu (long cycles)
|
|
{
|
|
unsigned c, icycles;
|
|
|
|
while (cycles > 0) {
|
|
icycles = e6809_sstep (via_ifr & 0x80, 0);
|
|
|
|
for (c = 0; c < icycles; c++) {
|
|
via_sstep0 ();
|
|
alg_sstep ();
|
|
via_sstep1 ();
|
|
}
|
|
|
|
cycles -= (long) icycles;
|
|
|
|
fcycles -= (long) icycles;
|
|
|
|
if (fcycles < 0) {
|
|
vector_t *tmp;
|
|
|
|
fcycles += FCYCLES_INIT;
|
|
osint_render ();
|
|
|
|
/* everything that was drawn during this pass now now enters
|
|
* the erase list for the next pass.
|
|
*/
|
|
|
|
vector_erse_cnt = vector_draw_cnt;
|
|
vector_draw_cnt = 0;
|
|
|
|
tmp = vectors_erse;
|
|
vectors_erse = vectors_draw;
|
|
vectors_draw = tmp;
|
|
}
|
|
}
|
|
}
|