kopia lustrzana https://github.com/Jean-MarcHarvengt/MCUME
extra emus for ESP32
jean-marcharvengt
rodzic
97dc933616
commit
f02bef6fac
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#
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# This is a project Makefile. It is assumed the directory this Makefile resides in is a
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# project subdirectory.
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#
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PROJECT_NAME := esp8086
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include $(IDF_PATH)/make/project.mk
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Plik binarny nie jest wyświetlany.
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#
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# Main component makefile.
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#
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# This Makefile can be left empty. By default, it will take the sources in the
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# src/ directory, compile them and link them into lib(subdirectory_name).a
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# in the build directory. This behaviour is entirely configurable,
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# please read the ESP-IDF documents if you need to do this.
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#
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COMPONENT_ADD_INCLUDEDIRS := .
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COMPONENT_SRCDIRS := .
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp32-hal-dac.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "rom/ets_sys.h"
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#include "esp_attr.h"
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#include "esp_intr.h"
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#include "soc/rtc_io_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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#include "esp32-hal-gpio.h"
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void IRAM_ATTR __dacWrite(uint8_t pin, uint8_t value)
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{
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if(pin < 25 || pin > 26){
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return;//not dac pin
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}
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pinMode(pin, ANALOG);
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uint8_t channel = pin - 25;
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//Disable Tone
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CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL1_REG, SENS_SW_TONE_EN);
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if (channel) {
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//Disable Channel Tone
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CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN2_M);
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//Set the Dac value
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SET_PERI_REG_BITS(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_DAC, value, RTC_IO_PDAC2_DAC_S); //dac_output
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//Channel output enable
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SET_PERI_REG_MASK(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_XPD_DAC | RTC_IO_PDAC2_DAC_XPD_FORCE);
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} else {
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//Disable Channel Tone
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CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN1_M);
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//Set the Dac value
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SET_PERI_REG_BITS(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_DAC, value, RTC_IO_PDAC1_DAC_S); //dac_output
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//Channel output enable
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SET_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_XPD_DAC | RTC_IO_PDAC1_DAC_XPD_FORCE);
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}
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}
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extern void dacWrite(uint8_t pin, uint8_t value) __attribute__ ((weak, alias("__dacWrite")));
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/*
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Arduino.h - Main include file for the Arduino SDK
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Copyright (c) 2005-2013 Arduino Team. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef MAIN_ESP32_HAL_DAC_H_
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#define MAIN_ESP32_HAL_DAC_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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//#include "esp32-hal.h"
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#include "driver/gpio.h"
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void dacWrite(uint8_t pin, uint8_t value);
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#ifdef __cplusplus
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}
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#endif
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#endif /* MAIN_ESP32_HAL_DAC_H_ */
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp32-hal-timer.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/xtensa_api.h"
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#include "freertos/task.h"
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#include "rom/ets_sys.h"
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#include "soc/timer_group_struct.h"
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#include "soc/dport_reg.h"
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#include "esp_attr.h"
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#include "esp_intr.h"
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#define HWTIMER_LOCK() portENTER_CRITICAL(timer->lock)
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#define HWTIMER_UNLOCK() portEXIT_CRITICAL(timer->lock)
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typedef struct {
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union {
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struct {
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uint32_t reserved0: 10;
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uint32_t alarm_en: 1; /*When set alarm is enabled*/
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uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/
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uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/
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uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/
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uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/
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uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/
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uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/
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};
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uint32_t val;
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} config;
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uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
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uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/
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uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
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uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
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uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
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uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
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uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/
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uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/
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} hw_timer_reg_t;
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typedef struct hw_timer_s {
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hw_timer_reg_t * dev;
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uint8_t num;
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uint8_t group;
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uint8_t timer;
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portMUX_TYPE lock;
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} hw_timer_t;
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static hw_timer_t hw_timer[4] = {
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{(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE),0,0,0,portMUX_INITIALIZER_UNLOCKED},
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{(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x0024),1,0,1,portMUX_INITIALIZER_UNLOCKED},
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{(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1000),2,1,0,portMUX_INITIALIZER_UNLOCKED},
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{(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1024),3,1,1,portMUX_INITIALIZER_UNLOCKED}
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};
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typedef void (*voidFuncPtr)(void);
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static voidFuncPtr __timerInterruptHandlers[4] = {0,0,0,0};
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void IRAM_ATTR __timerISR(void * arg){
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uint32_t s0 = TIMERG0.int_st_timers.val;
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uint32_t s1 = TIMERG1.int_st_timers.val;
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TIMERG0.int_clr_timers.val = s0;
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TIMERG1.int_clr_timers.val = s1;
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uint8_t status = (s1 & 3) << 2 | (s0 & 3);
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uint8_t i = 4;
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//restart the timers that should autoreload
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while(i--){
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hw_timer_reg_t * dev = hw_timer[i].dev;
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if((status & (1 << i)) && dev->config.autoreload){
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dev->config.alarm_en = 1;
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}
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}
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i = 4;
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//call callbacks
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while(i--){
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if(__timerInterruptHandlers[i] && status & (1 << i)){
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__timerInterruptHandlers[i]();
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}
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}
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}
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uint64_t timerRead(hw_timer_t *timer){
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timer->dev->update = 1;
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uint64_t h = timer->dev->cnt_high;
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uint64_t l = timer->dev->cnt_low;
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return (h << 32) | l;
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}
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uint64_t timerAlarmRead(hw_timer_t *timer){
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uint64_t h = timer->dev->alarm_high;
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uint64_t l = timer->dev->alarm_low;
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return (h << 32) | l;
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}
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void timerWrite(hw_timer_t *timer, uint64_t val){
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timer->dev->load_high = (uint32_t) (val >> 32);
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timer->dev->load_low = (uint32_t) (val);
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timer->dev->reload = 1;
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}
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void timerAlarmWrite(hw_timer_t *timer, uint64_t alarm_value, bool autoreload){
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timer->dev->alarm_high = (uint32_t) (alarm_value >> 32);
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timer->dev->alarm_low = (uint32_t) alarm_value;
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timer->dev->config.autoreload = autoreload;
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}
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void timerSetConfig(hw_timer_t *timer, uint32_t config){
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timer->dev->config.val = config;
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}
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uint32_t timerGetConfig(hw_timer_t *timer){
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return timer->dev->config.val;
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}
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void timerSetCountUp(hw_timer_t *timer, bool countUp){
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timer->dev->config.increase = countUp;
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}
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bool timerGetCountUp(hw_timer_t *timer){
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return timer->dev->config.increase;
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}
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void timerSetAutoReload(hw_timer_t *timer, bool autoreload){
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timer->dev->config.autoreload = autoreload;
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}
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bool timerGetAutoReload(hw_timer_t *timer){
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return timer->dev->config.autoreload;
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}
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void timerSetDivider(hw_timer_t *timer, uint16_t divider){//2 to 65536
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if(!divider){
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divider = 0xFFFF;
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} else if(divider == 1){
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divider = 2;
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}
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int timer_en = timer->dev->config.enable;
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timer->dev->config.enable = 0;
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timer->dev->config.divider = divider;
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timer->dev->config.enable = timer_en;
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}
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uint16_t timerGetDivider(hw_timer_t *timer){
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return timer->dev->config.divider;
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}
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void timerStart(hw_timer_t *timer){
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timer->dev->config.enable = 1;
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}
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void timerStop(hw_timer_t *timer){
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timer->dev->config.enable = 0;
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}
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void timerRestart(hw_timer_t *timer){
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timer->dev->config.enable = 0;
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timer->dev->config.enable = 1;
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}
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bool timerStarted(hw_timer_t *timer){
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return timer->dev->config.enable;
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}
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void timerAlarmEnable(hw_timer_t *timer){
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timer->dev->config.alarm_en = 1;
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}
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void timerAlarmDisable(hw_timer_t *timer){
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timer->dev->config.alarm_en = 0;
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}
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bool timerAlarmEnabled(hw_timer_t *timer){
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return timer->dev->config.alarm_en;
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}
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hw_timer_t * timerBegin(uint8_t num, uint16_t divider, bool countUp){
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if(num > 3){
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return NULL;
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}
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hw_timer_t * timer = &hw_timer[num];
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if(timer->group) {
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST);
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TIMERG1.int_ena.val &= ~BIT(timer->timer);
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} else {
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST);
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TIMERG0.int_ena.val &= ~BIT(timer->timer);
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}
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timer->dev->config.enable = 0;
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timerSetDivider(timer, divider);
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timerSetCountUp(timer, countUp);
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timerSetAutoReload(timer, false);
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timerAttachInterrupt(timer, NULL, false);
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timerWrite(timer, 0);
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timer->dev->config.enable = 1;
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return timer;
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}
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void timerEnd(hw_timer_t *timer){
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timer->dev->config.enable = 0;
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timerAttachInterrupt(timer, NULL, false);
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}
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void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge){
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static bool initialized = false;
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static intr_handle_t intr_handle = NULL;
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if(intr_handle){
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esp_intr_disable(intr_handle);
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}
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if(fn == NULL){
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timer->dev->config.level_int_en = 0;
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timer->dev->config.edge_int_en = 0;
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timer->dev->config.alarm_en = 0;
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if(timer->num & 2){
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TIMERG1.int_ena.val &= ~BIT(timer->timer);
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} else {
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TIMERG0.int_ena.val &= ~BIT(timer->timer);
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}
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__timerInterruptHandlers[timer->num] = NULL;
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} else {
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__timerInterruptHandlers[timer->num] = fn;
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timer->dev->config.level_int_en = edge?0:1;//When set, an alarm will generate a level type interrupt.
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timer->dev->config.edge_int_en = edge?1:0;//When set, an alarm will generate an edge type interrupt.
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int intr_source = 0;
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if(!edge){
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if(timer->group){
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intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer->timer;
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} else {
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intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer->timer;
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}
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} else {
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if(timer->group){
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intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer->timer;
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} else {
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intr_source = ETS_TG0_T0_EDGE_INTR_SOURCE + timer->timer;
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}
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}
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if(!initialized){
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initialized = true;
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esp_intr_alloc(intr_source, (int)(ESP_INTR_FLAG_IRAM|ESP_INTR_FLAG_LOWMED|ESP_INTR_FLAG_EDGE), __timerISR, NULL, &intr_handle);
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} else {
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intr_matrix_set(esp_intr_get_cpu(intr_handle), intr_source, esp_intr_get_intno(intr_handle));
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}
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if(timer->group){
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TIMERG1.int_ena.val |= BIT(timer->timer);
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} else {
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TIMERG0.int_ena.val |= BIT(timer->timer);
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}
|
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}
|
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if(intr_handle){
|
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esp_intr_enable(intr_handle);
|
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}
|
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}
|
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|
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void timerDetachInterrupt(hw_timer_t *timer){
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timerAttachInterrupt(timer, NULL, false);
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}
|
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|
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uint64_t timerReadMicros(hw_timer_t *timer){
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uint64_t timer_val = timerRead(timer);
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uint16_t div = timerGetDivider(timer);
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return timer_val * div / 80;
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}
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|
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double timerReadSeconds(hw_timer_t *timer){
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uint64_t timer_val = timerRead(timer);
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uint16_t div = timerGetDivider(timer);
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return (double)timer_val * div / 80000000;
|
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}
|
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|
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uint64_t timerAlarmReadMicros(hw_timer_t *timer){
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uint64_t timer_val = timerAlarmRead(timer);
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uint16_t div = timerGetDivider(timer);
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return timer_val * div / 80;
|
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}
|
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|
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double timerAlarmReadSeconds(hw_timer_t *timer){
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uint64_t timer_val = timerAlarmRead(timer);
|
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uint16_t div = timerGetDivider(timer);
|
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return (double)timer_val * div / 80000000;
|
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}
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
Arduino.h - Main include file for the Arduino SDK
|
||||
Copyright (c) 2005-2013 Arduino Team. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef MAIN_ESP32_HAL_TIMER_H_
|
||||
#define MAIN_ESP32_HAL_TIMER_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//#include "esp32-hal.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
|
||||
struct hw_timer_s;
|
||||
typedef struct hw_timer_s hw_timer_t;
|
||||
|
||||
hw_timer_t * timerBegin(uint8_t timer, uint16_t divider, bool countUp);
|
||||
void timerEnd(hw_timer_t *timer);
|
||||
|
||||
void timerSetConfig(hw_timer_t *timer, uint32_t config);
|
||||
uint32_t timerGetConfig(hw_timer_t *timer);
|
||||
|
||||
void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge);
|
||||
void timerDetachInterrupt(hw_timer_t *timer);
|
||||
|
||||
void timerStart(hw_timer_t *timer);
|
||||
void timerStop(hw_timer_t *timer);
|
||||
void timerRestart(hw_timer_t *timer);
|
||||
void timerWrite(hw_timer_t *timer, uint64_t val);
|
||||
void timerSetDivider(hw_timer_t *timer, uint16_t divider);
|
||||
void timerSetCountUp(hw_timer_t *timer, bool countUp);
|
||||
void timerSetAutoReload(hw_timer_t *timer, bool autoreload);
|
||||
|
||||
bool timerStarted(hw_timer_t *timer);
|
||||
uint64_t timerRead(hw_timer_t *timer);
|
||||
uint64_t timerReadMicros(hw_timer_t *timer);
|
||||
double timerReadSeconds(hw_timer_t *timer);
|
||||
uint16_t timerGetDivider(hw_timer_t *timer);
|
||||
bool timerGetCountUp(hw_timer_t *timer);
|
||||
bool timerGetAutoReload(hw_timer_t *timer);
|
||||
|
||||
void timerAlarmEnable(hw_timer_t *timer);
|
||||
void timerAlarmDisable(hw_timer_t *timer);
|
||||
void timerAlarmWrite(hw_timer_t *timer, uint64_t interruptAt, bool autoreload);
|
||||
|
||||
bool timerAlarmEnabled(hw_timer_t *timer);
|
||||
uint64_t timerAlarmRead(hw_timer_t *timer);
|
||||
uint64_t timerAlarmReadMicros(hw_timer_t *timer);
|
||||
double timerAlarmReadSeconds(hw_timer_t *timer);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* MAIN_ESP32_HAL_TIMER_H_ */
|
||||
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,368 @@
|
|||
/*
|
||||
TwoWire.cpp - TWI/I2C library for Arduino & Wiring
|
||||
Copyright (c) 2006 Nicholas Zambetti. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts
|
||||
Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support
|
||||
Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support
|
||||
Modified Nov 2017 by Chuck Todd (ctodd@cableone.net) - ESP32 ISR Support
|
||||
*/
|
||||
|
||||
extern "C" {
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <inttypes.h>
|
||||
}
|
||||
|
||||
#include "esp32-hal-i2c.h"
|
||||
#include "Wire.h"
|
||||
//#include "Arduino.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
TwoWire::TwoWire(uint8_t bus_num)
|
||||
:num(bus_num & 1)
|
||||
,sda(-1)
|
||||
,scl(-1)
|
||||
,i2c(NULL)
|
||||
,rxIndex(0)
|
||||
,rxLength(0)
|
||||
,rxQueued(0)
|
||||
,txIndex(0)
|
||||
,txLength(0)
|
||||
,txAddress(0)
|
||||
,txQueued(0)
|
||||
,transmitting(0)
|
||||
,last_error(I2C_ERROR_OK)
|
||||
,_timeOutMillis(50)
|
||||
{}
|
||||
|
||||
TwoWire::~TwoWire()
|
||||
{
|
||||
flush();
|
||||
if(i2c) {
|
||||
i2cRelease(i2c);
|
||||
i2c=NULL;
|
||||
}
|
||||
}
|
||||
|
||||
bool TwoWire::begin(int sdaPin, int sclPin, uint32_t frequency)
|
||||
{
|
||||
if(sdaPin < 0) { // default param passed
|
||||
if(num == 0) {
|
||||
if(sda==-1) {
|
||||
sdaPin = SDA; //use Default Pin
|
||||
} else {
|
||||
sdaPin = sda; // reuse prior pin
|
||||
}
|
||||
} else {
|
||||
if(sda==-1) {
|
||||
//log_e("no Default SDA Pin for Second Peripheral");
|
||||
return false; //no Default pin for Second Peripheral
|
||||
} else {
|
||||
sdaPin = sda; // reuse prior pin
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(sclPin < 0) { // default param passed
|
||||
if(num == 0) {
|
||||
if(scl == -1) {
|
||||
sclPin = SCL; // use Default pin
|
||||
} else {
|
||||
sclPin = scl; // reuse prior pin
|
||||
}
|
||||
} else {
|
||||
if(scl == -1) {
|
||||
//log_e("no Default SCL Pin for Second Peripheral");
|
||||
return false; //no Default pin for Second Peripheral
|
||||
} else {
|
||||
sclPin = scl; // reuse prior pin
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
sda = sdaPin;
|
||||
scl = sclPin;
|
||||
i2c = i2cInit(num, sdaPin, sclPin, frequency);
|
||||
if(!i2c) {
|
||||
printf("I2C init failed");
|
||||
return false;
|
||||
}
|
||||
|
||||
flush();
|
||||
return true;
|
||||
|
||||
}
|
||||
|
||||
void TwoWire::setTimeOut(uint16_t timeOutMillis)
|
||||
{
|
||||
_timeOutMillis = timeOutMillis;
|
||||
}
|
||||
|
||||
uint16_t TwoWire::getTimeOut()
|
||||
{
|
||||
return _timeOutMillis;
|
||||
}
|
||||
|
||||
void TwoWire::setClock(uint32_t frequency)
|
||||
{
|
||||
i2cSetFrequency(i2c, frequency);
|
||||
}
|
||||
|
||||
size_t TwoWire::getClock()
|
||||
{
|
||||
return i2cGetFrequency(i2c);
|
||||
}
|
||||
|
||||
/* stickBreaker Nov 2017 ISR, and bigblock 64k-1
|
||||
*/
|
||||
i2c_err_t TwoWire::writeTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop)
|
||||
{
|
||||
last_error = i2cWrite(i2c, address, buff, size, sendStop, _timeOutMillis);
|
||||
return last_error;
|
||||
}
|
||||
|
||||
i2c_err_t TwoWire::readTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop, uint32_t *readCount)
|
||||
{
|
||||
last_error = i2cRead(i2c, address, buff, size, sendStop, _timeOutMillis, readCount);
|
||||
return last_error;
|
||||
}
|
||||
|
||||
void TwoWire::beginTransmission(uint16_t address)
|
||||
{
|
||||
transmitting = 1;
|
||||
txAddress = address;
|
||||
txIndex = txQueued; // allow multiple beginTransmission(),write(),endTransmission(false) until endTransmission(true)
|
||||
txLength = txQueued;
|
||||
last_error = I2C_ERROR_OK;
|
||||
}
|
||||
|
||||
/*stickbreaker isr
|
||||
*/
|
||||
uint8_t TwoWire::endTransmission(bool sendStop) // Assumes Wire.beginTransaction(), Wire.write()
|
||||
{
|
||||
if(transmitting == 1) {
|
||||
last_error = writeTransmission(txAddress, &txBuffer[txQueued], txLength - txQueued, sendStop);
|
||||
rxIndex = 0;
|
||||
rxLength = rxQueued;
|
||||
rxQueued = 0;
|
||||
txQueued = 0; // the SendStop=true will restart all Queueing
|
||||
if(last_error == I2C_ERROR_CONTINUE){
|
||||
// txlength is howmany bytes in txbuffer have been use
|
||||
txQueued = txLength;
|
||||
}
|
||||
} else {
|
||||
last_error = I2C_ERROR_NO_BEGIN;
|
||||
flush();
|
||||
}
|
||||
txIndex = 0;
|
||||
txLength = 0;
|
||||
transmitting = 0;
|
||||
return last_error;
|
||||
}
|
||||
|
||||
/* @stickBreaker 11/2017 fix for ReSTART timeout, ISR
|
||||
*/
|
||||
uint8_t TwoWire::requestFrom(uint16_t address, uint8_t size, bool sendStop)
|
||||
{
|
||||
//use internal Wire rxBuffer, multiple requestFrom()'s may be pending, try to share rxBuffer
|
||||
uint32_t cnt = rxQueued; // currently queued reads, next available position in rxBuffer
|
||||
if(cnt < (I2C_BUFFER_LENGTH-1) && (size + cnt) <= I2C_BUFFER_LENGTH) { // any room left in rxBuffer
|
||||
rxQueued += size;
|
||||
} else { // no room to receive more!
|
||||
//log_e("rxBuff overflow %d", cnt + size);
|
||||
cnt = 0;
|
||||
last_error = I2C_ERROR_MEMORY;
|
||||
flush();
|
||||
return cnt;
|
||||
}
|
||||
|
||||
last_error = readTransmission(address, &rxBuffer[cnt], size, sendStop, &cnt);
|
||||
rxIndex = 0;
|
||||
rxLength = rxQueued;
|
||||
rxQueued = 0;
|
||||
txQueued = 0; // the SendStop=true will restart all Queueing
|
||||
if(last_error != I2C_ERROR_OK){
|
||||
cnt = 0;
|
||||
}
|
||||
return cnt;
|
||||
}
|
||||
|
||||
size_t TwoWire::write(uint8_t data)
|
||||
{
|
||||
if(transmitting) {
|
||||
if(txLength >= I2C_BUFFER_LENGTH) {
|
||||
last_error = I2C_ERROR_MEMORY;
|
||||
return 0;
|
||||
}
|
||||
txBuffer[txIndex] = data;
|
||||
++txIndex;
|
||||
txLength = txIndex;
|
||||
return 1;
|
||||
}
|
||||
last_error = I2C_ERROR_NO_BEGIN; // no begin, not transmitting
|
||||
return 0;
|
||||
}
|
||||
|
||||
size_t TwoWire::write(const uint8_t *data, size_t quantity)
|
||||
{
|
||||
for(size_t i = 0; i < quantity; ++i) {
|
||||
if(!write(data[i])) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return quantity;
|
||||
|
||||
}
|
||||
|
||||
int TwoWire::available(void)
|
||||
{
|
||||
int result = rxLength - rxIndex;
|
||||
return result;
|
||||
}
|
||||
|
||||
int TwoWire::read(void)
|
||||
{
|
||||
int value = -1;
|
||||
if(rxIndex < rxLength) {
|
||||
value = rxBuffer[rxIndex];
|
||||
++rxIndex;
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
int TwoWire::peek(void)
|
||||
{
|
||||
int value = -1;
|
||||
if(rxIndex < rxLength) {
|
||||
value = rxBuffer[rxIndex];
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
void TwoWire::flush(void)
|
||||
{
|
||||
rxIndex = 0;
|
||||
rxLength = 0;
|
||||
txIndex = 0;
|
||||
txLength = 0;
|
||||
rxQueued = 0;
|
||||
txQueued = 0;
|
||||
i2cFlush(i2c); // cleanup
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop)
|
||||
{
|
||||
return requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), static_cast<bool>(sendStop));
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity, uint8_t sendStop)
|
||||
{
|
||||
return requestFrom(address, static_cast<size_t>(quantity), static_cast<bool>(sendStop));
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity)
|
||||
{
|
||||
return requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), true);
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity)
|
||||
{
|
||||
return requestFrom(address, static_cast<size_t>(quantity), true);
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(int address, int quantity)
|
||||
{
|
||||
return requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), true);
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop)
|
||||
{
|
||||
return static_cast<uint8_t>(requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), static_cast<bool>(sendStop)));
|
||||
}
|
||||
|
||||
void TwoWire::beginTransmission(int address)
|
||||
{
|
||||
beginTransmission(static_cast<uint16_t>(address));
|
||||
}
|
||||
|
||||
void TwoWire::beginTransmission(uint8_t address)
|
||||
{
|
||||
beginTransmission(static_cast<uint16_t>(address));
|
||||
}
|
||||
|
||||
uint8_t TwoWire::endTransmission(void)
|
||||
{
|
||||
return endTransmission(true);
|
||||
}
|
||||
|
||||
/* stickbreaker Nov2017 better error reporting
|
||||
*/
|
||||
uint8_t TwoWire::lastError()
|
||||
{
|
||||
return (uint8_t)last_error;
|
||||
}
|
||||
|
||||
const char ERRORTEXT[] =
|
||||
"OK\0"
|
||||
"DEVICE\0"
|
||||
"ACK\0"
|
||||
"TIMEOUT\0"
|
||||
"BUS\0"
|
||||
"BUSY\0"
|
||||
"MEMORY\0"
|
||||
"CONTINUE\0"
|
||||
"NO_BEGIN\0"
|
||||
"\0";
|
||||
|
||||
|
||||
char * TwoWire::getErrorText(uint8_t err)
|
||||
{
|
||||
uint8_t t = 0;
|
||||
bool found = false;
|
||||
char * message = (char*)&ERRORTEXT;
|
||||
|
||||
while(!found && message[0]) {
|
||||
found = t == err;
|
||||
if(!found) {
|
||||
message = message + strlen(message) + 1;
|
||||
t++;
|
||||
}
|
||||
}
|
||||
if(!found) {
|
||||
return NULL;
|
||||
} else {
|
||||
return message;
|
||||
}
|
||||
}
|
||||
|
||||
/*stickbreaker Dump i2c Interrupt buffer, i2c isr Debugging
|
||||
*/
|
||||
|
||||
uint32_t TwoWire::setDebugFlags( uint32_t setBits, uint32_t resetBits){
|
||||
return i2cDebug(i2c,setBits,resetBits);
|
||||
}
|
||||
|
||||
bool TwoWire::busy(void){
|
||||
return ((i2cGetStatus(i2c) & 16 )==16);
|
||||
}
|
||||
|
||||
TwoWire Wire = TwoWire(0);
|
||||
TwoWire Wire1 = TwoWire(1);
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
TwoWire.h - TWI/I2C library for Arduino & Wiring
|
||||
Copyright (c) 2006 Nicholas Zambetti. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts
|
||||
Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support
|
||||
Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support
|
||||
Modified November 2017 by Chuck Todd <stickbreaker on GitHub> to use ISR and increase stability.
|
||||
*/
|
||||
|
||||
#ifndef TwoWire_h
|
||||
#define TwoWire_h
|
||||
|
||||
#include "esp32-hal-i2c.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/queue.h"
|
||||
|
||||
|
||||
|
||||
#define SDA (gpio_num_t)4
|
||||
#define SCL (gpio_num_t)5
|
||||
|
||||
|
||||
#define STICKBREAKER V1.0.1
|
||||
#define I2C_BUFFER_LENGTH 128
|
||||
typedef void(*user_onRequest)(void);
|
||||
typedef void(*user_onReceive)(uint8_t*, int);
|
||||
|
||||
class TwoWire
|
||||
{
|
||||
protected:
|
||||
uint8_t num;
|
||||
int8_t sda;
|
||||
int8_t scl;
|
||||
i2c_t * i2c;
|
||||
|
||||
uint8_t rxBuffer[I2C_BUFFER_LENGTH];
|
||||
uint16_t rxIndex;
|
||||
uint16_t rxLength;
|
||||
uint16_t rxQueued; //@stickBreaker
|
||||
|
||||
uint8_t txBuffer[I2C_BUFFER_LENGTH];
|
||||
uint16_t txIndex;
|
||||
uint16_t txLength;
|
||||
uint16_t txAddress;
|
||||
uint16_t txQueued; //@stickbreaker
|
||||
|
||||
uint8_t transmitting;
|
||||
/* slave Mode, not yet Stickbreaker
|
||||
static user_onRequest uReq[2];
|
||||
static user_onReceive uRcv[2];
|
||||
void onRequestService(void);
|
||||
void onReceiveService(uint8_t*, int);
|
||||
*/
|
||||
i2c_err_t last_error; // @stickBreaker from esp32-hal-i2c.h
|
||||
uint16_t _timeOutMillis;
|
||||
|
||||
public:
|
||||
TwoWire(uint8_t bus_num);
|
||||
~TwoWire();
|
||||
bool begin(int sda=-1, int scl=-1, uint32_t frequency=0);
|
||||
|
||||
void setClock(uint32_t frequency); // change bus clock without initing hardware
|
||||
size_t getClock(); // current bus clock rate in hz
|
||||
|
||||
void setTimeOut(uint16_t timeOutMillis);
|
||||
uint16_t getTimeOut();
|
||||
|
||||
uint8_t lastError();
|
||||
char * getErrorText(uint8_t err);
|
||||
|
||||
//@stickBreaker for big blocks and ISR model
|
||||
i2c_err_t writeTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true);
|
||||
i2c_err_t readTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true, uint32_t *readCount=NULL);
|
||||
|
||||
void beginTransmission(uint16_t address);
|
||||
void beginTransmission(uint8_t address);
|
||||
void beginTransmission(int address);
|
||||
|
||||
uint8_t endTransmission(bool sendStop);
|
||||
uint8_t endTransmission(void);
|
||||
|
||||
uint8_t requestFrom(uint16_t address, uint8_t size, bool sendStop);
|
||||
uint8_t requestFrom(uint16_t address, uint8_t size, uint8_t sendStop);
|
||||
uint8_t requestFrom(uint16_t address, uint8_t size);
|
||||
uint8_t requestFrom(uint8_t address, uint8_t size, uint8_t sendStop);
|
||||
uint8_t requestFrom(uint8_t address, uint8_t size);
|
||||
uint8_t requestFrom(int address, int size, int sendStop);
|
||||
uint8_t requestFrom(int address, int size);
|
||||
|
||||
size_t write(uint8_t);
|
||||
size_t write(const uint8_t *, size_t);
|
||||
int available(void);
|
||||
int read(void);
|
||||
int peek(void);
|
||||
void flush(void);
|
||||
|
||||
|
||||
|
||||
void onReceive( void (*)(int) );
|
||||
void onRequest( void (*)(void) );
|
||||
|
||||
uint32_t setDebugFlags( uint32_t setBits, uint32_t resetBits);
|
||||
bool busy();
|
||||
};
|
||||
|
||||
extern TwoWire Wire;
|
||||
extern TwoWire Wire1;
|
||||
|
||||
|
||||
/*
|
||||
V1.0.1 02AUG2018 First Fix after release, Correct ReSTART handling, change Debug control, change begin()
|
||||
to a function, this allow reporting if bus cannot be initialized, Wire.begin() can be used to recover
|
||||
a hung bus busy condition.
|
||||
V0.2.2 13APR2018 preserve custom SCL,SDA,Frequency when no parameters passed to begin()
|
||||
V0.2.1 15MAR2018 Hardware reset, Glitch prevention, adding destructor for second i2c testing
|
||||
*/
|
||||
#endif
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#
|
||||
# Main component makefile.
|
||||
#
|
||||
# This Makefile can be left empty. By default, it will take the sources in the
|
||||
# src/ directory, compile them and link them into lib(subdirectory_name).a
|
||||
# in the build directory. This behaviour is entirely configurable,
|
||||
# please read the ESP-IDF documents if you need to do this.
|
||||
#
|
||||
|
||||
COMPONENT_ADD_INCLUDEDIRS := .
|
||||
COMPONENT_SRCDIRS := .
|
||||
|
|
@ -0,0 +1,309 @@
|
|||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
|
||||
#include "stdint.h"
|
||||
#include "esp32-hal-gpio.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "rom/ets_sys.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_intr.h"
|
||||
#include "rom/gpio.h"
|
||||
#include "soc/gpio_reg.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/gpio_struct.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "esp_system.h"
|
||||
|
||||
#define ESP_REG(addr) *((volatile uint32_t *)(addr))
|
||||
|
||||
const int8_t esp32_adc2gpio[20] = {36, 37, 38, 39, 32, 33, 34, 35, -1, -1, 4, 0, 2, 15, 13, 12, 14, 27, 25, 26};
|
||||
|
||||
const DRAM_ATTR esp32_gpioMux_t esp32_gpioMux[GPIO_PIN_COUNT]={
|
||||
{0x44, 11, 11, 1},
|
||||
{0x88, -1, -1, -1},
|
||||
{0x40, 12, 12, 2},
|
||||
{0x84, -1, -1, -1},
|
||||
{0x48, 10, 10, 0},
|
||||
{0x6c, -1, -1, -1},
|
||||
{0x60, -1, -1, -1},
|
||||
{0x64, -1, -1, -1},
|
||||
{0x68, -1, -1, -1},
|
||||
{0x54, -1, -1, -1},
|
||||
{0x58, -1, -1, -1},
|
||||
{0x5c, -1, -1, -1},
|
||||
{0x34, 15, 15, 5},
|
||||
{0x38, 14, 14, 4},
|
||||
{0x30, 16, 16, 6},
|
||||
{0x3c, 13, 13, 3},
|
||||
{0x4c, -1, -1, -1},
|
||||
{0x50, -1, -1, -1},
|
||||
{0x70, -1, -1, -1},
|
||||
{0x74, -1, -1, -1},
|
||||
{0x78, -1, -1, -1},
|
||||
{0x7c, -1, -1, -1},
|
||||
{0x80, -1, -1, -1},
|
||||
{0x8c, -1, -1, -1},
|
||||
{0, -1, -1, -1},
|
||||
{0x24, 6, 18, -1}, //DAC1
|
||||
{0x28, 7, 19, -1}, //DAC2
|
||||
{0x2c, 17, 17, 7},
|
||||
{0, -1, -1, -1},
|
||||
{0, -1, -1, -1},
|
||||
{0, -1, -1, -1},
|
||||
{0, -1, -1, -1},
|
||||
{0x1c, 9, 4, 9},
|
||||
{0x20, 8, 5, 8},
|
||||
{0x14, 4, 6, -1},
|
||||
{0x18, 5, 7, -1},
|
||||
{0x04, 0, 0, -1},
|
||||
{0x08, 1, 1, -1},
|
||||
{0x0c, 2, 2, -1},
|
||||
{0x10, 3, 3, -1}
|
||||
};
|
||||
|
||||
typedef void (*voidFuncPtr)(void);
|
||||
typedef void (*voidFuncPtrArg)(void*);
|
||||
typedef struct {
|
||||
voidFuncPtr fn;
|
||||
void* arg;
|
||||
bool functional;
|
||||
} InterruptHandle_t;
|
||||
static InterruptHandle_t __pinInterruptHandlers[GPIO_PIN_COUNT] = {0,};
|
||||
|
||||
#include "driver/rtc_io.h"
|
||||
|
||||
extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode)
|
||||
{
|
||||
|
||||
if(!digitalPinIsValid(pin)) {
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t rtc_reg = rtc_gpio_desc[pin].reg;
|
||||
if(mode == ANALOG) {
|
||||
if(!rtc_reg) {
|
||||
return;//not rtc pin
|
||||
}
|
||||
//lock rtc
|
||||
uint32_t reg_val = ESP_REG(rtc_reg);
|
||||
if(reg_val & rtc_gpio_desc[pin].mux){
|
||||
return;//already in adc mode
|
||||
}
|
||||
reg_val &= ~(
|
||||
(RTC_IO_TOUCH_PAD1_FUN_SEL_V << rtc_gpio_desc[pin].func)
|
||||
|rtc_gpio_desc[pin].ie
|
||||
|rtc_gpio_desc[pin].pullup
|
||||
|rtc_gpio_desc[pin].pulldown);
|
||||
ESP_REG(RTC_GPIO_ENABLE_W1TC_REG) = (1 << (rtc_gpio_desc[pin].rtc_num + RTC_GPIO_ENABLE_W1TC_S));
|
||||
ESP_REG(rtc_reg) = reg_val | rtc_gpio_desc[pin].mux;
|
||||
//unlock rtc
|
||||
ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = ((uint32_t)2 << MCU_SEL_S) | ((uint32_t)2 << FUN_DRV_S) | FUN_IE;
|
||||
return;
|
||||
}
|
||||
|
||||
//RTC pins PULL settings
|
||||
if(rtc_reg) {
|
||||
//lock rtc
|
||||
ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].mux);
|
||||
if(mode & PULLUP) {
|
||||
ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pullup) & ~(rtc_gpio_desc[pin].pulldown);
|
||||
} else if(mode & PULLDOWN) {
|
||||
ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pulldown) & ~(rtc_gpio_desc[pin].pullup);
|
||||
} else {
|
||||
ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].pullup | rtc_gpio_desc[pin].pulldown);
|
||||
}
|
||||
//unlock rtc
|
||||
}
|
||||
|
||||
uint32_t pinFunction = 0, pinControl = 0;
|
||||
|
||||
//lock gpio
|
||||
if(mode & INPUT) {
|
||||
if(pin < 32) {
|
||||
GPIO.enable_w1tc = ((uint32_t)1 << pin);
|
||||
} else {
|
||||
GPIO.enable1_w1tc.val = ((uint32_t)1 << (pin - 32));
|
||||
}
|
||||
} else if(mode & OUTPUT) {
|
||||
if(pin > 33){
|
||||
//unlock gpio
|
||||
return;//pins above 33 can be only inputs
|
||||
} else if(pin < 32) {
|
||||
GPIO.enable_w1ts = ((uint32_t)1 << pin);
|
||||
} else {
|
||||
GPIO.enable1_w1ts.val = ((uint32_t)1 << (pin - 32));
|
||||
}
|
||||
}
|
||||
|
||||
if(mode & PULLUP) {
|
||||
pinFunction |= FUN_PU;
|
||||
} else if(mode & PULLDOWN) {
|
||||
pinFunction |= FUN_PD;
|
||||
}
|
||||
|
||||
pinFunction |= ((uint32_t)2 << FUN_DRV_S);//what are the drivers?
|
||||
pinFunction |= FUN_IE;//input enable but required for output as well?
|
||||
|
||||
if(mode & (INPUT | OUTPUT)) {
|
||||
pinFunction |= ((uint32_t)2 << MCU_SEL_S);
|
||||
} else if(mode == SPECIAL) {
|
||||
pinFunction |= ((uint32_t)(((pin)==1||(pin)==3)?0:1) << MCU_SEL_S);
|
||||
} else {
|
||||
pinFunction |= ((uint32_t)(mode >> 5) << MCU_SEL_S);
|
||||
}
|
||||
|
||||
ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = pinFunction;
|
||||
|
||||
if(mode & OPEN_DRAIN) {
|
||||
pinControl = (1 << GPIO_PIN0_PAD_DRIVER_S);
|
||||
}
|
||||
|
||||
GPIO.pin[pin].val = pinControl;
|
||||
//unlock gpio
|
||||
}
|
||||
|
||||
extern void IRAM_ATTR __digitalWrite(uint8_t pin, uint8_t val)
|
||||
{
|
||||
if(val) {
|
||||
if(pin < 32) {
|
||||
GPIO.out_w1ts = ((uint32_t)1 << pin);
|
||||
} else if(pin < 34) {
|
||||
GPIO.out1_w1ts.val = ((uint32_t)1 << (pin - 32));
|
||||
}
|
||||
} else {
|
||||
if(pin < 32) {
|
||||
GPIO.out_w1tc = ((uint32_t)1 << pin);
|
||||
} else if(pin < 34) {
|
||||
GPIO.out1_w1tc.val = ((uint32_t)1 << (pin - 32));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
extern int IRAM_ATTR __digitalRead(uint8_t pin)
|
||||
{
|
||||
if(pin < 32) {
|
||||
return (GPIO.in >> pin) & 0x1;
|
||||
} else if(pin < 40) {
|
||||
return (GPIO.in1.val >> (pin - 32)) & 0x1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static intr_handle_t gpio_intr_handle = NULL;
|
||||
|
||||
static void IRAM_ATTR __onPinInterrupt()
|
||||
{
|
||||
uint32_t gpio_intr_status_l=0;
|
||||
uint32_t gpio_intr_status_h=0;
|
||||
|
||||
gpio_intr_status_l = GPIO.status;
|
||||
gpio_intr_status_h = GPIO.status1.val;
|
||||
GPIO.status_w1tc = gpio_intr_status_l;//Clear intr for gpio0-gpio31
|
||||
GPIO.status1_w1tc.val = gpio_intr_status_h;//Clear intr for gpio32-39
|
||||
|
||||
uint8_t pin=0;
|
||||
if(gpio_intr_status_l) {
|
||||
do {
|
||||
if(gpio_intr_status_l & ((uint32_t)1 << pin)) {
|
||||
if(__pinInterruptHandlers[pin].fn) {
|
||||
if(__pinInterruptHandlers[pin].arg){
|
||||
((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg);
|
||||
} else {
|
||||
__pinInterruptHandlers[pin].fn();
|
||||
}
|
||||
}
|
||||
}
|
||||
} while(++pin<32);
|
||||
}
|
||||
if(gpio_intr_status_h) {
|
||||
pin=32;
|
||||
do {
|
||||
if(gpio_intr_status_h & ((uint32_t)1 << (pin - 32))) {
|
||||
if(__pinInterruptHandlers[pin].fn) {
|
||||
if(__pinInterruptHandlers[pin].arg){
|
||||
((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg);
|
||||
} else {
|
||||
__pinInterruptHandlers[pin].fn();
|
||||
}
|
||||
}
|
||||
}
|
||||
} while(++pin<GPIO_PIN_COUNT);
|
||||
}
|
||||
}
|
||||
|
||||
extern void cleanupFunctional(void* arg);
|
||||
|
||||
extern void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtrArg userFunc, void * arg, int intr_type, bool functional)
|
||||
{
|
||||
static bool interrupt_initialized = false;
|
||||
|
||||
if(!interrupt_initialized) {
|
||||
interrupt_initialized = true;
|
||||
esp_intr_alloc(ETS_GPIO_INTR_SOURCE, (int)ESP_INTR_FLAG_IRAM, __onPinInterrupt, NULL, &gpio_intr_handle);
|
||||
}
|
||||
|
||||
// if new attach without detach remove old info
|
||||
if (__pinInterruptHandlers[pin].functional && __pinInterruptHandlers[pin].arg)
|
||||
{
|
||||
cleanupFunctional(__pinInterruptHandlers[pin].arg);
|
||||
}
|
||||
__pinInterruptHandlers[pin].fn = (voidFuncPtr)userFunc;
|
||||
__pinInterruptHandlers[pin].arg = arg;
|
||||
__pinInterruptHandlers[pin].functional = functional;
|
||||
|
||||
esp_intr_disable(gpio_intr_handle);
|
||||
if(esp_intr_get_cpu(gpio_intr_handle)) { //APP_CPU
|
||||
GPIO.pin[pin].int_ena = 1;
|
||||
} else { //PRO_CPU
|
||||
GPIO.pin[pin].int_ena = 4;
|
||||
}
|
||||
GPIO.pin[pin].int_type = intr_type;
|
||||
esp_intr_enable(gpio_intr_handle);
|
||||
}
|
||||
|
||||
extern void __attachInterruptArg(uint8_t pin, voidFuncPtrArg userFunc, void * arg, int intr_type)
|
||||
{
|
||||
__attachInterruptFunctionalArg(pin, userFunc, arg, intr_type, false);
|
||||
}
|
||||
|
||||
extern void __attachInterrupt(uint8_t pin, voidFuncPtr userFunc, int intr_type) {
|
||||
__attachInterruptFunctionalArg(pin, (voidFuncPtrArg)userFunc, NULL, intr_type, false);
|
||||
}
|
||||
|
||||
extern void __detachInterrupt(uint8_t pin)
|
||||
{
|
||||
esp_intr_disable(gpio_intr_handle);
|
||||
if (__pinInterruptHandlers[pin].functional && __pinInterruptHandlers[pin].arg)
|
||||
{
|
||||
cleanupFunctional(__pinInterruptHandlers[pin].arg);
|
||||
}
|
||||
__pinInterruptHandlers[pin].fn = NULL;
|
||||
__pinInterruptHandlers[pin].arg = NULL;
|
||||
__pinInterruptHandlers[pin].arg = false;
|
||||
|
||||
GPIO.pin[pin].int_ena = 0;
|
||||
GPIO.pin[pin].int_type = 0;
|
||||
esp_intr_enable(gpio_intr_handle);
|
||||
}
|
||||
|
||||
|
||||
extern void pinMode(uint8_t pin, uint8_t mode) __attribute__ ((weak, alias("__pinMode")));
|
||||
extern void digitalWrite(uint8_t pin, uint8_t val) __attribute__ ((weak, alias("__digitalWrite")));
|
||||
extern int digitalRead(uint8_t pin) __attribute__ ((weak, alias("__digitalRead")));
|
||||
extern void attachInterrupt(uint8_t pin, voidFuncPtr handler, int mode) __attribute__ ((weak, alias("__attachInterrupt")));
|
||||
extern void attachInterruptArg(uint8_t pin, voidFuncPtrArg handler, void * arg, int mode) __attribute__ ((weak, alias("__attachInterruptArg")));
|
||||
extern void detachInterrupt(uint8_t pin) __attribute__ ((weak, alias("__detachInterrupt")));
|
||||
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
Arduino.h - Main include file for the Arduino SDK
|
||||
Copyright (c) 2005-2013 Arduino Team. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef MAIN_ESP32_HAL_GPIO_H_
|
||||
#define MAIN_ESP32_HAL_GPIO_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define LOW 0x0
|
||||
#define HIGH 0x1
|
||||
|
||||
//GPIO FUNCTIONS
|
||||
#define INPUT 0x01
|
||||
#define OUTPUT 0x02
|
||||
#define PULLUP 0x04
|
||||
#define INPUT_PULLUP 0x05
|
||||
#define PULLDOWN 0x08
|
||||
#define INPUT_PULLDOWN 0x09
|
||||
#define OPEN_DRAIN 0x10
|
||||
#define OUTPUT_OPEN_DRAIN 0x12
|
||||
#define SPECIAL 0xF0
|
||||
#define FUNCTION_1 0x00
|
||||
#define FUNCTION_2 0x20
|
||||
#define FUNCTION_3 0x40
|
||||
#define FUNCTION_4 0x60
|
||||
#define FUNCTION_5 0x80
|
||||
#define FUNCTION_6 0xA0
|
||||
#define ANALOG 0xC0
|
||||
|
||||
//Interrupt Modes
|
||||
#define DISABLED 0x00
|
||||
#define RISING 0x01
|
||||
#define FALLING 0x02
|
||||
#define CHANGE 0x03
|
||||
#define ONLOW 0x04
|
||||
#define ONHIGH 0x05
|
||||
#define ONLOW_WE 0x0C
|
||||
#define ONHIGH_WE 0x0D
|
||||
|
||||
typedef struct {
|
||||
uint8_t reg; /*!< GPIO register offset from DR_REG_IO_MUX_BASE */
|
||||
int8_t rtc; /*!< RTC GPIO number (-1 if not RTC GPIO pin) */
|
||||
int8_t adc; /*!< ADC Channel number (-1 if not ADC pin) */
|
||||
int8_t touch; /*!< Touch Channel number (-1 if not Touch pin) */
|
||||
} esp32_gpioMux_t;
|
||||
|
||||
extern const esp32_gpioMux_t esp32_gpioMux[40];
|
||||
extern const int8_t esp32_adc2gpio[20];
|
||||
|
||||
#define digitalPinIsValid(pin) ((pin) < 40 && esp32_gpioMux[(pin)].reg)
|
||||
#define digitalPinCanOutput(pin) ((pin) < 34 && esp32_gpioMux[(pin)].reg)
|
||||
#define digitalPinToRtcPin(pin) (((pin) < 40)?esp32_gpioMux[(pin)].rtc:-1)
|
||||
#define digitalPinToAnalogChannel(pin) (((pin) < 40)?esp32_gpioMux[(pin)].adc:-1)
|
||||
#define digitalPinToTouchChannel(pin) (((pin) < 40)?esp32_gpioMux[(pin)].touch:-1)
|
||||
#define digitalPinToDacChannel(pin) (((pin) == 25)?0:((pin) == 26)?1:-1)
|
||||
|
||||
void pinMode(uint8_t pin, uint8_t mode);
|
||||
void digitalWrite(uint8_t pin, uint8_t val);
|
||||
int digitalRead(uint8_t pin);
|
||||
|
||||
void attachInterrupt(uint8_t pin, void (*)(void), int mode);
|
||||
void attachInterruptArg(uint8_t pin, void (*)(void*), void * arg, int mode);
|
||||
void detachInterrupt(uint8_t pin);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* MAIN_ESP32_HAL_GPIO_H_ */
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,82 @@
|
|||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
// modified Nov 2017 by Chuck Todd <StickBreaker> to support Interrupt Driven I/O
|
||||
|
||||
#ifndef _ESP32_HAL_I2C_H_
|
||||
#define _ESP32_HAL_I2C_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/event_groups.h"
|
||||
|
||||
// External Wire.h equivalent error Codes
|
||||
typedef enum {
|
||||
I2C_ERROR_OK=0,
|
||||
I2C_ERROR_DEV,
|
||||
I2C_ERROR_ACK,
|
||||
I2C_ERROR_TIMEOUT,
|
||||
I2C_ERROR_BUS,
|
||||
I2C_ERROR_BUSY,
|
||||
I2C_ERROR_MEMORY,
|
||||
I2C_ERROR_CONTINUE,
|
||||
I2C_ERROR_NO_BEGIN
|
||||
} i2c_err_t;
|
||||
|
||||
struct i2c_struct_t;
|
||||
typedef struct i2c_struct_t i2c_t;
|
||||
|
||||
i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t clk_speed);
|
||||
void i2cRelease(i2c_t *i2c); // free ISR, Free DQ, Power off peripheral clock. Must call i2cInit() to recover
|
||||
i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis);
|
||||
i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount);
|
||||
i2c_err_t i2cFlush(i2c_t *i2c);
|
||||
i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed);
|
||||
uint32_t i2cGetFrequency(i2c_t * i2c);
|
||||
uint32_t i2cGetStatus(i2c_t * i2c); // Status register of peripheral
|
||||
|
||||
//Functions below should be used only if well understood
|
||||
//Might be deprecated and removed in future
|
||||
i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl);
|
||||
i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl);
|
||||
i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda);
|
||||
i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda);
|
||||
|
||||
//Stickbreakers ISR Support
|
||||
i2c_err_t i2cProcQueue(i2c_t *i2c, uint32_t *readCount, uint16_t timeOutMillis);
|
||||
i2c_err_t i2cAddQueueWrite(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event);
|
||||
i2c_err_t i2cAddQueueRead(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event);
|
||||
|
||||
//stickbreaker debug support
|
||||
uint32_t i2cDebug(i2c_t *, uint32_t setBits, uint32_t resetBits);
|
||||
// Debug actions have 3 currently defined locus
|
||||
// 0xXX------ : at entry of ProcQueue
|
||||
// 0x--XX---- : at exit of ProcQueue
|
||||
// 0x------XX : at entry of Flush
|
||||
//
|
||||
// bit 0 causes DumpI2c to execute
|
||||
// bit 1 causes DumpInts to execute
|
||||
// bit 2 causes DumpCmdqueue to execute
|
||||
// bit 3 causes DumpStatus to execute
|
||||
// bit 4 causes DumpFifo to execute
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ESP32_HAL_I2C_H_ */
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp32-hal-matrix.h"
|
||||
#include "esp_attr.h"
|
||||
#include "rom/gpio.h"
|
||||
|
||||
|
||||
|
||||
#define MATRIX_DETACH_OUT_SIG 0x100
|
||||
#define MATRIX_DETACH_IN_LOW_PIN 0x30
|
||||
#define MATRIX_DETACH_IN_LOW_HIGH 0x38
|
||||
|
||||
void IRAM_ATTR pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable)
|
||||
{
|
||||
gpio_matrix_out(pin, function, invertOut, invertEnable);
|
||||
}
|
||||
|
||||
void IRAM_ATTR pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable)
|
||||
{
|
||||
gpio_matrix_out(pin, MATRIX_DETACH_OUT_SIG, invertOut, invertEnable);
|
||||
}
|
||||
|
||||
void IRAM_ATTR pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted)
|
||||
{
|
||||
gpio_matrix_in(pin, signal, inverted);
|
||||
}
|
||||
|
||||
void IRAM_ATTR pinMatrixInDetach(uint8_t signal, bool high, bool inverted)
|
||||
{
|
||||
gpio_matrix_in(high?MATRIX_DETACH_IN_LOW_HIGH:MATRIX_DETACH_IN_LOW_PIN, signal, inverted);
|
||||
}
|
||||
/*
|
||||
void IRAM_ATTR intrMatrixAttach(uint32_t source, uint32_t inum){
|
||||
intr_matrix_set(PRO_CPU_NUM, source, inum);
|
||||
}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _ESP32_HAL_MATRIX_H_
|
||||
#define _ESP32_HAL_MATRIX_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//#include "esp32-hal.h"
|
||||
//#include "soc/gpio_sig_map.h"
|
||||
|
||||
void pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable);
|
||||
void pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable);
|
||||
void pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted);
|
||||
void pinMatrixInDetach(uint8_t signal, bool high, bool inverted);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* COMPONENTS_ARDUHAL_INCLUDE_ESP32_HAL_MATRIX_H_ */
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#!/bin/bash
|
||||
. ${IDF_PATH}/add_path.sh
|
||||
esptool.py --chip esp32 --port "/dev/cu.SLAB_USBtoUART" --baud $((230400*4)) write_flash -fs 4MB 0x10000 ../esp8086/build/esp8086.bin
|
||||
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,290 @@
|
|||
extern "C" {
|
||||
#include "emuapi.h"
|
||||
}
|
||||
|
||||
#ifdef HAS_SND
|
||||
#include "AudioPlaySystem.h"
|
||||
#include "esp_system.h"
|
||||
|
||||
#define USE_I2S 1
|
||||
|
||||
#ifdef USE_I2S
|
||||
#include "esp_event.h"
|
||||
#include "driver/i2s.h"
|
||||
#include "freertos/queue.h"
|
||||
#include "string.h"
|
||||
#define I2S_NUM ((i2s_port_t)0)
|
||||
//static QueueHandle_t queue;
|
||||
#else
|
||||
#include "esp32-hal-timer.h"
|
||||
#include "esp32-hal-dac.h"
|
||||
static int32_t LastPlayPos=0;
|
||||
volatile int32_t NextPlayPos=0;
|
||||
volatile uint8_t DacPin;
|
||||
uint16_t LastDacValue;
|
||||
hw_timer_t * timer = NULL;
|
||||
#endif
|
||||
|
||||
volatile uint16_t *Buffer;
|
||||
volatile uint16_t BufferSize;
|
||||
|
||||
|
||||
static const short square[]={
|
||||
32767,32767,32767,32767,
|
||||
32767,32767,32767,32767,
|
||||
32767,32767,32767,32767,
|
||||
32767,32767,32767,32767,
|
||||
32767,32767,32767,32767,
|
||||
32767,32767,32767,32767,
|
||||
32767,32767,32767,32767,
|
||||
32767,32767,32767,32767,
|
||||
-32767,-32767,-32767,-32767,
|
||||
-32767,-32767,-32767,-32767,
|
||||
-32767,-32767,-32767,-32767,
|
||||
-32767,-32767,-32767,-32767,
|
||||
-32767,-32767,-32767,-32767,
|
||||
-32767,-32767,-32767,-32767,
|
||||
-32767,-32767,-32767,-32767,
|
||||
-32767,-32767,-32767,-32767,
|
||||
};
|
||||
|
||||
const short noise[] {
|
||||
-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,
|
||||
-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,32767,-32767,
|
||||
-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,
|
||||
-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767,
|
||||
-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767,
|
||||
-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767,
|
||||
32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767,
|
||||
32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,
|
||||
32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,
|
||||
32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,-32767,-32767,
|
||||
32767,-32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,
|
||||
32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767,-32767,
|
||||
32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,
|
||||
32767,-32767,32767,-32767,-32767,32767,32767,-32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767,
|
||||
32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,
|
||||
32767,-32767,32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767,
|
||||
};
|
||||
|
||||
#define NOISEBSIZE 0x100
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int spos;
|
||||
unsigned int sinc;
|
||||
unsigned int vol;
|
||||
} Channel;
|
||||
|
||||
volatile bool playing = false;
|
||||
|
||||
|
||||
static Channel chan[6] = {
|
||||
{0,0,0},
|
||||
{0,0,0},
|
||||
{0,0,0},
|
||||
{0,0,0},
|
||||
{0,0,0},
|
||||
{0,0,0} };
|
||||
|
||||
|
||||
static void snd_Reset(void)
|
||||
{
|
||||
chan[0].vol = 0;
|
||||
chan[1].vol = 0;
|
||||
chan[2].vol = 0;
|
||||
chan[3].vol = 0;
|
||||
chan[4].vol = 0;
|
||||
chan[5].vol = 0;
|
||||
chan[0].sinc = 0;
|
||||
chan[1].sinc = 0;
|
||||
chan[2].sinc = 0;
|
||||
chan[3].sinc = 0;
|
||||
chan[4].sinc = 0;
|
||||
chan[5].sinc = 0;
|
||||
}
|
||||
|
||||
#ifdef CUSTOM_SND
|
||||
//extern "C" {
|
||||
void SND_Process(void *sndbuffer, int sndn);
|
||||
//}
|
||||
#endif
|
||||
|
||||
|
||||
static void snd_Mixer16(uint16_t * stream, int len )
|
||||
{
|
||||
if (playing)
|
||||
{
|
||||
#ifdef CUSTOM_SND
|
||||
SND_Process((void*)stream, len);
|
||||
#else
|
||||
int i;
|
||||
long s;
|
||||
//len = len >> 1;
|
||||
|
||||
short v0=chan[0].vol;
|
||||
short v1=chan[1].vol;
|
||||
short v2=chan[2].vol;
|
||||
short v3=chan[3].vol;
|
||||
short v4=chan[4].vol;
|
||||
short v5=chan[5].vol;
|
||||
for (i=0;i<len;i++)
|
||||
{
|
||||
s = ( v0*(square[(chan[0].spos>>8)&0x3f]) );
|
||||
s+= ( v1*(square[(chan[1].spos>>8)&0x3f]) );
|
||||
s+= ( v2*(square[(chan[2].spos>>8)&0x3f]) );
|
||||
s+= ( v3*(noise[(chan[3].spos>>8)&(NOISEBSIZE-1)]) );
|
||||
s+= ( v4*(noise[(chan[4].spos>>8)&(NOISEBSIZE-1)]) );
|
||||
s+= ( v5*(noise[(chan[5].spos>>8)&(NOISEBSIZE-1)]) );
|
||||
*stream++ = int16_t((s>>11));
|
||||
chan[0].spos += chan[0].sinc;
|
||||
chan[1].spos += chan[1].sinc;
|
||||
chan[2].spos += chan[2].sinc;
|
||||
chan[3].spos += chan[3].sinc;
|
||||
chan[4].spos += chan[4].sinc;
|
||||
chan[5].spos += chan[5].sinc;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef USE_I2S
|
||||
#else
|
||||
void IRAM_ATTR onTimer()
|
||||
{
|
||||
// Sound playing code, plays whatever's in the buffer continuously. Big change from previous versions
|
||||
if(LastDacValue!=Buffer[NextPlayPos]) // Send value to DAC only of changed since last value else no need
|
||||
{
|
||||
// value to DAC has changed, send to actual hardware, else we just leave setting as is as it's not changed
|
||||
LastDacValue=Buffer[NextPlayPos];
|
||||
dacWrite(DacPin,uint8_t((LastDacValue>>8)+127)); // write out the data
|
||||
}
|
||||
Buffer[NextPlayPos]=0; // Reset this buffer byte back to silence
|
||||
NextPlayPos++; // Move play pos to next byte in buffer
|
||||
if(NextPlayPos==BufferSize) // If gone past end of buffer,
|
||||
NextPlayPos=0; // set back to beginning
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void AudioPlaySystem::begin(void)
|
||||
{
|
||||
#ifdef USE_I2S
|
||||
Buffer = (uint16_t *)malloc(DEFAULT_SAMPLESIZE*4); //16bits, L+R
|
||||
uint16_t * dst=(uint16_t *)Buffer;
|
||||
for (int i=0; i<DEFAULT_SAMPLESIZE; i++) {
|
||||
*dst++=32767;
|
||||
*dst++=32767;
|
||||
};
|
||||
|
||||
i2s_config_t i2s_config;
|
||||
i2s_config.mode = (i2s_mode_t)(I2S_MODE_DAC_BUILT_IN|I2S_MODE_TX|I2S_MODE_MASTER);
|
||||
i2s_config.sample_rate=DEFAULT_SAMPLERATE;
|
||||
i2s_config.bits_per_sample=I2S_BITS_PER_SAMPLE_16BIT;
|
||||
i2s_config.communication_format=I2S_COMM_FORMAT_I2S_MSB;
|
||||
i2s_config.dma_buf_count = 2;
|
||||
i2s_config.dma_buf_len = DEFAULT_SAMPLESIZE;
|
||||
i2s_config.use_apll = false;
|
||||
i2s_config.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1;
|
||||
//i2s_driver_install(I2S_NUM, &i2s_config, 4, &queue);
|
||||
i2s_driver_install(I2S_NUM, &i2s_config, 0, NULL);
|
||||
i2s_set_pin(I2S_NUM, NULL);
|
||||
i2s_set_dac_mode(I2S_DAC_CHANNEL_LEFT_EN);
|
||||
//I2S enables *both* DAC channels; we only need DAC1.
|
||||
//ToDo: still needed now I2S supports set_dac_mode?
|
||||
//CLEAR_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_DAC_XPD_FORCE_M);
|
||||
//CLEAR_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_XPD_DAC_M);
|
||||
#else
|
||||
BufferSize = DEFAULT_SAMPLESIZE;
|
||||
Buffer=(volatile uint16_t *)malloc(BufferSize*2);
|
||||
volatile uint16_t * dst=Buffer;
|
||||
for (int i=0; i<BufferSize; i++) {
|
||||
*dst++=0;
|
||||
};
|
||||
|
||||
DacPin=25; // set dac pin to use
|
||||
LastDacValue=0; // set to mid point
|
||||
dacWrite(DacPin,LastDacValue); // Set speaker to mid point, stops click at start of first sound
|
||||
// Set up interrupt routine
|
||||
timer = timerBegin(0, 80, true); // use timer 0, pre-scaler is 80 (divide by 8000), count up
|
||||
timerAttachInterrupt(timer, &onTimer, true); // P3= edge triggered
|
||||
timerAlarmWrite(timer, 45, true); // will trigger 22050 times per sec (443 per 20 ms=22050/50)
|
||||
timerAlarmEnable(timer);
|
||||
#endif
|
||||
}
|
||||
|
||||
void AudioPlaySystem::start(void)
|
||||
{
|
||||
playing = true;
|
||||
}
|
||||
|
||||
void AudioPlaySystem::setSampleParameters(float clockfreq, float samplerate) {
|
||||
}
|
||||
|
||||
void AudioPlaySystem::reset(void)
|
||||
{
|
||||
snd_Reset();
|
||||
}
|
||||
|
||||
void AudioPlaySystem::stop(void)
|
||||
{
|
||||
playing = false;
|
||||
#ifdef USE_I2S
|
||||
i2s_driver_uninstall(I2S_NUM); //stop & destroy i2s driver
|
||||
#else
|
||||
#endif
|
||||
}
|
||||
|
||||
bool AudioPlaySystem::isPlaying(void)
|
||||
{
|
||||
return playing;
|
||||
}
|
||||
|
||||
|
||||
void AudioPlaySystem::sound(int C, int F, int V) {
|
||||
if (C < 6) {
|
||||
//printf("play %d %d %d\n",C,F,V);
|
||||
|
||||
chan[C].vol = V;
|
||||
chan[C].sinc = F>>1;
|
||||
}
|
||||
}
|
||||
|
||||
void AudioPlaySystem::step(void)
|
||||
{
|
||||
#ifdef USE_I2S
|
||||
int left=DEFAULT_SAMPLERATE/50;
|
||||
|
||||
while(left) {
|
||||
int n=DEFAULT_SAMPLESIZE;
|
||||
if (n>left) n=left;
|
||||
snd_Mixer16((uint16_t*)Buffer, n);
|
||||
//16 bit mono -> 16 bit r+l
|
||||
for (int i=n-1; i>=0; i--) {
|
||||
Buffer[i*2+1]=Buffer[i]+32767;
|
||||
Buffer[i*2]=Buffer[i]+32767;
|
||||
}
|
||||
i2s_write_bytes(I2S_NUM, (const void*)Buffer, n*4, portMAX_DELAY);
|
||||
left-=n;
|
||||
}
|
||||
#else
|
||||
|
||||
int32_t CurPos=NextPlayPos;
|
||||
int32_t samples;
|
||||
if (CurPos > LastPlayPos) {
|
||||
snd_Mixer16((uint16_t *)&Buffer[LastPlayPos], CurPos-LastPlayPos);
|
||||
samples = CurPos-LastPlayPos;
|
||||
}
|
||||
else {
|
||||
snd_Mixer16((uint16_t *)&Buffer[LastPlayPos], BufferSize-LastPlayPos);
|
||||
snd_Mixer16((uint16_t *)&Buffer[0], CurPos);
|
||||
samples = BufferSize-LastPlayPos;
|
||||
samples += CurPos;
|
||||
}
|
||||
LastPlayPos = CurPos;
|
||||
//printf("sam %d\n",bytes);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#ifndef audioplaysystem_h_
|
||||
#define audioplaysystem_h_
|
||||
|
||||
#define DEFAULT_SAMPLESIZE 512 // 22050/50=443 samples per 20ms
|
||||
#define DEFAULT_SAMPLERATE 22050
|
||||
|
||||
class AudioPlaySystem
|
||||
{
|
||||
public:
|
||||
AudioPlaySystem(void) { begin(); }
|
||||
void begin(void);
|
||||
void setSampleParameters(float clockfreq, float samplerate);
|
||||
void reset(void);
|
||||
void start(void);
|
||||
void stop(void);
|
||||
bool isPlaying(void);
|
||||
void sound(int C, int F, int V);
|
||||
void buzz(int size, int val);
|
||||
void step(void);
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
const uint16_t bmpjoy[] = {
|
||||
0x001e,0x0026,0x0000,0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000,0x0000,
|
||||
0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xf4d2,0xeaea,0xe227,0xe268,0xebce,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000,
|
||||
0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xeaa9,0xe984,0xe164,0xd964,0xe184,0xe1a4,0xe1a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xe207,0xe984,0xe206,0xe2e9,0xe267,0xd964,0xd9a5,0xd984,0xf1a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xebef,0xe984,0xe288,0xeb8b,0xeb0a,0xe247,0xd984,0xd984,0xd9a5,0xe1a5,0xe1c6,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xd9c6,0xe1c5,0xeb8b,0xe247,0xd943,0xd964,0xd984,0xd984,0xd984,0xd9a5,0xe9a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xe164,0xe268,0xeb4b,0xd964,0xd984,0xd984,0xd984,0xd984,0xd984,0xd9a5,0xe9a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xe184,0xe206,0xe247,0xd984,0xd984,0xd984,0xd984,0xd984,0xd984,0xd9a5,0xe9a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xd9a5,0xd984,0xd964,0xd984,0xd984,0xd984,0xd984,0xd984,0xd984,0xd9a5,0xe9a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0x18e3,0x18e3,0x18e3,0xeb2b,0xe9a5,0xd9a5,0xd984,0xd984,0xd984,0xd984,0xd984,0xd984,0xd9a5,0xe1a4,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x247c,0x18e3,0xe71c,0xdefc,0xdedb,0xdefc,0x18e3,0xe184,0xd984,0xd9a5,0xd984,0xd984,0xd984,0xd984,0xd9a5,0xe143,0x18e3,0xdf1c,0xdedb,0xdedb,0xdefb,0xe71c,0x18e3,0x247c,0x247c,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x18e3,0xbe18,0xbe19,0xbe18,0xbe18,0xbe18,0xb619,0x18e3,0xe143,0xd943,0xd984,0xd984,0xd984,0xd964,0xe122,0x18e3,0xad96,0xbe19,0xbe18,0xbe18,0xbe18,0xbe19,0xbe18,0x18e3,0x1c5d,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xbe18,0xbdf8,0xadb7,0xadb7,0xadb7,0xb5b7,0xb5b7,0xadf8,0x18e3,0xd269,0xd9a5,0xd963,0xd984,0xda07,0x18e3,0xadb7,0xadb7,0xb5b7,0xadb7,0xadb7,0xadb7,0xadb7,0xbdf8,0xbe18,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xb5b7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xad96,0xadf8,0xbe18,0xe69a,0xe618,0xee79,0xce59,0xadf8,0xadb7,0xad97,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xad97,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xb5d7,0x9d15,0x8493,0xdf5d,0xe79e,0xefdf,0xadb7,0x8493,0xb5b7,0xb5b7,0xad97,0xadb7,0xad97,0xadb7,0xadb7,0xad97,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xadb7,0xadb7,0xad97,0xadb7,0xadb7,0x7c52,0x4b2e,0x5b90,0xdf3c,0xe75d,0xf79e,0x9515,0x42ed,0x63d0,0x9d55,0xb5b7,0xad96,0xadb7,0xad97,0xadb7,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xadb7,0xad97,0xadb7,0xadb7,0x6bf1,0x4b2e,0x4b2e,0x532e,0xdf1c,0xe75d,0xefbe,0x8cb3,0x42ac,0x534f,0x534f,0x9d15,0xb5b7,0xad96,0xadb7,0xadb7,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xadb7,0xad96,0xb5d7,0x7c52,0x4b0e,0x532e,0x322a,0x428b,0xdf1c,0xe75d,0xf7be,0x8472,0x29a8,0x4aed,0x534f,0x5b6f,0xad76,0xadb7,0xad97,0xad97,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xad97,0xad97,0xb5b7,0x9d35,0x534f,0x534f,0x3a4a,0x31e8,0x42ab,0xdf1c,0xe75d,0xf7be,0x8472,0x29c8,0x3a29,0x4b0d,0x4b2e,0x7c52,0xb5d7,0xad96,0xadb7,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xad96,0xb5d7,0x7c52,0x4b2e,0x4aed,0x3209,0x3209,0x428b,0xdf1c,0xe75d,0xf7be,0x8472,0x29c8,0x3a29,0x3a6a,0x534f,0x5b8f,0xad96,0xadb7,0xad97,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xad97,0xad97,0xb5b7,0x63d0,0x4b2f,0x428b,0x3209,0x3209,0x428b,0xdf1c,0xe75d,0xf7be,0x8472,0x29c8,0x3a2a,0x3a29,0x4b2e,0x534f,0x9d15,0xb5b7,0xad96,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xad97,0xadb7,0xad96,0x5b90,0x532e,0x3a6b,0x3209,0x3209,0x4aab,0xdf1c,0xe73d,0xef9e,0x8492,0x29c8,0x3a2a,0x3209,0x4b0d,0x4b2e,0x94f4,0xb5d7,0xad97,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xad97,0xad97,0xad97,0x5bb0,0x534f,0x3a6b,0x3209,0x3209,0x3a4a,0xd6db,0xf7be,0xf7df,0x73f0,0x29c8,0x3a2a,0x3229,0x4b0e,0x4b2e,0x94f4,0xb5d7,0xad97,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xad97,0xb5b7,0x6bf1,0x4b2e,0x42ac,0x3209,0x3a2a,0x31e8,0x636e,0xbe18,0x94d3,0x3229,0x3229,0x3209,0x3a4a,0x534f,0x534f,0x9d35,0xb5b7,0xad96,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xad97,0xad96,0xb5d7,0x8493,0x4b2e,0x532e,0x3a2a,0x3209,0x3a29,0x31e8,0x29c8,0x29c8,0x3229,0x3a29,0x3209,0x42cc,0x534f,0x63b0,0xad97,0xad97,0xad97,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xad97,0xadb7,0xa576,0x536f,0x534f,0x4aed,0x3209,0x3209,0x3a29,0x3a2a,0x3a2a,0x3229,0x3209,0x428b,0x534f,0x4b0e,0x8493,0xb5d7,0xad96,0xadb7,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xad97,0xadb7,0xad96,0xb5b7,0x8cb3,0x4b0e,0x536f,0x4b0e,0x3a6b,0x3229,0x3209,0x3209,0x3a4a,0x42cc,0x534f,0x4b0e,0x63d0,0xadb7,0xad97,0xad97,0xad96,0xad96,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xad97,0xadb7,0xadd7,0xb5b7,0x8473,0x4b0e,0x534f,0x534f,0x4b2e,0x4b0d,0x4b0e,0x534f,0x534f,0x4b0e,0x63b0,0xa576,0xb5b7,0xad97,0xad97,0xceba,0xb5f8,0xad96,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xad96,0xadd7,0xb514,0xbc92,0xadb7,0xb5d7,0x94d4,0x5b90,0x4b2e,0x4b2e,0x4b2e,0x4b2e,0x4b2e,0x534f,0x7c32,0xad96,0xb5b7,0xad97,0xad97,0xb5b7,0xe75d,0xbe18,0xad96,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xb514,0xd9c5,0xe122,0xcb6d,0xadd7,0xb5b7,0xad96,0x94f4,0x7c52,0x7432,0x7c32,0x8cb3,0xa556,0xb5d7,0xadb7,0xad97,0xadb7,0xad96,0xbe18,0xe75d,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xad96,0xadf8,0xc410,0xe101,0xd943,0xd207,0xadb7,0xad96,0xadb7,0xb5d7,0xb5d7,0xb5d7,0xb5d7,0xb5d7,0xb5b7,0xad97,0xad97,0xad97,0xad76,0xad96,0xdf3c,0xce9a,0xad76,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xb576,0xd289,0xd9a5,0xbc30,0xadd7,0xad96,0xad97,0xad97,0xad96,0xad97,0xad96,0xad96,0xad97,0xad97,0xadb7,0xb5b7,0xbe18,0xdf3c,0xdefc,0xad97,0xadb7,0xadb7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xb5d7,0xb5b7,0xadb7,0xadb7,0xb576,0xadd7,0xad97,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xad96,0xce7a,0xe75d,0xe75d,0xce9a,0xad96,0xadb7,0xb5b7,0xb5b7,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x18e3,0xd6bb,0xbe18,0xadb7,0xadb7,0xadb7,0xad96,0xadb7,0xad97,0xad97,0xad97,0xad97,0xad97,0xad97,0xad97,0xadb7,0xad97,0xb5d7,0xbe18,0xadb7,0xad76,0xadb7,0xadb7,0xbe18,0xd6bb,0x18e3,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x18e3,0xd6bb,0xbdf8,0xb5b7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xad96,0xad96,0xadb7,0xadb7,0xb5b7,0xbdf8,0xd6bb,0x18e3,0x247c,0x247c,0x247c,
|
||||
0x247c,0x247c,0x247c,0x247c,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x247c,0x247c,0x247c,0x247c,
|
||||
0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000,
|
||||
0x0000,0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000,0x0000};
|
||||
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
const uint16_t bmpvbar[] = {
|
||||
0x0020,0x0094,
|
||||
0x0000,0x0000,0x0000,0xad96,0xdf3d,0xd6fc,0xd6fc,0xd6fd,0xd6fd,0xd71d,0xdf1d,0xd71d,0xd71c,0xd71d,0xd71d,0xd71d,0xd71d,0xd71d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf3d,0xbe18,0x0000,0x0000,0x0000,0x0861,
|
||||
0x0000,0x0000,0xbe39,0xcedc,0xb63b,0xadfa,0xadfb,0xadfb,0xadfb,0xadfb,0xae1b,0xae1b,0xae1b,0xae1b,0xae1b,0xae1b,0xae3b,0xae3b,0xae3b,0xae3b,0xb63b,0xb63b,0xb63c,0xb63c,0xb65c,0xb65c,0xb65c,0xc69c,0xd71d,0x5b0c,0x0000,0x0861,
|
||||
0x0000,0x0000,0xcedd,0xa5da,0x7d19,0x74d9,0x74da,0x74fa,0x74fa,0x74fa,0x74fa,0x751a,0x751a,0x751a,0x753a,0x753b,0x7d3b,0x7d3b,0x7d5b,0x7d5b,0x7d5b,0x7d7b,0x7d7b,0x7d7b,0x7d9c,0x7d9c,0x8ddb,0x9e1b,0xae7b,0xd71d,0x0000,0x0861,
|
||||
0x0000,0xdf3d,0xa5fb,0x74da,0x4c59,0x445a,0x3c5a,0x447b,0x447b,0x447b,0x449b,0x449b,0x44bb,0x44bb,0x44db,0x4cdb,0x4cdc,0x4cfc,0x4cfc,0x4d1c,0x4d1c,0x4d3c,0x4d3c,0x555d,0x555d,0x557c,0x65bc,0x7dfb,0x961b,0xbe9c,0xad96,0x0861,
|
||||
0x0000,0xc69b,0x7d1a,0x443a,0x345b,0x2c7c,0x2c7c,0x349c,0x349c,0x34bc,0x34bc,0x34dc,0x34dc,0x3cfd,0x3cfd,0x3cfd,0x3d1d,0x3d1d,0x453d,0x455e,0x455e,0x455e,0x457e,0x4d9e,0x4d9e,0x55be,0x5dfd,0x761c,0x8e1c,0xa63b,0xd6fc,0x0861,
|
||||
0xad96,0xadfa,0x5c59,0x2c3b,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x453e,0x455e,0x457e,0x457e,0x457e,0x459f,0x4dbf,0x4dbf,0x55de,0x5dfe,0x6e1d,0x8e5d,0x9e3c,0xbe9c,0x8430,
|
||||
0xd6fd,0x8d39,0x3c1a,0x2c5c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x55fe,0x65fe,0x8e7e,0x9e7d,0xae5c,0xdf3d,
|
||||
0xcebc,0x74b9,0x343b,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x5dfe,0x7e5e,0x9e9e,0xa65c,0xd6fd,
|
||||
0xc67c,0x5c5a,0x2c3b,0x247c,0x249c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4dde,0x55de,0x763f,0x9e9e,0xa65c,0xcedc,
|
||||
0xbe5b,0x543a,0x245c,0x247c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4dde,0x55de,0x661f,0xa69e,0xae5b,0xcedc,
|
||||
0xbe3b,0x543a,0x245c,0x2c7c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x55de,0x55fe,0x5e1e,0xa69d,0xb65b,0xcebc,
|
||||
0xbe3a,0x543a,0x245c,0x2c7c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbe,0x55de,0x55fe,0x5dfe,0xa69d,0xb65b,0xcebc,
|
||||
0xbe3a,0x545a,0x245c,0x2c7c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbe,0x55de,0x55fe,0x5dfe,0xa69e,0xb67b,0xc6bc,
|
||||
0xbe3a,0x5459,0x2c5c,0x2c7c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1d,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x55be,0x4dde,0x55ff,0x5e1f,0xa69e,0xb67c,0xc6bc,
|
||||
0xbe3a,0x5459,0x2c5c,0x2c7d,0x2c7d,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x55be,0x4ddf,0x55ff,0x661f,0xa6be,0xb67c,0xc6bc,
|
||||
0xbe3a,0x5459,0x245c,0x2c7c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351d,0x3d1e,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459f,0x4d9f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351e,0x3d1e,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459f,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351e,0x3d1e,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459f,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1e,0x3d3e,0x453e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d3d,0x3d3e,0x453e,0x455e,0x457e,0x457e,0x459e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x3cdd,0x3cfd,0x3d1d,0x3d3d,0x3d3d,0x3d3d,0x453e,0x455e,0x455e,0x457e,0x459e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34bd,0x34dd,0x34dd,0x3cfd,0x3cfd,0x3d1e,0x3d3e,0x3d3d,0x3d1d,0x3d3e,0x3d3e,0x455e,0x457e,0x459e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34bc,0x34dd,0x34fd,0x3cfd,0x3d1e,0x3d3e,0x3d3e,0x3d3d,0x3d1d,0x3d1e,0x3d3e,0x3d3e,0x455e,0x457e,0x459e,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34bc,0x34dd,0x3cfd,0x3d1d,0x453e,0x3d5e,0x3d5e,0x453d,0x451d,0x3d1d,0x351e,0x3d1e,0x3d3e,0x457e,0x459e,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34dd,0x34fd,0x3d1d,0x453d,0x455e,0x457e,0x455e,0x4d3d,0x4d3d,0x3d1d,0x34fe,0x351d,0x3d1d,0x3d5e,0x457e,0x4d9f,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34dd,0x34fd,0x3d3e,0x457e,0x457e,0x457e,0x4d5d,0x5d7d,0x657d,0x451d,0x34fd,0x34fd,0x34fd,0x3d3e,0x457e,0x4d9f,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34dd,0x3d1d,0x455e,0x459e,0x459e,0x457d,0x5d5c,0x85dd,0x861d,0x5d5d,0x3cfd,0x34dd,0x34dd,0x351d,0x3d5e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34fd,0x3d3d,0x459e,0x4dbe,0x4dbe,0x4d5d,0x757c,0xae7d,0xaebe,0x75bd,0x451d,0x34dd,0x2cbd,0x34fd,0x3d3e,0x457e,0x4dbe,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2cbd,0x2cbd,0x351d,0x455d,0x45be,0x4ddf,0x459e,0x553c,0x95db,0xcf1e,0xcf3e,0x963e,0x553d,0x34dd,0x2cbc,0x2cbd,0x3d1d,0x455d,0x4dbe,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2cbd,0x34dd,0x3d1d,0x459d,0x4dbe,0x4ddf,0x459e,0x6d5b,0xb67c,0xe79e,0xe79f,0xb6be,0x6d7d,0x3cdd,0x2c9c,0x2cbd,0x34fd,0x455d,0x4dbe,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9c,0x2cbd,0x34dd,0x3d3d,0x4d9d,0x4dde,0x4dbe,0x4d7d,0x85bb,0xcefd,0xf7bf,0xefdf,0xcf3e,0x8ddd,0x44dd,0x349c,0x2c9c,0x34dd,0x3d3e,0x459e,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9d,0x2cbd,0x34fd,0x455d,0x4dbd,0x55de,0x4dbe,0x5d5c,0xa61b,0xe75d,0xffdf,0xf7df,0xe77e,0xae5d,0x5d1d,0x34bc,0x349c,0x34bc,0x3d1e,0x459f,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x249c,0x2c9c,0x2cbc,0x3cfd,0x455d,0x4dde,0x55fe,0x4d9d,0x757b,0xbe9c,0xef9e,0xffde,0xffdf,0xefbe,0xc6de,0x757d,0x3cbd,0x2c9c,0x349c,0x351d,0x457e,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x247c,0x2c9c,0x2cbc,0x3cfd,0x457e,0x4dde,0x4dde,0x557c,0x8ddb,0xd71d,0xf7be,0xffde,0xffdf,0xf7df,0xdf5e,0x95fd,0x4cdd,0x2c9d,0x2c9c,0x34fd,0x457e,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x247c,0x2c9c,0x34bc,0x3cfd,0x459e,0x4dff,0x4dbe,0x657b,0xae5b,0xe77e,0xffde,0xffde,0xffdf,0xf7df,0xe79e,0xae7d,0x5d3d,0x2c9d,0x2c9c,0x34dd,0x455e,0x4dbe,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x34bc,0x3d1d,0x459e,0x4ddf,0x4d9d,0x7d9b,0xc6dc,0xefbf,0xffde,0xffde,0xffdf,0xf7ff,0xf7be,0xc6fe,0x7d9d,0x349d,0x2c9c,0x34dd,0x455e,0x4dbe,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x34bc,0x3d1d,0x459f,0x4dde,0x557c,0x9dfb,0xdf5d,0xf7df,0xffde,0xffde,0xffff,0xffff,0xf7de,0xdf5e,0x9e1e,0x4cdd,0x2c9c,0x34fd,0x455e,0x4dbe,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x34bc,0x3d1d,0x457e,0x4d9d,0x6d7b,0xb67c,0xef9e,0xf7ff,0xffde,0xffdf,0xffff,0xffff,0xf7de,0xef9e,0xb69e,0x6d3c,0x349c,0x34fd,0x457e,0x4dbe,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9d,0x34bc,0x3cfd,0x457e,0x4d5c,0x859a,0xcefd,0xf7be,0xfffe,0xfffe,0xffff,0xffff,0xffff,0xffde,0xf7be,0xd71e,0x859c,0x3cbc,0x34fd,0x3d7e,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9d,0x34bd,0x3cfd,0x455e,0x553b,0x9dfb,0xdf5e,0xf7df,0xfffe,0xfffe,0xffff,0xffff,0xffff,0xffde,0xf7df,0xe77e,0xa61d,0x54fc,0x351e,0x457e,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x247c,0x2c9d,0x34bd,0x34fd,0x453d,0x5d3b,0xae5c,0xe77e,0xf7df,0xf7df,0xf7df,0xf7df,0xf7df,0xf7df,0xf7bf,0xf7bf,0xe77e,0xae7d,0x5d1c,0x3d1e,0x459e,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x247c,0x2c9d,0x34bd,0x34dd,0x3d1d,0x653c,0xa65d,0xd75e,0xe79f,0xe79f,0xe79f,0xe79f,0xe79f,0xe77f,0xe77f,0xdf7f,0xd73e,0xa67d,0x5d3d,0x3d3e,0x459f,0x4dbe,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9d,0x349c,0x34dd,0x3d1d,0x5d3d,0x963d,0xbede,0xc71f,0xc71f,0xc6ff,0xc6ff,0xbeff,0xbede,0xbede,0xbebe,0xb69d,0x8e1d,0x553d,0x3d5e,0x459f,0x4dbe,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9d,0x349c,0x34bd,0x34fe,0x4d5e,0x75de,0x965e,0x967f,0x965f,0x965f,0x963e,0x961e,0x8e1e,0x8dfd,0x8ddd,0x85bd,0x6d7d,0x453d,0x3d5e,0x459f,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9d,0x349c,0x34bd,0x34fe,0x455e,0x5d9e,0x6dde,0x6dde,0x6dde,0x65be,0x659e,0x657e,0x5d5d,0x5d3d,0x5d3c,0x551c,0x4d1d,0x3d3d,0x457e,0x4d9f,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9d,0x349c,0x34bc,0x34dd,0x3d3e,0x4d7e,0x559e,0x559e,0x4d9e,0x4d7e,0x455e,0x451d,0x451d,0x3cfd,0x3cdd,0x3cdd,0x3cfd,0x3d5e,0x459e,0x4d9f,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9d,0x349d,0x34bc,0x34dd,0x3d1e,0x455e,0x457e,0x4d9e,0x4d7e,0x455e,0x453e,0x3d1d,0x3d1d,0x34fd,0x34fd,0x34fe,0x3d1e,0x3d7e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9d,0x2c9d,0x34bc,0x34dc,0x34fd,0x3d3e,0x455e,0x457e,0x457e,0x455e,0x3d3e,0x3d3e,0x3d1d,0x351d,0x34fd,0x3d1e,0x3d3e,0x457e,0x4d9e,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9d,0x2c9d,0x2cbc,0x34bc,0x34dd,0x3d1d,0x3d3e,0x455e,0x455e,0x3d5e,0x3d3e,0x3d3e,0x3d1e,0x3d1d,0x3d1d,0x3d3e,0x455e,0x457e,0x4d9e,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9d,0x2c9d,0x2cbd,0x34bd,0x34dd,0x3cfd,0x3d1d,0x3d3e,0x3d3e,0x3d3e,0x3d3e,0x3d3e,0x3d1e,0x3d1d,0x3d3d,0x455e,0x457e,0x4d9e,0x4d9f,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9c,0x2cbd,0x2cbd,0x34bd,0x34dd,0x34dd,0x3cfd,0x3d1d,0x3d3e,0x3d3e,0x3d3e,0x3d3e,0x3d1e,0x3d3e,0x453e,0x457e,0x457e,0x4d9f,0x4d9f,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2cbd,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3d1d,0x3d1d,0x3d1e,0x3d3e,0x3d3e,0x3d3e,0x3d3e,0x455e,0x457e,0x459e,0x4d9f,0x4d9f,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2cbd,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1e,0x3d3e,0x453e,0x453e,0x457e,0x457e,0x459e,0x4d9f,0x4d9f,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2cbd,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1e,0x3d3e,0x453e,0x455e,0x457e,0x457e,0x459e,0x4d9f,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x453e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6be,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dde,0x4dde,0x55ff,0x5e1f,0xa6be,0xb67c,0xc6bc,
|
||||
0xbe3a,0x543a,0x245c,0x247d,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x2cbd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1d,0x3d1e,0x3d3e,0x453e,0x455e,0x457e,0x457e,0x459e,0x459e,0x4dbf,0x4dbf,0x4dde,0x4dde,0x55ff,0x5e1f,0xa69e,0xb67c,0xc6bc,
|
||||
0xc63b,0x543a,0x245c,0x247d,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x2cbd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1e,0x3d3e,0x3d3e,0x3d3e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dde,0x55de,0x55df,0x5e1f,0xa69e,0xb65c,0xc6bc,
|
||||
0xc63b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x2cbd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1e,0x3d3e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x4d9f,0x4dbf,0x4dbf,0x4ddf,0x55de,0x55df,0x5e1f,0xa69e,0xb63b,0xc6bc,
|
||||
0xc63b,0x5439,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d3e,0x453e,0x455e,0x455e,0x457e,0x457e,0x459e,0x4d9f,0x4dbf,0x4dbf,0x4ddf,0x4dde,0x55df,0x5e3f,0xa69e,0xb65b,0xc6bc,
|
||||
0xbe3b,0x5439,0x245b,0x247c,0x2c7c,0x2c7c,0x2c9c,0x349d,0x34bd,0x34dd,0x34dd,0x3cfd,0x3cfd,0x3d1d,0x3d1d,0x3d3e,0x453e,0x455e,0x455e,0x457e,0x457e,0x457e,0x4d9e,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x5e3f,0xa6be,0xb65c,0xc6bc,
|
||||
0xbe3b,0x5439,0x2c5b,0x247c,0x2c7c,0x2c7c,0x2c9c,0x349d,0x34bd,0x34bd,0x34dd,0x3cdd,0x3cfd,0x3cfd,0x3d1d,0x3d1d,0x453e,0x453e,0x455e,0x455e,0x457e,0x457e,0x4d9e,0x4d9e,0x4dbe,0x4dbf,0x55df,0x55ff,0x5e1f,0xa6be,0xb67c,0xce9c,
|
||||
0xbe3b,0x5439,0x2c3b,0x2c3c,0x2c5c,0x2c5c,0x2c7c,0x2c9c,0x349c,0x349c,0x34bc,0x34bc,0x3cdc,0x3cdd,0x3cfd,0x3cfd,0x3d1d,0x451d,0x453d,0x453e,0x455e,0x455e,0x457e,0x4d7e,0x4d9e,0x4d9e,0x4dbe,0x55be,0x5dfe,0x967e,0xae5c,0xc69c,
|
||||
0xbe3b,0x5418,0x33f9,0x341a,0x343b,0x343b,0x345b,0x347b,0x347b,0x3c7b,0x3c9b,0x3c9b,0x3cbc,0x3cbc,0x44dc,0x44dc,0x44dc,0x44fc,0x451c,0x451d,0x451d,0x4d3d,0x4d3d,0x4d5d,0x4d5d,0x4d5d,0x557c,0x559c,0x55bc,0x861c,0x9dfb,0xc69c,
|
||||
0xbe3b,0x5c38,0x4439,0x4c5a,0x4c5a,0x4c7a,0x547a,0x549a,0x549a,0x549a,0x54ba,0x54ba,0x54bb,0x5cdb,0x5cdb,0x5cfb,0x5cfb,0x5cfb,0x5d1b,0x5d1b,0x5d1b,0x5d3b,0x5d3c,0x655c,0x655c,0x5d5b,0x5d7b,0x659b,0x659b,0x85db,0x8db9,0xc69c,
|
||||
0xbe3b,0x6c78,0x64ba,0x6cda,0x6cfa,0x6cfa,0x751a,0x751a,0x751a,0x751a,0x753a,0x753b,0x753b,0x755b,0x755b,0x755b,0x7d5b,0x7d7b,0x7d7b,0x7d7b,0x7d7b,0x7d9b,0x7d9b,0x7d9b,0x7dbb,0x7dbb,0x7ddb,0x7ddb,0x7ddc,0x8dfb,0x9599,0xc69c,
|
||||
0xbe3b,0x74d9,0x7d5b,0x857b,0x857c,0x859b,0x859b,0x859b,0x85bc,0x85bc,0x8dbc,0x8dbc,0x8ddc,0x8ddc,0x8ddc,0x8ddc,0x8dfc,0x8dfc,0x8dfc,0x8dfc,0x8e1c,0x8e1c,0x8e1c,0x961d,0x963d,0x8e3d,0x8e5c,0x965c,0x965d,0xa65c,0xa5fa,0xc69c,
|
||||
0xbe3b,0x74da,0x7d7c,0x859c,0x859c,0x85bc,0x85bd,0x85bd,0x85bd,0x85dd,0x85dd,0x8ddd,0x8dfd,0x8dfd,0x8dfd,0x8dfd,0x8e1d,0x8e1d,0x8e3d,0x8e3d,0x8e3e,0x8e3e,0x8e5e,0x8e5e,0x8e5e,0x967e,0x967d,0x967e,0x9e7e,0xb6be,0xae5b,0xc6bc,
|
||||
0xbe3b,0x6cba,0x6d1c,0x6d3c,0x6d3c,0x6d5d,0x6d5d,0x757d,0x757d,0x757d,0x759d,0x759d,0x75bd,0x75bd,0x75be,0x75de,0x75de,0x75de,0x75fe,0x75fe,0x761e,0x7e1e,0x7e1e,0x7e3f,0x7e3f,0x7e5f,0x7e5e,0x865e,0x8e7f,0xb6de,0xb67c,0xc6bc,
|
||||
0xbe3b,0x5c5a,0x4c9c,0x4cbc,0x4cbc,0x4cdc,0x4cdd,0x4cfd,0x4cfd,0x551d,0x551d,0x553d,0x553d,0x555d,0x555d,0x555d,0x557e,0x5d7e,0x5d9e,0x5dbe,0x5dbe,0x5dbe,0x5dde,0x5ddf,0x65ff,0x65ff,0x65ff,0x661f,0x763f,0xaebf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x5439,0x2c5c,0x2c7c,0x2c7c,0x349c,0x349c,0x34bd,0x34bd,0x34dd,0x3cdd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3d,0x453e,0x455e,0x457e,0x457e,0x457e,0x459e,0x4d9e,0x4dbf,0x4dbf,0x4ddf,0x55df,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34fd,0x3d1d,0x3d3d,0x453e,0x453e,0x4d5e,0x4d5e,0x3d3e,0x3d1e,0x3d1e,0x3d3e,0x457e,0x459e,0x4d9e,0x4dbe,0x55de,0x5dfe,0x5e1f,0x6e3f,0xa6be,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34fd,0x3d1d,0x3d1d,0x453d,0x453e,0x3d3e,0x3d3e,0x3d3d,0x3d3d,0x3d3e,0x3d5e,0x457f,0x459e,0x4d9e,0x55be,0x5dde,0x5dfe,0x5e1f,0x661f,0xa6be,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351d,0x3d1d,0x453d,0x3d3e,0x3d3e,0x3d3d,0x455d,0x455e,0x457e,0x457f,0x459f,0x4d9e,0x55be,0x5dde,0x5dff,0x5e1f,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351d,0x3d1d,0x3d1d,0x3d3d,0x3d3e,0x453d,0x455d,0x457e,0x457e,0x457f,0x4d9f,0x55be,0x5dde,0x5dfe,0x5dff,0x5dff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351d,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x457f,0x4d9e,0x55be,0x5dde,0x5dff,0x5dff,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x457e,0x4d9e,0x55be,0x5dde,0x5dff,0x55ff,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x4d7e,0x55be,0x5ddf,0x5dff,0x55df,0x55df,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x4d9e,0x55be,0x5ddf,0x55df,0x55df,0x55df,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x559e,0x55de,0x55df,0x55df,0x55df,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x4d7e,0x55be,0x5dde,0x55df,0x55df,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x4d9e,0x55be,0x55de,0x55bf,0x4dbf,0x4ddf,0x55df,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x4d7e,0x55be,0x55be,0x55be,0x4dbe,0x4dbf,0x4ddf,0x55df,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x4d9e,0x55be,0x55be,0x4dbe,0x4dbe,0x4dbf,0x4ddf,0x55df,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x4d7e,0x559e,0x55be,0x55be,0x4d9e,0x4dbf,0x4dbf,0x4ddf,0x55df,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc,
|
||||
0xbe3b,0x5439,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1e,0x3d1e,0x3d3e,0x455e,0x4d7e,0x559e,0x55be,0x4d9e,0x4d9e,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xcebc,
|
||||
0xbe5b,0x5459,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x34bd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1e,0x3d1e,0x3d1e,0x453d,0x4d5e,0x559e,0x559e,0x4d9e,0x4d9f,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa69e,0xb67c,0xcedc,
|
||||
0xbe7b,0x5c59,0x2c3b,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x351d,0x3d1e,0x3d1d,0x453d,0x4d5d,0x559e,0x4d9e,0x4d9e,0x459f,0x459f,0x4d9f,0x4dbf,0x4ddf,0x55df,0x55ff,0x6e3f,0xa69e,0xae5b,0xcedc,
|
||||
0xc69c,0x6c98,0x2c3b,0x247d,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x351d,0x3d1d,0x451d,0x4d3d,0x557d,0x559e,0x4d9e,0x4d9e,0x457e,0x459e,0x4d9f,0x4dbf,0x4dde,0x55de,0x55de,0x7e5e,0xa69d,0xae3b,0xd6fc,
|
||||
0xd6fd,0x8519,0x341a,0x247c,0x2c7d,0x2c9c,0x2c9c,0x2cbc,0x2cbc,0x34dd,0x34fd,0x34fd,0x351d,0x351d,0x3d1d,0x453d,0x4d5d,0x559d,0x4d9e,0x4d7e,0x457e,0x457e,0x4d9e,0x4d9e,0x4dbe,0x55de,0x5dde,0x5dfe,0x8e5e,0xa65c,0xae5b,0xdf3d,
|
||||
0xdf3d,0xa5ba,0x4c39,0x2c5c,0x247c,0x2c9c,0x2c9c,0x2cbc,0x34bc,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1c,0x453d,0x4d7d,0x4d9e,0x4d7e,0x457e,0x457e,0x457e,0x4d9e,0x4d9e,0x4dbe,0x55be,0x5dde,0x6e1e,0x8e5d,0x9e3b,0xbe7b,0xdf3c,
|
||||
0x0000,0xbe7c,0x74d9,0x3c3a,0x2c5b,0x2c7c,0x2c9c,0x349c,0x34bc,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x451c,0x4d3d,0x4d7d,0x4d7e,0x455d,0x455e,0x455e,0x457e,0x4d7e,0x4d9e,0x4d9e,0x55be,0x65fe,0x763e,0x8e1c,0xa61b,0xd6dc,0x0861,
|
||||
0x0000,0xd6fd,0x9dba,0x6499,0x443a,0x345b,0x3c5b,0x3c7b,0x3c7b,0x3c7c,0x3c9c,0x3c9c,0x3cbc,0x44dc,0x4cfc,0x551c,0x553c,0x4d1c,0x451c,0x451d,0x453d,0x4d3d,0x4d5d,0x4d5d,0x4d7d,0x557d,0x65dd,0x7e1d,0x8e1c,0xb65b,0xdefc,0x0861,
|
||||
0x0000,0x0000,0xc69c,0x9579,0x6cb9,0x649a,0x649a,0x649a,0x64ba,0x64ba,0x64ba,0x64db,0x64db,0x6cfb,0x6d1b,0x753b,0x6d3b,0x6d1b,0x6d1b,0x6d3b,0x6d3b,0x6d5b,0x6d5c,0x6d5c,0x6d5c,0x757c,0x7dbc,0x95fb,0xa65b,0xcefd,0x0000,0x0861,
|
||||
0x0000,0x0000,0xe73d,0xc69c,0xa5da,0x9d9a,0x9d9a,0x9d9a,0xa59a,0xa5ba,0xa5ba,0x9dbb,0x9dbb,0xa5ba,0xa5da,0xa5fa,0xa5da,0xa5db,0xa5db,0xa5db,0xa5db,0xa5fb,0xa5fb,0xa5fb,0xa5fb,0xa61b,0xae3b,0xb67b,0xc6dc,0xe75e,0x0000,0x0861,
|
||||
0x0000,0x0000,0x0000,0xe75d,0xd6fc,0xcebc,0xcebc,0xcebc,0xcebc,0xcebc,0xcebc,0xcebc,0xcebc,0xcebc,0xcedc,0xcedc,0xcedc,0xcedc,0xcedc,0xcedc,0xcedc,0xcedc,0xcedc,0xcedc,0xd6dc,0xd6dc,0xd6fc,0xd71c,0xdf1c,0x0000,0x0000,0x0861};
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#
|
||||
# Main component makefile.
|
||||
#
|
||||
# This Makefile can be left empty. By default, it will take the sources in the
|
||||
# src/ directory, compile them and link them into lib(subdirectory_name).a
|
||||
# in the build directory. This behaviour is entirely configurable,
|
||||
# please read the ESP-IDF documents if you need to do this.
|
||||
#
|
||||
|
||||
CPPFLAGS += -Wno-error=parentheses -Wno-error=maybe-uninitialized #-DEMULATED_JOYSTICK -DUSE_SHORT_SLICE -DUSE_DOUBLE_BUFFER -DNO_SOUND -fno-common -fno-builtin -fno-exceptions -fstrict-aliasing -Wno-narrowing -Wno-error=unused-value -Wno-error=return-type -Wno-error=sequence-point -Wno-error=implicit-int -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-error=char-subscripts -Wno-error=attributes
|
||||
#-Werror=maybe-uninitialized
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,263 @@
|
|||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include "emu.h"
|
||||
|
||||
|
||||
extern uint8_t bootdrive, hdcount;
|
||||
extern uint16_t segregs[6];
|
||||
extern uint8_t cf;
|
||||
extern _bytewordregs_ regs;
|
||||
|
||||
FILE *file;
|
||||
|
||||
struct struct_drive {
|
||||
uint32_t filesize;
|
||||
uint16_t cyls;
|
||||
uint16_t sects;
|
||||
uint16_t heads;
|
||||
uint8_t inserted;
|
||||
} disk[4];
|
||||
uint8_t sectorbuffer[512];
|
||||
|
||||
uint8_t insertdisk(uint8_t drivenum) {
|
||||
if (drivenum & 0x80) {
|
||||
drivenum -= 126;
|
||||
disk[drivenum].sects = 63;
|
||||
disk[drivenum].heads = 16;
|
||||
disk[drivenum].cyls = 1023; //up to 512 MB
|
||||
hdcount = 1;
|
||||
} else {
|
||||
#ifdef FDD_144M
|
||||
disk[drivenum].cyls = 80;
|
||||
disk[drivenum].sects = 18;
|
||||
disk[drivenum].heads = 2;
|
||||
#endif
|
||||
#ifdef FDD_122M
|
||||
disk[drivenum].cyls = 80;
|
||||
disk[drivenum].sects = 15;
|
||||
disk[drivenum].heads = 2;
|
||||
#endif
|
||||
#ifdef FDD_720K
|
||||
disk[drivenum].cyls = 80;
|
||||
disk[drivenum].sects = 9;
|
||||
disk[drivenum].heads = 2;
|
||||
#endif
|
||||
#ifdef FDD_360K
|
||||
disk[drivenum].cyls = 40;
|
||||
disk[drivenum].sects = 9;
|
||||
disk[drivenum].heads = 2;
|
||||
#endif
|
||||
#ifdef FDD_320K
|
||||
disk[drivenum].cyls = 40;
|
||||
disk[drivenum].sects = 8;
|
||||
disk[drivenum].heads = 2;
|
||||
#endif
|
||||
#ifdef FDD_180K
|
||||
disk[drivenum].cyls = 40;
|
||||
disk[drivenum].sects = 9;
|
||||
disk[drivenum].heads = 1;
|
||||
#endif
|
||||
}
|
||||
disk[drivenum].inserted = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ejectdisk(uint8_t drivenum) {
|
||||
if (drivenum & 0x80) drivenum -= 126;
|
||||
disk[drivenum].inserted = 0;
|
||||
}
|
||||
|
||||
extern uint16_t ramseg;
|
||||
extern "C" {
|
||||
extern void emu_SdReadBlock(int block, void * buf);
|
||||
}
|
||||
uint8_t sectdone;
|
||||
void getsect(uint32_t lba, uint8_t *dst) {
|
||||
#ifdef USB_DISK
|
||||
uint8_t chksum;
|
||||
uint32_t curmicros;
|
||||
retrysectget:
|
||||
Serial.write(0xFF);
|
||||
Serial.write(0x05);
|
||||
outByte(lba & 0xFF); chksum = lba & 0xFF;
|
||||
outByte((lba >> 8) & 0xFF); chksum += (lba >> 8) & 0xFF;
|
||||
outByte((lba >> 16) & 0xFF); chksum += (lba >> 16) & 0xFF;
|
||||
outByte((lba >> 24) & 0xFF); chksum += (lba >> 24) & 0xFF;
|
||||
outByte(chksum);
|
||||
Serial.write(0xFE);
|
||||
Serial.write(0x02);
|
||||
sectdone = 0;
|
||||
curmicros = micros();
|
||||
while (!sectdone) {
|
||||
if (micros() < curmicros) curmicros = micros();
|
||||
if ((micros() - curmicros) >= 200000) goto retrysectget;
|
||||
net_loop();
|
||||
}
|
||||
#else
|
||||
if (file)
|
||||
{
|
||||
//printf("read block %d\n",lba);
|
||||
fseek(file,lba*512,SEEK_SET);
|
||||
fread(dst,1,512,file);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void putsect(uint32_t lba, uint8_t *src) {
|
||||
#ifdef USB_DISK
|
||||
uint8_t chksum;
|
||||
uint16_t i;
|
||||
uint32_t curmicros;
|
||||
retrysectput:
|
||||
Serial.write(0xFF);
|
||||
Serial.write(0x06);
|
||||
outByte(lba & 0xFF); chksum = lba & 0xFF;
|
||||
outByte((lba >> 8) & 0xFF); chksum += (lba >> 8) & 0xFF;
|
||||
outByte((lba >> 16) & 0xFF); chksum += (lba >> 16) & 0xFF;
|
||||
outByte((lba >> 24) & 0xFF); chksum += (lba >> 24) & 0xFF;
|
||||
for (i=0; i<512; i++) {
|
||||
outByte(src[i]);
|
||||
chksum += src[i];
|
||||
}
|
||||
outByte(chksum);
|
||||
Serial.write(0xFE);
|
||||
Serial.write(0x02);
|
||||
sectdone = 0;
|
||||
curmicros = micros();
|
||||
while (!sectdone) {
|
||||
if (micros() < curmicros) curmicros = micros();
|
||||
if ((micros() - curmicros) >= 200000) goto retrysectput;
|
||||
net_loop();
|
||||
}
|
||||
#else
|
||||
//card.writeBlock(lba, src);
|
||||
#endif
|
||||
}
|
||||
void readdisk(uint8_t drivenum, uint16_t dstseg, uint16_t dstoff, uint16_t cyl, uint16_t sect, uint16_t head, uint16_t sectcount) {
|
||||
uint32_t memdest, goodsects, dummy, lba;
|
||||
if ((sect == 0) || !disk[drivenum].inserted) return;
|
||||
#ifdef MEGA
|
||||
SPI.setClockDivider(SPI_CLOCK_SDCARD);
|
||||
#endif
|
||||
lba = ((long)cyl * (long)disk[drivenum].heads + (long)head) * (long)disk[drivenum].sects + (long)sect - 1;
|
||||
memdest = (uint32_t)dstseg * 16 + (uint32_t)dstoff;
|
||||
for (goodsects = 0; goodsects < sectcount; goodsects++) {
|
||||
getsect(lba, sectorbuffer);
|
||||
memdest = (uint32_t)dstseg * 16 + (uint32_t)dstoff;
|
||||
for (dummy = 0; dummy < 512; dummy++) {
|
||||
write86(memdest++, sectorbuffer[dummy]);
|
||||
//Serial.write(sectorbuffer[dummy]);
|
||||
}
|
||||
dstoff += 512;
|
||||
lba++;
|
||||
}
|
||||
cf = 0; regs.byteregs[regah] = 0; regs.byteregs[regal] = sectcount;
|
||||
#ifdef MEGA
|
||||
SPI.setClockDivider(SPI_CLOCK_SPIRAM);
|
||||
#endif
|
||||
}
|
||||
|
||||
void writedisk(uint8_t drivenum, uint16_t dstseg, uint16_t dstoff, uint16_t cyl, uint16_t sect, uint16_t head, uint16_t sectcount) {
|
||||
uint32_t memdest, goodsects, dummy, lba;
|
||||
if ((sect == 0) || !disk[drivenum].inserted) return;
|
||||
#ifdef MEGA
|
||||
SPI.setClockDivider(SPI_CLOCK_SDCARD);
|
||||
#endif
|
||||
lba = ((long)cyl * (long)disk[drivenum].heads + (long)head) * (long)disk[drivenum].sects + (long)sect - 1;
|
||||
for (goodsects = 0; goodsects < sectcount; goodsects++) {
|
||||
memdest = (uint32_t)dstseg * 16 + (uint32_t)dstoff;
|
||||
for (dummy = 0; dummy < 512; dummy++) {
|
||||
sectorbuffer[dummy] = read86(memdest++);
|
||||
}
|
||||
//card.erase(lba, lba);
|
||||
putsect(lba, sectorbuffer);
|
||||
dstoff += 512;
|
||||
lba++;
|
||||
}
|
||||
cf = 0; regs.byteregs[regah] = 0; regs.byteregs[regal] = sectcount;
|
||||
#ifdef MEGA
|
||||
SPI.setClockDivider(SPI_CLOCK_SPIRAM);
|
||||
#endif
|
||||
}
|
||||
|
||||
void diskhandler() {
|
||||
static uint8_t lastdiskah[4], lastdiskcf[4];
|
||||
uint8_t drivenum;
|
||||
drivenum = regs.byteregs[regdl];
|
||||
if (drivenum & 0x80) drivenum -= 126;
|
||||
switch (regs.byteregs[regah]) {
|
||||
case 0: //reset disk system
|
||||
regs.byteregs[regah] = 0; cf = 0; //useless function in an emulator. say success and return.
|
||||
break;
|
||||
case 1: //return last status
|
||||
regs.byteregs[regah] = lastdiskah[drivenum];
|
||||
cf = lastdiskcf[drivenum];
|
||||
return;
|
||||
case 2: //read sector(s) into memory
|
||||
if (disk[drivenum].inserted) {
|
||||
readdisk(drivenum, segregs[reges], getreg16(regbx), (uint16_t)regs.byteregs[regch] + ((uint16_t)regs.byteregs[regcl] / 64) * 256, regs.byteregs[regcl] & 63, regs.byteregs[regdh], regs.byteregs[regal]);
|
||||
cf = 0; regs.byteregs[regah] = 0;
|
||||
} else {
|
||||
cf = 1;
|
||||
regs.byteregs[regah] = 1;
|
||||
}
|
||||
break;
|
||||
case 3: //write sector(s) from memory
|
||||
if (disk[drivenum].inserted) {
|
||||
writedisk(drivenum, segregs[reges], getreg16(regbx), regs.byteregs[regch] + (regs.byteregs[regcl] / 64) * 256, regs.byteregs[regcl] & 63, regs.byteregs[regdh], regs.byteregs[regal]);
|
||||
cf = 0; regs.byteregs[regah] = 0;
|
||||
} else {
|
||||
cf = 1;
|
||||
regs.byteregs[regah] = 1;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
case 5: //format track
|
||||
cf = 0; regs.byteregs[regah] = 0;
|
||||
break;
|
||||
case 8: //get drive parameters
|
||||
if (disk[drivenum].inserted) {
|
||||
cf = 0; regs.byteregs[regah] = 0;
|
||||
regs.byteregs[regch] = disk[drivenum].cyls - 1;
|
||||
regs.byteregs[regcl] = disk[drivenum].sects & 63;
|
||||
regs.byteregs[regcl] = regs.byteregs[regcl] + (disk[drivenum].cyls / 256) * 64;
|
||||
regs.byteregs[regdh] = disk[drivenum].heads - 1;
|
||||
//segregs[reges] = 0; regs.wordregs[regdi] = 0x7C0B; //floppy parameter table
|
||||
if (drivenum < 2) {
|
||||
regs.byteregs[regbl] = 4; //else regs.byteregs[regbl] = 0;
|
||||
regs.byteregs[regdl] = 2;
|
||||
} else regs.byteregs[regdl] = hdcount;
|
||||
} else {
|
||||
cf = 1; regs.byteregs[regah] = 0xAA;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
cf = 1;
|
||||
}
|
||||
lastdiskah[drivenum] = regs.byteregs[regah];
|
||||
lastdiskcf[drivenum] = cf;
|
||||
if (regs.byteregs[regdl] & 0x80) write86(0x474, regs.byteregs[regah]);
|
||||
}
|
||||
|
||||
void initDisk(char * filename) {
|
||||
int len=0;
|
||||
if (NULL != (file = fopen(filename, "rb"))) {
|
||||
fseek(file,0,SEEK_END);
|
||||
len = ftell(file);
|
||||
//printf("disk size %d\n",len);
|
||||
fseek(file,0,SEEK_SET);
|
||||
|
||||
}
|
||||
|
||||
if (len) {
|
||||
bootdrive = 0x80;
|
||||
insertdisk(0x80);
|
||||
hdcount = 1;
|
||||
}
|
||||
else {
|
||||
bootdrive = 0xFF;
|
||||
fclose(file);
|
||||
file = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
//Uncomment MEGA define if using a Mega 2560, otherwise leave undefined if using a Teensy 3.6
|
||||
//#define MEGA
|
||||
|
||||
|
||||
#define RAM_SIZE 655360UL
|
||||
#define NATIVE_RAM (32768) // 231424UL
|
||||
#define NATIVE_START 0UL
|
||||
|
||||
|
||||
|
||||
#define ROM_READ(a,b) a[b]
|
||||
|
||||
|
||||
//#define INCLUDE_ROM_BASIC
|
||||
|
||||
|
||||
//#define BOOT_FDD
|
||||
#define BOOT_HDD
|
||||
//#define BOOT_BASIC
|
||||
|
||||
//#define FDD_180K
|
||||
//#define FDD_320K
|
||||
//#define FDD_360K
|
||||
//#define FDD_720K
|
||||
//#define FDD_122M
|
||||
//#define FDD_144M
|
||||
|
||||
|
||||
#define BAUD_RATE 1000000
|
||||
|
||||
//#define USE_NETWORKING
|
||||
//#define USE_PARALLEL
|
||||
|
||||
//#define PROFILING
|
||||
|
||||
// END ARDUINO86 USER CONFIGURABLE OPTIONS
|
||||
|
||||
#define regax 0
|
||||
#define regcx 1
|
||||
#define regdx 2
|
||||
#define regbx 3
|
||||
#define regsp 4
|
||||
#define regbp 5
|
||||
#define regsi 6
|
||||
#define regdi 7
|
||||
#define reges 0
|
||||
#define regcs 1
|
||||
#define regss 2
|
||||
#define regds 3
|
||||
|
||||
#define regal 0
|
||||
#define regah 1
|
||||
#define regcl 2
|
||||
#define regch 3
|
||||
#define regdl 4
|
||||
#define regdh 5
|
||||
#define regbl 6
|
||||
#define regbh 7
|
||||
|
||||
#define StepIP(x) ip+=x
|
||||
#define getmem8(x,y) read86(segbase(x)+(uint32_t)y)
|
||||
//#define getmem16(x,y) (read86(segbase(x)+y) | ((uint16_t)read86(segbase(x)+y+1)<<8))
|
||||
#define getmem16(x,y) readw86(segbase(x)+(uint32_t)y)
|
||||
#define putmem8(x,y,z) write86(segbase(x)+(uint32_t)y, z)
|
||||
//#define putmem16(x,y,z) write86(segbase(x)+y, ((z)&0xFF)); write86(segbase(x)+y+1, (((z)>>8)&0xFF))
|
||||
#define putmem16(x,y,z) writew86(segbase(x)+(uint32_t)y, z)
|
||||
#define signext(value) ((((uint16_t)value&0x80)*0x1FE)|(uint16_t)value)
|
||||
#define signext32(value) ((((uint32_t)value&0x8000)*0x1FFFE)|(uint32_t)value)
|
||||
#define getreg16(regid) regs.wordregs[regid]
|
||||
#define getreg8(regid) regs.byteregs[byteregtable[regid]]
|
||||
#define putreg16(regid, writeval) regs.wordregs[regid] = writeval
|
||||
#define putreg8(regid, writeval) regs.byteregs[byteregtable[regid]] = writeval
|
||||
#define getsegreg(regid) segregs[regid]
|
||||
#define putsegreg(regid, writeval) segregs[regid] = writeval
|
||||
#define segbase(x) ((uint32_t)x<<4)
|
||||
|
||||
#define makeflagsword() (2 | (uint16_t)cf | ((uint16_t)pf << 2) | ((uint16_t)af << 4) | ((uint16_t)zf << 6) \
|
||||
| ((uint16_t)sf << 7) | ((uint16_t)tf << 8) | ((uint16_t)ifl << 9) | ((uint16_t)df << 10) | ((uint16_t)of << 11))
|
||||
|
||||
#define decodeflagsword(x) {\
|
||||
temp16 = x;\
|
||||
cf = temp16 & 1;\
|
||||
pf = (temp16 >> 2) & 1;\
|
||||
af = (temp16 >> 4) & 1;\
|
||||
zf = (temp16 >> 6) & 1;\
|
||||
sf = (temp16 >> 7) & 1;\
|
||||
tf = (temp16 >> 8) & 1;\
|
||||
ifl = (temp16 >> 9) & 1;\
|
||||
df = (temp16 >> 10) & 1;\
|
||||
of = (temp16 >> 11) & 1;\
|
||||
}
|
||||
|
||||
|
||||
|
||||
//#define RAM_write(a,v) {
|
||||
//}
|
||||
|
||||
//#define RAM_read(a,v) {
|
||||
//}
|
||||
|
||||
|
||||
void setup_memory();
|
||||
void setup_timer();
|
||||
uint8_t insertdisk(uint8_t drivenum);
|
||||
void reset86();
|
||||
void exec86(uint32_t execloops);
|
||||
uint8_t read86(uint32_t addr32);
|
||||
void write86(uint32_t addr32, uint8_t value);
|
||||
void doirq(uint8_t irqnum);
|
||||
void incsends();
|
||||
void init_display();
|
||||
void write_video(uint16_t addr);
|
||||
void clear_display();
|
||||
void palettereset();
|
||||
void display_CSIP();
|
||||
void ps2poll();
|
||||
void setup_ps2(uint8_t data_pin, uint8_t irq_pin);
|
||||
void video_init();
|
||||
uint8_t VRAM_read(uint32_t addr32);
|
||||
void VRAM_write(uint32_t addr32, uint8_t value);
|
||||
void setup_ps2(uint8_t data_pin, uint8_t irq_pin);
|
||||
void ps2poll();
|
||||
void out8253 (uint16_t portnum, uint8_t value);
|
||||
uint8_t in8253 (uint16_t portnum);
|
||||
void init8259();
|
||||
void out8259(uint16_t portnum, uint8_t value);
|
||||
uint8_t in8259(uint16_t portnum);
|
||||
|
||||
extern uint8_t port3da;
|
||||
|
||||
void initDisk(char * filename);
|
||||
void init8253();
|
||||
void net_init();
|
||||
void net_loop();
|
||||
void net_handler();
|
||||
uint8_t cached_read(uint32_t addr32);
|
||||
void cached_write(uint32_t addr32, uint8_t value);
|
||||
void cache_init();
|
||||
|
||||
uint8_t net_read_ram(uint32_t addr32);
|
||||
void diskhandler();
|
||||
|
||||
//extern uint8_t SPI_RAM_pins[8];
|
||||
extern uint8_t net_mac[6];
|
||||
extern uint8_t bufSerial[1600];
|
||||
void outByte(uint8_t cc);
|
||||
|
||||
extern struct i8253_s i8253;
|
||||
union _bytewordregs_{
|
||||
uint16_t wordregs[8];
|
||||
uint8_t byteregs[8];
|
||||
} ;
|
||||
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,132 @@
|
|||
#ifndef EMUAPI_H
|
||||
#define EMUAPI_H
|
||||
|
||||
//#define INVX 1
|
||||
//#define INVY 1
|
||||
//#define HAS_SND 1
|
||||
//#define CUSTOM_SND 1
|
||||
#define HAS_I2CKBD 1
|
||||
#define USE_WIRE 1
|
||||
|
||||
|
||||
|
||||
// Title: < >
|
||||
#define TITLE " 8086 Emulator "
|
||||
#define ROMSDIR "pc"
|
||||
|
||||
#define emu_Init(ROM) {mac_Init(); mac_Start(ROM); }
|
||||
#define emu_Step(x) { mac_Step(); }
|
||||
#define emu_Input(x) { mac_Input(x); }
|
||||
|
||||
#define VID_FRAME_SKIP 0x0
|
||||
#define PALETTE_SIZE 256
|
||||
#define SINGLELINE_RENDERING 1
|
||||
#define TFT_VBUFFER_YCROP 0
|
||||
|
||||
#define ACTION_NONE 0
|
||||
#define ACTION_MAXKBDVAL 225
|
||||
#define ACTION_EXITKBD 128
|
||||
#define ACTION_RUNTFT 129
|
||||
|
||||
#ifdef KEYMAP_PRESENT
|
||||
|
||||
#define TAREA_W_DEF 32
|
||||
#define TAREA_H_DEF 32
|
||||
#define TAREA_END 255
|
||||
#define TAREA_NEW_ROW 254
|
||||
#define TAREA_NEW_COL 253
|
||||
#define TAREA_XY 252
|
||||
#define TAREA_WH 251
|
||||
|
||||
#define KEYBOARD_X 16
|
||||
#define KEYBOARD_Y 32
|
||||
#define KEYBOARD_KEY_H 30
|
||||
#define KEYBOARD_KEY_W 28
|
||||
#define KEYBOARD_HIT_COLOR RGBVAL16(0xff,0x00,0x00)
|
||||
|
||||
const unsigned short keysw[]=
|
||||
{ TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18,
|
||||
TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18,
|
||||
TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18,
|
||||
TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18,
|
||||
//TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18,
|
||||
TAREA_END};
|
||||
|
||||
const unsigned short keys[]={
|
||||
'1','2','3','4','5','6','7','8','9',0xFF09,
|
||||
'Q','W','E','R','T','Y','U','I','O','P',
|
||||
'A','S','D','F','G','H','J','K','L', 0xFF0D,
|
||||
'Z','X','C','V','B','N','M',',','.',' ' };
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef HAS_I2CKBD
|
||||
const unsigned short i2ckeys[] = {
|
||||
0X0080,0X0008,0X0180,0X0108,0X0280,0X0208,0X0380,0X0308,0X0480,0X0408,
|
||||
0X0040,0X0004,0X0140,0X0104,0X0240,0X0204,0X0340,0X0304,0X0440,0X0404,
|
||||
0X0020,0X0002,0X0120,0X0102,0X0220,0X0202,0X0320,0X0302,0X0420,0X0402,
|
||||
0X0010,0X0001,0X0110,0X0101,0X0210,0X0201,0X0310,0X0301,0X0410,0X0401 };
|
||||
//0X0580,0X0540,0X0520,0X0510,0X0508,0X0504,0X0502,0X0501,0X0680,0X0640 };
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#define MASK_JOY2_RIGHT 0x0001
|
||||
#define MASK_JOY2_LEFT 0x0002
|
||||
#define MASK_JOY2_UP 0x0004
|
||||
#define MASK_JOY2_DOWN 0x0008
|
||||
#define MASK_JOY2_BTN 0x0010
|
||||
#define MASK_KEY_USER1 0x0020
|
||||
#define MASK_KEY_USER2 0x0040
|
||||
#define MASK_KEY_USER3 0x0080
|
||||
#define MASK_JOY1_RIGHT 0x0100
|
||||
#define MASK_JOY1_LEFT 0x0200
|
||||
#define MASK_JOY1_UP 0x0400
|
||||
#define MASK_JOY1_DOWN 0x0800
|
||||
#define MASK_JOY1_BTN 0x1000
|
||||
#define MASK_KEY_USER4 0x2000
|
||||
|
||||
|
||||
extern void emu_init(void);
|
||||
extern void emu_printf(char * text);
|
||||
extern void emu_printi(int val);
|
||||
extern void * emu_Malloc(int size);
|
||||
extern void emu_Free(void * pt);
|
||||
|
||||
extern int emu_FileOpen(char * filename);
|
||||
extern int emu_FileRead(char * buf, int size);
|
||||
extern unsigned char emu_FileGetc(void);
|
||||
extern int emu_FileSeek(int seek);
|
||||
extern void emu_FileClose(void);
|
||||
extern int emu_FileSize(char * filename);
|
||||
extern int emu_LoadFile(char * filename, char * buf, int size);
|
||||
extern int emu_LoadFileSeek(char * filename, char * buf, int size, int seek);
|
||||
|
||||
extern void emu_InitJoysticks(void);
|
||||
extern int emu_SwapJoysticks(int statusOnly);
|
||||
extern unsigned short emu_DebounceLocalKeys(void);
|
||||
extern int emu_ReadKeys(void);
|
||||
extern int emu_GetPad(void);
|
||||
extern int emu_ReadAnalogJoyX(int min, int max);
|
||||
extern int emu_ReadAnalogJoyY(int min, int max);
|
||||
extern int emu_ReadI2CKeyboard(void);
|
||||
extern int emu_setKeymap(int index);
|
||||
|
||||
extern void emu_sndInit();
|
||||
extern void emu_sndPlaySound(int chan, int volume, int freq);
|
||||
extern void emu_sndPlayBuzz(int size, int val);
|
||||
|
||||
extern void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index);
|
||||
extern void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride);
|
||||
extern void emu_DrawLine(unsigned char * VBuf, int width, int height, int line);
|
||||
extern void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line);
|
||||
extern void emu_DrawVsync(void);
|
||||
extern int emu_FrameSkip(void);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,620 @@
|
|||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
extern "C" {
|
||||
#include "emuapi.h"
|
||||
}
|
||||
#include "emu.h"
|
||||
#include "ps2.h"
|
||||
|
||||
|
||||
|
||||
uint8_t * RAM;
|
||||
uint8_t * LORAM; //LORAM[NATIVE_RAM];
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define PALMULT8(x) ((x)<<5)
|
||||
#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) )
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
|
||||
#include "esp_system.h"
|
||||
|
||||
|
||||
|
||||
struct i8253_s {
|
||||
uint16_t chandata[3];
|
||||
uint8_t accessmode[3];
|
||||
uint8_t bytetoggle[3];
|
||||
uint32_t effectivedata[3];
|
||||
float chanfreq[3];
|
||||
uint8_t active[3];
|
||||
uint16_t counter[3];
|
||||
};
|
||||
|
||||
extern struct i8253_s i8253;
|
||||
|
||||
void doirq(uint8_t irqnum);
|
||||
void write86(uint32_t addr32, uint8_t value);
|
||||
uint8_t read86(uint32_t addr32);
|
||||
|
||||
uint8_t curkey = 0;
|
||||
|
||||
|
||||
|
||||
uint8_t VRAM[16384];
|
||||
|
||||
|
||||
uint32_t updateaddrs[64];
|
||||
uint8_t updatepos = 0;
|
||||
|
||||
void VRAM_write(uint32_t addr32, uint8_t value) {
|
||||
|
||||
if (addr32 < 16384) {
|
||||
VRAM[addr32] = value;
|
||||
|
||||
//printf("%d %d\n",addr32,value);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t VRAM_read(uint32_t addr32) {
|
||||
|
||||
if (addr32 < 16384) return VRAM[addr32];
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8_t ansicolor[16] = { 0, 4, 2, 6, 1, 5, 3, 7, 0, 4, 2, 6, 1, 5, 3, 7 };
|
||||
uint16_t palettecga[16], palettevga[256];
|
||||
|
||||
|
||||
void installPalette(void) {
|
||||
palettecga[0] = RGBVAL16(0, 0, 0);
|
||||
palettecga[1] = RGBVAL16(0, 0, 0xAA);
|
||||
palettecga[2] = RGBVAL16(0, 0xAA, 0);
|
||||
palettecga[3] = RGBVAL16(0, 0xAA, 0xAA);
|
||||
palettecga[4] = RGBVAL16(0xAA, 0, 0);
|
||||
palettecga[5] = RGBVAL16(0xAA, 0, 0xAA);
|
||||
palettecga[6] = RGBVAL16(0xAA, 0x55, 0);
|
||||
palettecga[7] = RGBVAL16(0xAA, 0xAA, 0xAA);
|
||||
palettecga[8] = RGBVAL16(0x55, 0x55, 0x55);
|
||||
palettecga[9] = RGBVAL16(0x55, 0x55, 0xFF);
|
||||
palettecga[10] = RGBVAL16(0x55, 0xFF, 0x55);
|
||||
palettecga[11] = RGBVAL16(0x55, 0xFF, 0xFF);
|
||||
palettecga[12] = RGBVAL16(0xFF, 0x55, 0x55);
|
||||
palettecga[13] = RGBVAL16(0xFF, 0x55, 0xFF);
|
||||
palettecga[14] = RGBVAL16(0xFF, 0xFF, 0x55);
|
||||
palettecga[15] = RGBVAL16(0xFF, 0xFF, 0xFF);
|
||||
palettevga[0] = RGBVAL16(0, 0, 0);
|
||||
palettevga[1] = RGBVAL16(0, 0, 169);
|
||||
palettevga[2] = RGBVAL16(0, 169, 0);
|
||||
palettevga[3] = RGBVAL16(0, 169, 169);
|
||||
palettevga[4] = RGBVAL16(169, 0, 0);
|
||||
palettevga[5] = RGBVAL16(169, 0, 169);
|
||||
palettevga[6] = RGBVAL16(169, 169, 0);
|
||||
palettevga[7] = RGBVAL16(169, 169, 169);
|
||||
palettevga[8] = RGBVAL16(0, 0, 84);
|
||||
palettevga[9] = RGBVAL16(0, 0, 255);
|
||||
palettevga[10] = RGBVAL16(0, 169, 84);
|
||||
palettevga[11] = RGBVAL16(0, 169, 255);
|
||||
palettevga[12] = RGBVAL16(169, 0, 84);
|
||||
palettevga[13] = RGBVAL16(169, 0, 255);
|
||||
palettevga[14] = RGBVAL16(169, 169, 84);
|
||||
palettevga[15] = RGBVAL16(169, 169, 255);
|
||||
palettevga[16] = RGBVAL16(0, 84, 0);
|
||||
palettevga[17] = RGBVAL16(0, 84, 169);
|
||||
palettevga[18] = RGBVAL16(0, 255, 0);
|
||||
palettevga[19] = RGBVAL16(0, 255, 169);
|
||||
palettevga[20] = RGBVAL16(169, 84, 0);
|
||||
palettevga[21] = RGBVAL16(169, 84, 169);
|
||||
palettevga[22] = RGBVAL16(169, 255, 0);
|
||||
palettevga[23] = RGBVAL16(169, 255, 169);
|
||||
palettevga[24] = RGBVAL16(0, 84, 84);
|
||||
palettevga[25] = RGBVAL16(0, 84, 255);
|
||||
palettevga[26] = RGBVAL16(0, 255, 84);
|
||||
palettevga[27] = RGBVAL16(0, 255, 255);
|
||||
palettevga[28] = RGBVAL16(169, 84, 84);
|
||||
palettevga[29] = RGBVAL16(169, 84, 255);
|
||||
palettevga[30] = RGBVAL16(169, 255, 84);
|
||||
palettevga[31] = RGBVAL16(169, 255, 255);
|
||||
palettevga[32] = RGBVAL16(84, 0, 0);
|
||||
palettevga[33] = RGBVAL16(84, 0, 169);
|
||||
palettevga[34] = RGBVAL16(84, 169, 0);
|
||||
palettevga[35] = RGBVAL16(84, 169, 169);
|
||||
palettevga[36] = RGBVAL16(255, 0, 0);
|
||||
palettevga[37] = RGBVAL16(255, 0, 169);
|
||||
palettevga[38] = RGBVAL16(255, 169, 0);
|
||||
palettevga[39] = RGBVAL16(255, 169, 169);
|
||||
palettevga[40] = RGBVAL16(84, 0, 84);
|
||||
palettevga[41] = RGBVAL16(84, 0, 255);
|
||||
palettevga[42] = RGBVAL16(84, 169, 84);
|
||||
palettevga[43] = RGBVAL16(84, 169, 255);
|
||||
palettevga[44] = RGBVAL16(255, 0, 84);
|
||||
palettevga[45] = RGBVAL16(255, 0, 255);
|
||||
palettevga[46] = RGBVAL16(255, 169, 84);
|
||||
palettevga[47] = RGBVAL16(255, 169, 255);
|
||||
palettevga[48] = RGBVAL16(84, 84, 0);
|
||||
palettevga[49] = RGBVAL16(84, 84, 169);
|
||||
palettevga[50] = RGBVAL16(84, 255, 0);
|
||||
palettevga[51] = RGBVAL16(84, 255, 169);
|
||||
palettevga[52] = RGBVAL16(255, 84, 0);
|
||||
palettevga[53] = RGBVAL16(255, 84, 169);
|
||||
palettevga[54] = RGBVAL16(255, 255, 0);
|
||||
palettevga[55] = RGBVAL16(255, 255, 169);
|
||||
palettevga[56] = RGBVAL16(84, 84, 84);
|
||||
palettevga[57] = RGBVAL16(84, 84, 255);
|
||||
palettevga[58] = RGBVAL16(84, 255, 84);
|
||||
palettevga[59] = RGBVAL16(84, 255, 255);
|
||||
palettevga[60] = RGBVAL16(255, 84, 84);
|
||||
palettevga[61] = RGBVAL16(255, 84, 255);
|
||||
palettevga[62] = RGBVAL16(255, 255, 84);
|
||||
palettevga[63] = RGBVAL16(255, 255, 255);
|
||||
palettevga[64] = RGBVAL16(255, 125, 125);
|
||||
palettevga[65] = RGBVAL16(255, 157, 125);
|
||||
palettevga[66] = RGBVAL16(255, 190, 125);
|
||||
palettevga[67] = RGBVAL16(255, 222, 125);
|
||||
palettevga[68] = RGBVAL16(255, 255, 125);
|
||||
palettevga[69] = RGBVAL16(222, 255, 125);
|
||||
palettevga[70] = RGBVAL16(190, 255, 125);
|
||||
palettevga[71] = RGBVAL16(157, 255, 125);
|
||||
palettevga[72] = RGBVAL16(125, 255, 125);
|
||||
palettevga[73] = RGBVAL16(125, 255, 157);
|
||||
palettevga[74] = RGBVAL16(125, 255, 190);
|
||||
palettevga[75] = RGBVAL16(125, 255, 222);
|
||||
palettevga[76] = RGBVAL16(125, 255, 255);
|
||||
palettevga[77] = RGBVAL16(125, 222, 255);
|
||||
palettevga[78] = RGBVAL16(125, 190, 255);
|
||||
palettevga[79] = RGBVAL16(125, 157, 255);
|
||||
palettevga[80] = RGBVAL16(182, 182, 255);
|
||||
palettevga[81] = RGBVAL16(198, 182, 255);
|
||||
palettevga[82] = RGBVAL16(218, 182, 255);
|
||||
palettevga[83] = RGBVAL16(234, 182, 255);
|
||||
palettevga[84] = RGBVAL16(255, 182, 255);
|
||||
palettevga[85] = RGBVAL16(255, 182, 234);
|
||||
palettevga[86] = RGBVAL16(255, 182, 218);
|
||||
palettevga[87] = RGBVAL16(255, 182, 198);
|
||||
palettevga[88] = RGBVAL16(255, 182, 182);
|
||||
palettevga[89] = RGBVAL16(255, 198, 182);
|
||||
palettevga[90] = RGBVAL16(255, 218, 182);
|
||||
palettevga[91] = RGBVAL16(255, 234, 182);
|
||||
palettevga[92] = RGBVAL16(255, 255, 182);
|
||||
palettevga[93] = RGBVAL16(234, 255, 182);
|
||||
palettevga[94] = RGBVAL16(218, 255, 182);
|
||||
palettevga[95] = RGBVAL16(198, 255, 182);
|
||||
palettevga[96] = RGBVAL16(182, 255, 182);
|
||||
palettevga[97] = RGBVAL16(182, 255, 198);
|
||||
palettevga[98] = RGBVAL16(182, 255, 218);
|
||||
palettevga[99] = RGBVAL16(182, 255, 234);
|
||||
palettevga[100] = RGBVAL16(182, 255, 255);
|
||||
palettevga[101] = RGBVAL16(182, 234, 255);
|
||||
palettevga[102] = RGBVAL16(182, 218, 255);
|
||||
palettevga[103] = RGBVAL16(182, 198, 255);
|
||||
palettevga[104] = RGBVAL16(0, 0, 113);
|
||||
palettevga[105] = RGBVAL16(28, 0, 113);
|
||||
palettevga[106] = RGBVAL16(56, 0, 113);
|
||||
palettevga[107] = RGBVAL16(84, 0, 113);
|
||||
palettevga[108] = RGBVAL16(113, 0, 113);
|
||||
palettevga[109] = RGBVAL16(113, 0, 84);
|
||||
palettevga[110] = RGBVAL16(113, 0, 56);
|
||||
palettevga[111] = RGBVAL16(113, 0, 28);
|
||||
palettevga[112] = RGBVAL16(113, 0, 0);
|
||||
palettevga[113] = RGBVAL16(113, 28, 0);
|
||||
palettevga[114] = RGBVAL16(113, 56, 0);
|
||||
palettevga[115] = RGBVAL16(113, 84, 0);
|
||||
palettevga[116] = RGBVAL16(113, 113, 0);
|
||||
palettevga[117] = RGBVAL16(84, 113, 0);
|
||||
palettevga[118] = RGBVAL16(56, 113, 0);
|
||||
palettevga[119] = RGBVAL16(28, 113, 0);
|
||||
palettevga[120] = RGBVAL16(0, 113, 0);
|
||||
palettevga[121] = RGBVAL16(0, 113, 28);
|
||||
palettevga[122] = RGBVAL16(0, 113, 56);
|
||||
palettevga[123] = RGBVAL16(0, 113, 84);
|
||||
palettevga[124] = RGBVAL16(0, 113, 113);
|
||||
palettevga[125] = RGBVAL16(0, 84, 113);
|
||||
palettevga[126] = RGBVAL16(0, 56, 113);
|
||||
palettevga[127] = RGBVAL16(0, 28, 113);
|
||||
palettevga[128] = RGBVAL16(56, 56, 113);
|
||||
palettevga[129] = RGBVAL16(68, 56, 113);
|
||||
palettevga[130] = RGBVAL16(84, 56, 113);
|
||||
palettevga[131] = RGBVAL16(97, 56, 113);
|
||||
palettevga[132] = RGBVAL16(113, 56, 113);
|
||||
palettevga[133] = RGBVAL16(113, 56, 97);
|
||||
palettevga[134] = RGBVAL16(113, 56, 84);
|
||||
palettevga[135] = RGBVAL16(113, 56, 68);
|
||||
palettevga[136] = RGBVAL16(113, 56, 56);
|
||||
palettevga[137] = RGBVAL16(113, 68, 56);
|
||||
palettevga[138] = RGBVAL16(113, 84, 56);
|
||||
palettevga[139] = RGBVAL16(113, 97, 56);
|
||||
palettevga[140] = RGBVAL16(113, 113, 56);
|
||||
palettevga[141] = RGBVAL16(97, 113, 56);
|
||||
palettevga[142] = RGBVAL16(84, 113, 56);
|
||||
palettevga[143] = RGBVAL16(68, 113, 56);
|
||||
palettevga[144] = RGBVAL16(56, 113, 56);
|
||||
palettevga[145] = RGBVAL16(56, 113, 68);
|
||||
palettevga[146] = RGBVAL16(56, 113, 84);
|
||||
palettevga[147] = RGBVAL16(56, 113, 97);
|
||||
palettevga[148] = RGBVAL16(56, 113, 113);
|
||||
palettevga[149] = RGBVAL16(56, 97, 113);
|
||||
palettevga[150] = RGBVAL16(56, 84, 113);
|
||||
palettevga[151] = RGBVAL16(56, 68, 113);
|
||||
palettevga[152] = RGBVAL16(80, 80, 113);
|
||||
palettevga[153] = RGBVAL16(89, 80, 113);
|
||||
palettevga[154] = RGBVAL16(97, 80, 113);
|
||||
palettevga[155] = RGBVAL16(105, 80, 113);
|
||||
palettevga[156] = RGBVAL16(113, 80, 113);
|
||||
palettevga[157] = RGBVAL16(113, 80, 105);
|
||||
palettevga[158] = RGBVAL16(113, 80, 97);
|
||||
palettevga[159] = RGBVAL16(113, 80, 89);
|
||||
palettevga[160] = RGBVAL16(113, 80, 80);
|
||||
palettevga[161] = RGBVAL16(113, 89, 80);
|
||||
palettevga[162] = RGBVAL16(113, 97, 80);
|
||||
palettevga[163] = RGBVAL16(113, 105, 80);
|
||||
palettevga[164] = RGBVAL16(113, 113, 80);
|
||||
palettevga[165] = RGBVAL16(105, 113, 80);
|
||||
palettevga[166] = RGBVAL16(97, 113, 80);
|
||||
palettevga[167] = RGBVAL16(89, 113, 80);
|
||||
palettevga[168] = RGBVAL16(80, 113, 80);
|
||||
palettevga[169] = RGBVAL16(80, 113, 89);
|
||||
palettevga[170] = RGBVAL16(80, 113, 97);
|
||||
palettevga[171] = RGBVAL16(80, 113, 105);
|
||||
palettevga[172] = RGBVAL16(80, 113, 113);
|
||||
palettevga[173] = RGBVAL16(80, 105, 113);
|
||||
palettevga[174] = RGBVAL16(80, 97, 113);
|
||||
palettevga[175] = RGBVAL16(80, 89, 113);
|
||||
palettevga[176] = RGBVAL16(0, 0, 64);
|
||||
palettevga[177] = RGBVAL16(16, 0, 64);
|
||||
palettevga[178] = RGBVAL16(32, 0, 64);
|
||||
palettevga[179] = RGBVAL16(48, 0, 64);
|
||||
palettevga[180] = RGBVAL16(64, 0, 64);
|
||||
palettevga[181] = RGBVAL16(64, 0, 48);
|
||||
palettevga[182] = RGBVAL16(64, 0, 32);
|
||||
palettevga[183] = RGBVAL16(64, 0, 16);
|
||||
palettevga[184] = RGBVAL16(64, 0, 0);
|
||||
palettevga[185] = RGBVAL16(64, 16, 0);
|
||||
palettevga[186] = RGBVAL16(64, 32, 0);
|
||||
palettevga[187] = RGBVAL16(64, 48, 0);
|
||||
palettevga[188] = RGBVAL16(64, 64, 0);
|
||||
palettevga[189] = RGBVAL16(48, 64, 0);
|
||||
palettevga[190] = RGBVAL16(32, 64, 0);
|
||||
palettevga[191] = RGBVAL16(16, 64, 0);
|
||||
palettevga[192] = RGBVAL16(0, 64, 0);
|
||||
palettevga[193] = RGBVAL16(0, 64, 16);
|
||||
palettevga[194] = RGBVAL16(0, 64, 32);
|
||||
palettevga[195] = RGBVAL16(0, 64, 48);
|
||||
palettevga[196] = RGBVAL16(0, 64, 64);
|
||||
palettevga[197] = RGBVAL16(0, 48, 64);
|
||||
palettevga[198] = RGBVAL16(0, 32, 64);
|
||||
palettevga[199] = RGBVAL16(0, 16, 64);
|
||||
palettevga[200] = RGBVAL16(32, 32, 64);
|
||||
palettevga[201] = RGBVAL16(40, 32, 64);
|
||||
palettevga[202] = RGBVAL16(48, 32, 64);
|
||||
palettevga[203] = RGBVAL16(56, 32, 64);
|
||||
palettevga[204] = RGBVAL16(64, 32, 64);
|
||||
palettevga[205] = RGBVAL16(64, 32, 56);
|
||||
palettevga[206] = RGBVAL16(64, 32, 48);
|
||||
palettevga[207] = RGBVAL16(64, 32, 40);
|
||||
palettevga[208] = RGBVAL16(64, 32, 32);
|
||||
palettevga[209] = RGBVAL16(64, 40, 32);
|
||||
palettevga[210] = RGBVAL16(64, 48, 32);
|
||||
palettevga[211] = RGBVAL16(64, 56, 32);
|
||||
palettevga[212] = RGBVAL16(64, 64, 32);
|
||||
palettevga[213] = RGBVAL16(56, 64, 32);
|
||||
palettevga[214] = RGBVAL16(48, 64, 32);
|
||||
palettevga[215] = RGBVAL16(40, 64, 32);
|
||||
palettevga[216] = RGBVAL16(32, 64, 32);
|
||||
palettevga[217] = RGBVAL16(32, 64, 40);
|
||||
palettevga[218] = RGBVAL16(32, 64, 48);
|
||||
palettevga[219] = RGBVAL16(32, 64, 56);
|
||||
palettevga[220] = RGBVAL16(32, 64, 64);
|
||||
palettevga[221] = RGBVAL16(32, 56, 64);
|
||||
palettevga[222] = RGBVAL16(32, 48, 64);
|
||||
palettevga[223] = RGBVAL16(32, 40, 64);
|
||||
palettevga[224] = RGBVAL16(44, 44, 64);
|
||||
palettevga[225] = RGBVAL16(48, 44, 64);
|
||||
palettevga[226] = RGBVAL16(52, 44, 64);
|
||||
palettevga[227] = RGBVAL16(60, 44, 64);
|
||||
palettevga[228] = RGBVAL16(64, 44, 64);
|
||||
palettevga[229] = RGBVAL16(64, 44, 60);
|
||||
palettevga[230] = RGBVAL16(64, 44, 52);
|
||||
palettevga[231] = RGBVAL16(64, 44, 48);
|
||||
palettevga[232] = RGBVAL16(64, 44, 44);
|
||||
palettevga[233] = RGBVAL16(64, 48, 44);
|
||||
palettevga[234] = RGBVAL16(64, 52, 44);
|
||||
palettevga[235] = RGBVAL16(64, 60, 44);
|
||||
palettevga[236] = RGBVAL16(64, 64, 44);
|
||||
palettevga[237] = RGBVAL16(60, 64, 44);
|
||||
palettevga[238] = RGBVAL16(52, 64, 44);
|
||||
palettevga[239] = RGBVAL16(48, 64, 44);
|
||||
palettevga[240] = RGBVAL16(44, 64, 44);
|
||||
palettevga[241] = RGBVAL16(44, 64, 48);
|
||||
palettevga[242] = RGBVAL16(44, 64, 52);
|
||||
palettevga[243] = RGBVAL16(44, 64, 60);
|
||||
palettevga[244] = RGBVAL16(44, 64, 64);
|
||||
palettevga[245] = RGBVAL16(44, 60, 64);
|
||||
palettevga[246] = RGBVAL16(44, 52, 64);
|
||||
palettevga[247] = RGBVAL16(44, 48, 64);
|
||||
palettevga[248] = RGBVAL16(0, 0, 0);
|
||||
palettevga[249] = RGBVAL16(0, 0, 0);
|
||||
palettevga[250] = RGBVAL16(0, 0, 0);
|
||||
palettevga[251] = RGBVAL16(0, 0, 0);
|
||||
palettevga[252] = RGBVAL16(0, 0, 0);
|
||||
palettevga[253] = RGBVAL16(0, 0, 0);
|
||||
palettevga[254] = RGBVAL16(0, 0, 0);
|
||||
palettevga[255] = RGBVAL16(0, 0, 0);
|
||||
}
|
||||
|
||||
extern uint8_t vidmode, portram[0x400];
|
||||
|
||||
|
||||
|
||||
#include "font.h"
|
||||
|
||||
|
||||
static unsigned short line[320];
|
||||
|
||||
|
||||
void drawscreentext80(void) {
|
||||
uint16_t row, col, y, x, xpos;
|
||||
uint16_t fontdata;
|
||||
|
||||
for (y=0; y<(25*8); y++)
|
||||
{
|
||||
row = y>>3;
|
||||
uint8_t * vrampt=&VRAM[160*row];
|
||||
xpos = 0;
|
||||
for (col=0; col<80; col++)
|
||||
{
|
||||
uint8_t bold, attrib, cc, bg, fg;
|
||||
cc = *vrampt++;
|
||||
attrib = *vrampt++;
|
||||
bg = (attrib >> 4) & 7;
|
||||
fg = attrib & 0x0F;
|
||||
//if (y == 0) {printf("0x%02X",cc);}
|
||||
fontdata = ROM_READ(font, ((uint32_t)cc << 3) + (y&0x7));
|
||||
for (x=0; x<4; x++)
|
||||
{
|
||||
if (fontdata & 1) {
|
||||
line[xpos++] = palettecga[fg];
|
||||
//tft.drawPixel(realx++, realy, palettecga[fg]);
|
||||
} else {
|
||||
line[xpos++] = palettecga[bg];
|
||||
//tft.drawPixel(realx++, realy, palettecga[bg]);
|
||||
}
|
||||
fontdata >>= 2;
|
||||
}
|
||||
}
|
||||
//if (y == 0) {printf("\n");}
|
||||
|
||||
emu_DrawLine16(&line[0], 320, 200, y);
|
||||
}
|
||||
}
|
||||
|
||||
void drawscreenlorescga(void) {
|
||||
//uint16_t row;
|
||||
uint16_t y, x, xpos;
|
||||
uint8_t intensity, usepal;
|
||||
uint16_t color;
|
||||
usepal = (portram[0x3D9]>>5) & 1;
|
||||
intensity = ( (portram[0x3D9]>>4) & 1) << 3;
|
||||
|
||||
for (y=0; y<(25*8); y++)
|
||||
{
|
||||
//row = y>>3;
|
||||
//uint8_t * vrampt=&VRAM[160*row];
|
||||
xpos = 0;
|
||||
for (x=0; x<320; x++)
|
||||
{
|
||||
int ychar = y;// >> 1;
|
||||
int xchar = x;// >> 1;
|
||||
uint8_t curchar = VRAM[((ychar & 1) * 8192 + (ychar >> 1) * 80 + (xchar >> 2))];
|
||||
switch (xchar & 3) {
|
||||
case 3: color = curchar & 3; break;
|
||||
case 2: color = (curchar >> 2) & 3; break;
|
||||
case 1: color = (curchar >> 4) & 3; break;
|
||||
case 0: color = (curchar >> 6) & 3; break;
|
||||
}
|
||||
color = (color << 1) + usepal + intensity;
|
||||
if (color == (usepal + intensity)) color = 0;
|
||||
line[xpos++] = palettecga[color];
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
for (col=0; col<80; col++)
|
||||
{
|
||||
uint8_t value = *vrampt++;
|
||||
for (i=0; i<4; i++)
|
||||
{
|
||||
uint8_t packedcolor;
|
||||
packedcolor = value >> 6;
|
||||
if (!packedcolor) color = 0; else color = packedcolor * 2 + usepal + intensity;
|
||||
line[xpos++] = palettecga[color];
|
||||
value <<= 2;
|
||||
}
|
||||
}
|
||||
*/
|
||||
//if (y == 0) {printf("\n");}
|
||||
|
||||
emu_DrawLine16(&line[0], 320, 200, y);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void drawscreenhirescga(void) {
|
||||
uint16_t y, x, xpos;
|
||||
uint16_t color;
|
||||
for (y=0; y<(25*8); y++)
|
||||
{
|
||||
xpos = 0;
|
||||
for (x=0; x<320; x++)
|
||||
{
|
||||
int ychar = y >> 1;
|
||||
int xchar = x;
|
||||
uint8_t curchar = VRAM[((ychar & 1) * 8192 + (ychar >> 1) * 80 + (xchar >> 3))];
|
||||
color = ((curchar >> (7-(x&7))) & 1) ? 15 : 0;
|
||||
line[xpos++] = palettecga[color];
|
||||
}
|
||||
|
||||
emu_DrawLine16(&line[0], 320, 200, y);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void updatescreen() {
|
||||
switch (vidmode & 0x7F) {
|
||||
case 0:
|
||||
case 1:
|
||||
//drawtext40(origaddr, value);
|
||||
break;
|
||||
case 2:
|
||||
case 3:
|
||||
//case 7:
|
||||
drawscreentext80();
|
||||
break;
|
||||
case 4:
|
||||
drawscreenlorescga();
|
||||
break;
|
||||
case 5:
|
||||
drawscreenlorescga(); //change to BW function later
|
||||
break;
|
||||
case 6:
|
||||
drawscreenhirescga();
|
||||
break;
|
||||
}
|
||||
//printf("%d\n",vidmode & 0x7F);
|
||||
}
|
||||
|
||||
|
||||
void mac_Init(void)
|
||||
{
|
||||
RAM = (uint8_t*) heap_caps_malloc(RAM_SIZE,MALLOC_CAP_SPIRAM); //malloc (MEMSIZE);
|
||||
if (!RAM)printf("SPI RAM malloc failed\n");
|
||||
|
||||
LORAM = (uint8_t*)malloc(NATIVE_RAM);
|
||||
if (!LORAM)printf("LORAM malloc failed\n");
|
||||
|
||||
|
||||
installPalette();
|
||||
init8253();
|
||||
reset86();
|
||||
init8259();
|
||||
}
|
||||
|
||||
|
||||
static uint8_t nbkeys=0;
|
||||
static uint8_t kcnt=0;
|
||||
static int toggle=1;
|
||||
|
||||
//static char * seq="DIR\r";
|
||||
static char * seq="CAT.EXE\r";
|
||||
//static char * seq="PRINCE.BAT\r";
|
||||
|
||||
|
||||
static int hk=0;
|
||||
static int k=0;
|
||||
static bool isMouse = true;
|
||||
static int prev_key = 0;
|
||||
static int prev_j = 0;
|
||||
|
||||
static void keyevent(int keysym, int isdown)
|
||||
{
|
||||
uint8_t scancode = translatescancode(keysym);
|
||||
if (scancode != 0xFF) {
|
||||
portram[0x60] = scancode;
|
||||
if (!isdown) portram[0x60] |= 0x80;
|
||||
portram[0x64] |= 2;
|
||||
doirq(1);
|
||||
vTaskDelay(50 / portTICK_PERIOD_MS);
|
||||
}
|
||||
}
|
||||
|
||||
void mac_Input(int bClick)
|
||||
{
|
||||
hk = emu_ReadI2CKeyboard();
|
||||
k = emu_ReadKeys();
|
||||
|
||||
if (nbkeys == 0) {
|
||||
if (bClick & MASK_JOY2_BTN) {
|
||||
nbkeys = strlen(seq);
|
||||
kcnt=0;
|
||||
}
|
||||
}
|
||||
else {
|
||||
char k = seq[kcnt];
|
||||
if (k == 13) keyevent(0xFF0D,toggle);
|
||||
else keyevent(k,toggle);
|
||||
//setKey(ascii2scan[k],toggle);
|
||||
if (!toggle) {
|
||||
kcnt++;
|
||||
nbkeys--;
|
||||
toggle = true;
|
||||
}
|
||||
else {
|
||||
toggle = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void mac_Step(void)
|
||||
{
|
||||
exec86(8000);
|
||||
updatescreen();
|
||||
|
||||
//hk = emu_ReadI2CKeyboard();
|
||||
if ( (hk != 0) && (hk != prev_key) ) {
|
||||
printf("press %d\n", hk);
|
||||
prev_key = hk;
|
||||
keyevent ( hk, 0 );
|
||||
} else{
|
||||
if (prev_key) {
|
||||
printf("release %d\n", prev_key);
|
||||
keyevent ( prev_key, 1 );
|
||||
prev_key = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int j = 0;
|
||||
if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) {
|
||||
j |= 0x08;
|
||||
}
|
||||
if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) {
|
||||
j |= 0x04;
|
||||
}
|
||||
if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) {
|
||||
j |= 0x01;
|
||||
}
|
||||
if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) {
|
||||
j |= 0x02;
|
||||
}
|
||||
if ( k & MASK_JOY2_BTN) {
|
||||
printf("fire\n");
|
||||
j |= 0x80;
|
||||
}
|
||||
//if (j != prev_j) IkbdJoystickChange(joynum,j);
|
||||
prev_j = j;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
void mac_Start(char * filename)
|
||||
{
|
||||
initDisk(filename);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
extern void mac_Init(void);
|
||||
extern void mac_Step(void);
|
||||
extern void mac_Start(char * filename);
|
||||
extern void mac_Input(int bClick);
|
||||
|
|
@ -0,0 +1,263 @@
|
|||
#ifdef MEGA
|
||||
const uint8_t font[2048] PROGMEM = {
|
||||
#else
|
||||
const uint8_t font[2048] = {
|
||||
#endif
|
||||
0,0,0,0,0,0,0,
|
||||
0,126,129,165,129,189,153,129,
|
||||
126,126,255,219,255,195,231,255,
|
||||
126,54,127,127,127,62,28,8,
|
||||
0,8,28,62,127,62,28,8,
|
||||
0,28,62,28,127,127,62,28,
|
||||
62,8,8,28,62,127,62,28,
|
||||
62,0,0,0,0,0,0,0,
|
||||
0,255,255,231,195,195,231,255,
|
||||
255,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,
|
||||
0,254,198,254,198,198,230,103,
|
||||
3,153,90,60,231,231,60,90,
|
||||
153,1,7,31,127,31,7,1,
|
||||
0,64,112,124,127,124,112,64,
|
||||
0,24,60,126,24,24,126,60,
|
||||
24,102,102,102,102,102,0,102,
|
||||
0,254,219,219,222,216,216,216,
|
||||
0,124,198,28,54,54,28,51,
|
||||
30,0,0,0,0,126,126,126,
|
||||
0,24,60,126,24,126,60,24,
|
||||
255,24,60,126,24,24,24,24,
|
||||
0,24,24,24,24,126,60,24,
|
||||
0,0,24,48,127,48,24,0,
|
||||
0,0,12,6,127,6,12,0,
|
||||
0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,
|
||||
0,12,30,30,12,12,0,12,
|
||||
0,54,54,54,0,0,0,0,
|
||||
0,54,54,127,54,127,54,54,
|
||||
0,12,62,3,30,48,31,12,
|
||||
0,0,99,51,24,12,102,99,
|
||||
0,28,54,28,110,59,51,110,
|
||||
0,6,6,3,0,0,0,0,
|
||||
0,24,12,6,6,6,12,24,
|
||||
0,6,12,24,24,24,12,6,
|
||||
0,0,102,60,255,60,102,0,
|
||||
0,0,12,12,63,12,12,0,
|
||||
0,0,0,0,0,0,12,12,
|
||||
6,0,0,0,63,0,0,0,
|
||||
0,0,0,0,0,0,12,12,
|
||||
0,96,48,24,12,6,3,1,
|
||||
0,62,99,115,123,111,103,62,
|
||||
0,12,14,12,12,12,12,63,
|
||||
0,30,51,48,28,6,51,63,
|
||||
0,30,51,48,28,48,51,30,
|
||||
0,56,60,54,51,127,48,120,
|
||||
0,63,3,31,48,48,51,30,
|
||||
0,28,6,3,31,51,51,30,
|
||||
0,63,51,48,24,12,12,12,
|
||||
0,30,51,51,30,51,51,30,
|
||||
0,30,51,51,62,48,24,14,
|
||||
0,0,12,12,0,0,12,12,
|
||||
0,0,12,12,0,0,12,12,
|
||||
6,24,12,6,3,6,12,24,
|
||||
0,0,0,63,0,0,63,0,
|
||||
0,6,12,24,48,24,12,6,
|
||||
0,30,51,48,24,12,0,12,
|
||||
0,62,99,123,123,123,3,30,
|
||||
0,12,30,51,51,63,51,51,
|
||||
0,63,102,102,62,102,102,63,
|
||||
0,60,102,3,3,3,102,60,
|
||||
0,31,54,102,102,102,54,31,
|
||||
0,127,70,22,30,22,70,127,
|
||||
0,127,70,22,30,22,6,15,
|
||||
0,60,102,3,3,115,102,124,
|
||||
0,51,51,51,63,51,51,51,
|
||||
0,30,12,12,12,12,12,30,
|
||||
0,120,48,48,48,51,51,30,
|
||||
0,103,102,54,30,54,102,103,
|
||||
0,15,6,6,6,70,102,127,
|
||||
0,99,119,127,127,107,99,99,
|
||||
0,99,103,111,123,115,99,99,
|
||||
0,28,54,99,99,99,54,28,
|
||||
0,63,102,102,62,6,6,15,
|
||||
0,30,51,51,51,59,30,56,
|
||||
0,63,102,102,62,54,102,103,
|
||||
0,30,51,7,14,56,51,30,
|
||||
0,63,45,12,12,12,12,30,
|
||||
0,51,51,51,51,51,51,63,
|
||||
0,51,51,51,51,51,30,12,
|
||||
0,99,99,99,107,127,119,99,
|
||||
0,99,99,54,28,28,54,99,
|
||||
0,51,51,51,30,12,12,30,
|
||||
0,127,99,49,24,76,102,127,
|
||||
0,30,6,6,6,6,6,30,
|
||||
0,3,6,12,24,48,96,64,
|
||||
0,30,24,24,24,24,24,30,
|
||||
0,8,28,54,99,0,0,0,
|
||||
0,0,0,0,0,0,0,0,
|
||||
255,12,12,24,0,0,0,0,
|
||||
0,0,0,30,48,62,51,110,
|
||||
0,7,6,6,62,102,102,59,
|
||||
0,0,0,30,51,3,51,30,
|
||||
0,56,48,48,62,51,51,110,
|
||||
0,0,0,30,51,63,3,30,
|
||||
0,28,54,6,15,6,6,15,
|
||||
0,0,0,110,51,51,62,48,
|
||||
31,7,6,54,110,102,102,103,
|
||||
0,12,0,14,12,12,12,30,
|
||||
0,48,0,48,48,48,51,51,
|
||||
30,7,6,102,54,30,54,103,
|
||||
0,14,12,12,12,12,12,30,
|
||||
0,0,0,51,127,127,107,99,
|
||||
0,0,0,31,51,51,51,51,
|
||||
0,0,0,30,51,51,51,30,
|
||||
0,0,0,59,102,102,62,6,
|
||||
15,0,0,110,51,51,62,48,
|
||||
120,0,0,59,110,102,6,15,
|
||||
0,0,0,62,3,30,48,31,
|
||||
0,8,12,62,12,12,44,24,
|
||||
0,0,0,51,51,51,51,110,
|
||||
0,0,0,51,51,51,30,12,
|
||||
0,0,0,99,107,127,127,54,
|
||||
0,0,0,99,54,28,54,99,
|
||||
0,0,0,51,51,51,62,48,
|
||||
31,0,0,63,25,12,38,63,
|
||||
0,56,12,12,7,12,12,56,
|
||||
0,24,24,24,0,24,24,24,
|
||||
0,7,12,12,56,12,12,7,
|
||||
0,110,59,0,0,0,0,0,
|
||||
0,0,8,28,54,99,99,127,
|
||||
0,30,51,3,51,30,24,48,
|
||||
30,0,51,0,51,51,51,126,
|
||||
0,56,0,30,51,63,3,30,
|
||||
0,126,195,60,96,124,102,252,
|
||||
0,51,0,30,48,62,51,126,
|
||||
0,7,0,30,48,62,51,126,
|
||||
0,12,12,30,48,62,51,126,
|
||||
0,0,0,30,3,3,30,48,
|
||||
28,126,195,60,102,126,6,60,
|
||||
0,51,0,30,51,63,3,30,
|
||||
0,7,0,30,51,63,3,30,
|
||||
0,51,0,14,12,12,12,30,
|
||||
0,62,99,28,24,24,24,60,
|
||||
0,7,0,14,12,12,12,30,
|
||||
0,99,28,54,99,127,99,99,
|
||||
0,12,12,0,30,51,63,51,
|
||||
0,56,0,63,6,30,6,63,
|
||||
0,0,0,254,48,254,51,254,
|
||||
0,124,54,51,127,51,51,115,
|
||||
0,30,51,0,30,51,51,30,
|
||||
0,0,51,0,30,51,51,30,
|
||||
0,0,7,0,30,51,51,30,
|
||||
0,30,51,0,51,51,51,126,
|
||||
0,0,7,0,51,51,51,126,
|
||||
0,0,51,0,51,51,62,48,
|
||||
31,195,24,60,102,102,60,24,
|
||||
0,51,0,51,51,51,51,30,
|
||||
0,24,24,126,3,3,126,24,
|
||||
24,28,54,38,15,6,103,63,
|
||||
0,51,51,30,63,12,63,12,
|
||||
12,31,51,51,95,99,243,99,
|
||||
227,112,216,24,60,24,24,27,
|
||||
14,56,0,30,48,62,51,126,
|
||||
0,28,0,14,12,12,12,30,
|
||||
0,0,56,0,30,51,51,30,
|
||||
0,0,56,0,51,51,51,126,
|
||||
0,0,31,0,31,51,51,51,
|
||||
0,63,0,51,55,63,59,51,
|
||||
0,60,54,54,124,0,126,0,
|
||||
0,28,54,54,28,0,62,0,
|
||||
0,12,0,12,6,3,51,30,
|
||||
0,0,0,0,63,3,3,0,
|
||||
0,0,0,0,63,48,48,0,
|
||||
0,195,99,51,123,204,102,51,
|
||||
240,195,99,51,219,236,246,243,
|
||||
192,24,24,0,24,24,24,24,
|
||||
0,0,204,102,51,102,204,0,
|
||||
0,0,51,102,204,102,51,0,
|
||||
0,68,17,68,17,68,17,68,
|
||||
17,170,85,170,85,170,85,170,
|
||||
85,219,238,219,119,219,238,219,
|
||||
119,24,24,24,24,24,24,24,
|
||||
24,24,24,24,24,31,24,24,
|
||||
24,24,24,31,24,31,24,24,
|
||||
24,108,108,108,108,111,108,108,
|
||||
108,0,0,0,0,127,108,108,
|
||||
108,0,0,31,24,31,24,24,
|
||||
24,108,108,111,96,111,108,108,
|
||||
108,108,108,108,108,108,108,108,
|
||||
108,0,0,127,96,111,108,108,
|
||||
108,108,108,111,96,127,0,0,
|
||||
0,108,108,108,108,127,0,0,
|
||||
0,24,24,31,24,31,0,0,
|
||||
0,0,0,0,0,31,24,24,
|
||||
24,24,24,24,24,248,0,0,
|
||||
0,24,24,24,24,255,0,0,
|
||||
0,0,0,0,0,255,24,24,
|
||||
24,24,24,24,24,248,24,24,
|
||||
24,0,0,0,0,255,0,0,
|
||||
0,24,24,24,24,255,24,24,
|
||||
24,24,24,248,24,248,24,24,
|
||||
24,108,108,108,108,236,108,108,
|
||||
108,108,108,236,12,252,0,0,
|
||||
0,0,0,252,12,236,108,108,
|
||||
108,108,108,239,0,255,0,0,
|
||||
0,0,0,255,0,239,108,108,
|
||||
108,108,108,236,12,236,108,108,
|
||||
108,0,0,255,0,255,0,0,
|
||||
0,108,108,239,0,239,108,108,
|
||||
108,24,24,255,0,255,0,0,
|
||||
0,108,108,108,108,255,0,0,
|
||||
0,0,0,255,0,255,24,24,
|
||||
24,0,0,0,0,255,108,108,
|
||||
108,108,108,108,108,252,0,0,
|
||||
0,24,24,248,24,248,0,0,
|
||||
0,0,0,248,24,248,24,24,
|
||||
24,0,0,0,0,252,108,108,
|
||||
108,108,108,108,108,255,108,108,
|
||||
108,24,24,255,24,255,24,24,
|
||||
24,24,24,24,24,31,0,0,
|
||||
0,0,0,0,0,248,24,24,
|
||||
24,255,255,255,255,255,255,255,
|
||||
255,0,0,0,0,255,255,255,
|
||||
255,15,15,15,15,15,15,15,
|
||||
15,240,240,240,240,240,240,240,
|
||||
240,255,255,255,255,0,0,0,
|
||||
0,0,0,110,59,19,59,110,
|
||||
0,0,30,51,31,51,31,3,
|
||||
3,0,63,51,3,3,3,3,
|
||||
0,0,127,54,54,54,54,54,
|
||||
0,63,51,6,12,6,51,63,
|
||||
0,0,0,126,27,27,27,14,
|
||||
0,0,102,102,102,102,62,6,
|
||||
3,0,110,59,24,24,24,24,
|
||||
0,63,12,30,51,51,30,12,
|
||||
63,28,54,99,127,99,54,28,
|
||||
0,28,54,99,99,54,54,119,
|
||||
0,56,12,24,62,51,51,30,
|
||||
0,0,0,126,219,219,126,0,
|
||||
0,96,48,126,219,219,126,6,
|
||||
3,28,6,3,31,3,6,28,
|
||||
0,30,51,51,51,51,51,51,
|
||||
0,0,63,0,63,0,63,0,
|
||||
0,12,12,63,12,12,0,63,
|
||||
0,6,12,24,12,6,0,63,
|
||||
0,24,12,6,12,24,0,63,
|
||||
0,112,216,216,24,24,24,24,
|
||||
24,24,24,24,24,24,27,27,
|
||||
14,12,12,0,63,0,12,12,
|
||||
0,0,110,59,0,110,59,0,
|
||||
0,28,54,54,28,0,0,0,
|
||||
0,0,0,0,24,24,0,0,
|
||||
0,0,0,0,0,24,0,0,
|
||||
0,240,48,48,48,55,54,60,
|
||||
56,30,54,54,54,54,0,0,
|
||||
0,14,24,12,6,30,0,0,
|
||||
0,0,0,60,60,60,60,0,
|
||||
0,0,0,0,0,0,0,0,0
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
|
||||
// Font: c64_lower.64c
|
||||
|
||||
const unsigned char font8x8[128][8] =
|
||||
{
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0000 (nul)
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0001
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0002
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0003
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0004
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0005
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0006
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0007
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0008
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0009
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000A
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000B
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000C
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000D
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000E
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000F
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0010
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0011
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0012
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0013
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0014
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0015
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0016
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0017
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0018
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0019
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001A
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001B
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001C
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001D
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001E
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001F
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0020 (space)
|
||||
{ 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18, 0x00}, // U+0021 (!)
|
||||
{ 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0022 (")
|
||||
{ 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36, 0x00}, // U+0023 (#)
|
||||
{ 0x0C, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x0C, 0x00}, // U+0024 ($)
|
||||
{ 0x00, 0x63, 0x33, 0x18, 0x0C, 0x66, 0x63, 0x00}, // U+0025 (%)
|
||||
{ 0x1C, 0x36, 0x1C, 0x6E, 0x3B, 0x33, 0x6E, 0x00}, // U+0026 (&)
|
||||
{ 0x06, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0027 (')
|
||||
{ 0x18, 0x0C, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x00}, // U+0028 (()
|
||||
{ 0x06, 0x0C, 0x18, 0x18, 0x18, 0x0C, 0x06, 0x00}, // U+0029 ())
|
||||
{ 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00}, // U+002A (*)
|
||||
{ 0x00, 0x0C, 0x0C, 0x3F, 0x0C, 0x0C, 0x00, 0x00}, // U+002B (+)
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+002C (,)
|
||||
{ 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00}, // U+002D (-)
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+002E (.)
|
||||
{ 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x00}, // U+002F (/)
|
||||
{ 0x3E, 0x63, 0x73, 0x7B, 0x6F, 0x67, 0x3E, 0x00}, // U+0030 (0)
|
||||
{ 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x3F, 0x00}, // U+0031 (1)
|
||||
{ 0x1E, 0x33, 0x30, 0x1C, 0x06, 0x33, 0x3F, 0x00}, // U+0032 (2)
|
||||
{ 0x1E, 0x33, 0x30, 0x1C, 0x30, 0x33, 0x1E, 0x00}, // U+0033 (3)
|
||||
{ 0x38, 0x3C, 0x36, 0x33, 0x7F, 0x30, 0x78, 0x00}, // U+0034 (4)
|
||||
{ 0x3F, 0x03, 0x1F, 0x30, 0x30, 0x33, 0x1E, 0x00}, // U+0035 (5)
|
||||
{ 0x1C, 0x06, 0x03, 0x1F, 0x33, 0x33, 0x1E, 0x00}, // U+0036 (6)
|
||||
{ 0x3F, 0x33, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00}, // U+0037 (7)
|
||||
{ 0x1E, 0x33, 0x33, 0x1E, 0x33, 0x33, 0x1E, 0x00}, // U+0038 (8)
|
||||
{ 0x1E, 0x33, 0x33, 0x3E, 0x30, 0x18, 0x0E, 0x00}, // U+0039 (9)
|
||||
{ 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+003A (:)
|
||||
{ 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+003B (//)
|
||||
{ 0x18, 0x0C, 0x06, 0x03, 0x06, 0x0C, 0x18, 0x00}, // U+003C (<)
|
||||
{ 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00}, // U+003D (=)
|
||||
{ 0x06, 0x0C, 0x18, 0x30, 0x18, 0x0C, 0x06, 0x00}, // U+003E (>)
|
||||
{ 0x1E, 0x33, 0x30, 0x18, 0x0C, 0x00, 0x0C, 0x00}, // U+003F (?)
|
||||
{ 0x3E, 0x63, 0x7B, 0x7B, 0x7B, 0x03, 0x1E, 0x00}, // U+0040 (@)
|
||||
{ 0x0C, 0x1E, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x00}, // U+0041 (A)
|
||||
{ 0x3F, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3F, 0x00}, // U+0042 (B)
|
||||
{ 0x3C, 0x66, 0x03, 0x03, 0x03, 0x66, 0x3C, 0x00}, // U+0043 (C)
|
||||
{ 0x1F, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1F, 0x00}, // U+0044 (D)
|
||||
{ 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x46, 0x7F, 0x00}, // U+0045 (E)
|
||||
{ 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x06, 0x0F, 0x00}, // U+0046 (F)
|
||||
{ 0x3C, 0x66, 0x03, 0x03, 0x73, 0x66, 0x7C, 0x00}, // U+0047 (G)
|
||||
{ 0x33, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x33, 0x00}, // U+0048 (H)
|
||||
{ 0x1E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0049 (I)
|
||||
{ 0x78, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E, 0x00}, // U+004A (J)
|
||||
{ 0x67, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x67, 0x00}, // U+004B (K)
|
||||
{ 0x0F, 0x06, 0x06, 0x06, 0x46, 0x66, 0x7F, 0x00}, // U+004C (L)
|
||||
{ 0x63, 0x77, 0x7F, 0x7F, 0x6B, 0x63, 0x63, 0x00}, // U+004D (M)
|
||||
{ 0x63, 0x67, 0x6F, 0x7B, 0x73, 0x63, 0x63, 0x00}, // U+004E (N)
|
||||
{ 0x1C, 0x36, 0x63, 0x63, 0x63, 0x36, 0x1C, 0x00}, // U+004F (O)
|
||||
{ 0x3F, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x0F, 0x00}, // U+0050 (P)
|
||||
{ 0x1E, 0x33, 0x33, 0x33, 0x3B, 0x1E, 0x38, 0x00}, // U+0051 (Q)
|
||||
{ 0x3F, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x67, 0x00}, // U+0052 (R)
|
||||
{ 0x1E, 0x33, 0x07, 0x0E, 0x38, 0x33, 0x1E, 0x00}, // U+0053 (S)
|
||||
{ 0x3F, 0x2D, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0054 (T)
|
||||
{ 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F, 0x00}, // U+0055 (U)
|
||||
{ 0x33, 0x33, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0056 (V)
|
||||
{ 0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63, 0x00}, // U+0057 (W)
|
||||
{ 0x63, 0x63, 0x36, 0x1C, 0x1C, 0x36, 0x63, 0x00}, // U+0058 (X)
|
||||
{ 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x0C, 0x1E, 0x00}, // U+0059 (Y)
|
||||
{ 0x7F, 0x63, 0x31, 0x18, 0x4C, 0x66, 0x7F, 0x00}, // U+005A (Z)
|
||||
{ 0x1E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x1E, 0x00}, // U+005B ([)
|
||||
{ 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00}, // U+005C (\)
|
||||
{ 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x00}, // U+005D (])
|
||||
{ 0x08, 0x1C, 0x36, 0x63, 0x00, 0x00, 0x00, 0x00}, // U+005E (^)
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF}, // U+005F (_)
|
||||
{ 0x0C, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0060 (`)
|
||||
{ 0x00, 0x00, 0x1E, 0x30, 0x3E, 0x33, 0x6E, 0x00}, // U+0061 (a)
|
||||
{ 0x07, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3B, 0x00}, // U+0062 (b)
|
||||
{ 0x00, 0x00, 0x1E, 0x33, 0x03, 0x33, 0x1E, 0x00}, // U+0063 (c)
|
||||
{ 0x38, 0x30, 0x30, 0x3e, 0x33, 0x33, 0x6E, 0x00}, // U+0064 (d)
|
||||
{ 0x00, 0x00, 0x1E, 0x33, 0x3f, 0x03, 0x1E, 0x00}, // U+0065 (e)
|
||||
{ 0x1C, 0x36, 0x06, 0x0f, 0x06, 0x06, 0x0F, 0x00}, // U+0066 (f)
|
||||
{ 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0067 (g)
|
||||
{ 0x07, 0x06, 0x36, 0x6E, 0x66, 0x66, 0x67, 0x00}, // U+0068 (h)
|
||||
{ 0x0C, 0x00, 0x0E, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0069 (i)
|
||||
{ 0x30, 0x00, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E}, // U+006A (j)
|
||||
{ 0x07, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x67, 0x00}, // U+006B (k)
|
||||
{ 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+006C (l)
|
||||
{ 0x00, 0x00, 0x33, 0x7F, 0x7F, 0x6B, 0x63, 0x00}, // U+006D (m)
|
||||
{ 0x00, 0x00, 0x1F, 0x33, 0x33, 0x33, 0x33, 0x00}, // U+006E (n)
|
||||
{ 0x00, 0x00, 0x1E, 0x33, 0x33, 0x33, 0x1E, 0x00}, // U+006F (o)
|
||||
{ 0x00, 0x00, 0x3B, 0x66, 0x66, 0x3E, 0x06, 0x0F}, // U+0070 (p)
|
||||
{ 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x78}, // U+0071 (q)
|
||||
{ 0x00, 0x00, 0x3B, 0x6E, 0x66, 0x06, 0x0F, 0x00}, // U+0072 (r)
|
||||
{ 0x00, 0x00, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x00}, // U+0073 (s)
|
||||
{ 0x08, 0x0C, 0x3E, 0x0C, 0x0C, 0x2C, 0x18, 0x00}, // U+0074 (t)
|
||||
{ 0x00, 0x00, 0x33, 0x33, 0x33, 0x33, 0x6E, 0x00}, // U+0075 (u)
|
||||
{ 0x00, 0x00, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0076 (v)
|
||||
{ 0x00, 0x00, 0x63, 0x6B, 0x7F, 0x7F, 0x36, 0x00}, // U+0077 (w)
|
||||
{ 0x00, 0x00, 0x63, 0x36, 0x1C, 0x36, 0x63, 0x00}, // U+0078 (x)
|
||||
{ 0x00, 0x00, 0x33, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0079 (y)
|
||||
{ 0x00, 0x00, 0x3F, 0x19, 0x0C, 0x26, 0x3F, 0x00}, // U+007A (z)
|
||||
{ 0x38, 0x0C, 0x0C, 0x07, 0x0C, 0x0C, 0x38, 0x00}, // U+007B ({)
|
||||
{ 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00}, // U+007C (|)
|
||||
{ 0x07, 0x0C, 0x0C, 0x38, 0x0C, 0x0C, 0x07, 0x00}, // U+007D (})
|
||||
{ 0x6E, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+007E (~)
|
||||
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} // U+007F
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
#include "go.h"
|
||||
|
||||
extern "C" {
|
||||
#include "emuapi.h"
|
||||
#include "iopins.h"
|
||||
}
|
||||
|
||||
#include "esp_event.h"
|
||||
|
||||
#include "keyboard_osd.h"
|
||||
#include "ili9341_t3dma.h"
|
||||
#ifdef HAS_SND
|
||||
#include "AudioPlaySystem.h"
|
||||
#endif
|
||||
|
||||
#include "emul.h"
|
||||
|
||||
|
||||
ILI9341_t3DMA tft = ILI9341_t3DMA(PIN_NUM_CS, PIN_NUM_DC, -1, PIN_NUM_MOSI, PIN_NUM_CLK, PIN_NUM_MISO, TPIN_NUM_CS, TPIN_NUM_IRQ);
|
||||
#ifdef HAS_SND
|
||||
AudioPlaySystem audio;
|
||||
#endif
|
||||
|
||||
|
||||
static void spi_task(void *args)
|
||||
{
|
||||
while(true) {
|
||||
tft.refresh();
|
||||
}
|
||||
}
|
||||
|
||||
static void input_task(void *args)
|
||||
{
|
||||
while(true) {
|
||||
/*
|
||||
if ((emu_ReadKeys() & (MASK_KEY_USER1+MASK_KEY_USER2)) == (MASK_KEY_USER1+MASK_KEY_USER2)) {
|
||||
printf("rebooting\n");
|
||||
esp_restart();
|
||||
}
|
||||
*/
|
||||
|
||||
uint16_t bClick = emu_DebounceLocalKeys();
|
||||
/*
|
||||
if (bClick & MASK_KEY_USER2) {
|
||||
printf("%d\n",emu_SwapJoysticks(1));
|
||||
emu_SwapJoysticks(0);
|
||||
}
|
||||
else
|
||||
*/
|
||||
{
|
||||
emu_Input(bClick);
|
||||
}
|
||||
#ifdef HAS_SND
|
||||
audio.step();
|
||||
#endif
|
||||
vTaskDelay(20 / portTICK_PERIOD_MS);
|
||||
}
|
||||
}
|
||||
|
||||
static void main_step() {
|
||||
if (menuActive()) {
|
||||
uint16_t bClick = emu_DebounceLocalKeys();
|
||||
int action = handleMenu(bClick);
|
||||
char * filename = menuSelection();
|
||||
if (action == ACTION_RUNTFT) {
|
||||
#ifdef HAS_SND
|
||||
audio.begin();
|
||||
audio.start();
|
||||
#endif
|
||||
toggleMenu(false);
|
||||
tft.fillScreenNoDma( RGBVAL16(0x00,0x00,0x00) );
|
||||
xTaskCreatePinnedToCore(input_task, "inputthread", 4096, NULL, 2, NULL, 0);
|
||||
emu_Init(filename);
|
||||
}
|
||||
//vTaskDelay(20 / portTICK_PERIOD_MS);
|
||||
}
|
||||
else {
|
||||
emu_Step();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void setup(void)
|
||||
{
|
||||
printf("Starting emulator\n");
|
||||
|
||||
tft.begin();
|
||||
//tft.flipscreen(true);
|
||||
tft.start();
|
||||
tft.refresh();
|
||||
|
||||
emu_init();
|
||||
|
||||
xTaskCreatePinnedToCore(spi_task, "spithread", 4096, NULL, 1, NULL, 0);
|
||||
//vTaskPrioritySet(NULL, tskIDLE_PRIORITY+1);
|
||||
//toggleMenu(false);
|
||||
//xTaskCreatePinnedToCore(input_task, "inputthread", 4096, NULL, 2, NULL, 0);
|
||||
|
||||
//emu_Init("filename");
|
||||
|
||||
}
|
||||
|
||||
void loop(void)
|
||||
{
|
||||
unsigned long t = esp_timer_get_time();
|
||||
main_step();
|
||||
//printf("%d\n",(int)((esp_timer_get_time()-t)/1000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void setup(void);
|
||||
void loop(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
#ifdef MEGA
|
||||
#include <TimerOne.h>
|
||||
#else
|
||||
#include "esp32-hal-timer.h"
|
||||
//IntervalTimer myTimer;
|
||||
hw_timer_t * timer = NULL;
|
||||
#endif
|
||||
|
||||
#define PIT_MODE_LATCHCOUNT 0
|
||||
#define PIT_MODE_LOBYTE 1
|
||||
#define PIT_MODE_HIBYTE 2
|
||||
#define PIT_MODE_TOGGLE 3
|
||||
|
||||
|
||||
struct i8253_s {
|
||||
uint16_t chandata[3];
|
||||
uint8_t accessmode[3];
|
||||
uint8_t bytetoggle[3];
|
||||
uint32_t effectivedata[3];
|
||||
float chanfreq[3];
|
||||
uint8_t active[3];
|
||||
uint16_t counter[3];
|
||||
} i8253;
|
||||
|
||||
volatile uint8_t timerTick = 0;
|
||||
|
||||
void timer_isr() {
|
||||
timerTick = 1;
|
||||
}
|
||||
|
||||
void out8253 (uint16_t portnum, uint8_t value) {
|
||||
uint8_t curbyte;
|
||||
portnum &= 3;
|
||||
switch (portnum) {
|
||||
case 0:
|
||||
case 1:
|
||||
case 2: //channel data
|
||||
if ( (i8253.accessmode[portnum] == PIT_MODE_LOBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 0) ) ) curbyte = 0;
|
||||
else if ( (i8253.accessmode[portnum] == PIT_MODE_HIBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 1) ) ) curbyte = 1;
|
||||
if (curbyte == 0) { //low byte
|
||||
i8253.chandata[portnum] = (i8253.chandata[portnum] & 0xFF00) | value;
|
||||
}
|
||||
else { //high byte
|
||||
i8253.chandata[portnum] = (i8253.chandata[portnum] & 0x00FF) | ( (uint16_t) value << 8);
|
||||
}
|
||||
if (i8253.chandata[portnum] == 0) i8253.effectivedata[portnum] = 65536;
|
||||
else i8253.effectivedata[portnum] = i8253.chandata[portnum];
|
||||
i8253.active[portnum] = 1;
|
||||
if (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) i8253.bytetoggle[portnum] = (~i8253.bytetoggle[portnum]) & 1;
|
||||
//i8253.chanfreq[portnum] = (float) ( (uint32_t) ( ( (float) 1193182.0 / (float) i8253.effectivedata[portnum]) * (float) 1000.0) );
|
||||
//Serial.print("period "); Serial.println((uint32_t) ((float)1000000.0 / ( ( (float) 1193182.0 / (float) i8253.effectivedata[portnum]))));
|
||||
if (portnum == 0) {
|
||||
uint32_t period;
|
||||
period = (uint32_t) ((float)1000000.0 / ( ( (float) 1193182.0 / (float) i8253.effectivedata[portnum])));
|
||||
#ifdef MEGA
|
||||
if (period < 4000) period = 4000; //limit to 250 Hz, or the emulator just can't keep up on a Mega
|
||||
//Serial.println((float)1000000.0 / (float)period);
|
||||
Timer1.attachInterrupt(timer_isr, period);
|
||||
#else
|
||||
//myTimer.begin(timer_isr, period);
|
||||
//printf("timer %d\n",period);
|
||||
timerAttachInterrupt(timer, &timer_isr, true); // P3= edge triggered
|
||||
timerAlarmWrite(timer, period, true); // will trigger 22050 times per sec (443 per 20 ms=22050/50)
|
||||
timerAlarmEnable(timer);
|
||||
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
case 3: //mode/command
|
||||
i8253.accessmode[value>>6] = (value >> 4) & 3;
|
||||
if (i8253.accessmode[value>>6] == PIT_MODE_TOGGLE) i8253.bytetoggle[value>>6] = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t in8253 (uint16_t portnum) {
|
||||
uint8_t curbyte;
|
||||
portnum &= 3;
|
||||
switch (portnum) {
|
||||
case 0:
|
||||
case 1:
|
||||
case 2: //channel data
|
||||
if ( (i8253.accessmode[portnum] == 0) || (i8253.accessmode[portnum] == PIT_MODE_LOBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 0) ) ) curbyte = 0;
|
||||
else if ( (i8253.accessmode[portnum] == PIT_MODE_HIBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 1) ) ) curbyte = 1;
|
||||
if ( (i8253.accessmode[portnum] == 0) || (i8253.accessmode[portnum] == PIT_MODE_LOBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 0) ) ) curbyte = 0;
|
||||
else if ( (i8253.accessmode[portnum] == PIT_MODE_HIBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 1) ) ) curbyte = 1;
|
||||
if ( (i8253.accessmode[portnum] == 0) || (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) ) i8253.bytetoggle[portnum] = (~i8253.bytetoggle[portnum]) & 1;
|
||||
if (curbyte == 0) { //low byte
|
||||
if (i8253.counter[portnum] < 10) i8253.counter[portnum] = i8253.chandata[portnum];
|
||||
i8253.counter[portnum] -= 10;
|
||||
return ( (uint8_t) i8253.counter[portnum]);
|
||||
}
|
||||
else { //high byte
|
||||
return ( (uint8_t) (i8253.counter[portnum] >> 8) );
|
||||
}
|
||||
break;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
void init8253() {
|
||||
memset (&i8253, 0, sizeof (i8253) );
|
||||
#ifdef MEGA
|
||||
Timer1.initialize(54925);
|
||||
Timer1.attachInterrupt(timer_isr, 54925);
|
||||
#else
|
||||
//myTimer.begin(timer_isr, 54925);
|
||||
timer = timerBegin(0, 80, true); // use timer 0, pre-scaler is 80 (divide by 8000), count up
|
||||
timerAttachInterrupt(timer, &timer_isr, true);
|
||||
timerAlarmWrite(timer, 54925, true);
|
||||
timerAlarmEnable(timer);
|
||||
|
||||
#endif
|
||||
//set_port_write_redirector (0x40, 0x43, &out8253);
|
||||
//set_port_read_redirector (0x40, 0x43, &in8253);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/* i8259.c - emulation code for the Intel 8259 controller.
|
||||
Note: This is not a very complete i8259 interrupt controller
|
||||
implementation, but for the purposes of a PC, it's all we need. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
struct structpic {
|
||||
uint8_t imr; //mask register
|
||||
uint8_t irr; //request register
|
||||
uint8_t isr; //service register
|
||||
uint8_t icwstep; //used during initialization to keep track of which ICW we're at
|
||||
uint8_t icw[5];
|
||||
uint8_t intoffset; //interrupt vector offset
|
||||
uint8_t priority; //which IRQ has highest priority
|
||||
uint8_t autoeoi; //automatic EOI mode
|
||||
uint8_t readmode; //remember what to return on read register from OCW3
|
||||
uint8_t enabled;
|
||||
} i8259;
|
||||
|
||||
|
||||
void init8259() {
|
||||
memset((void *)&i8259, 0, sizeof(i8259));
|
||||
}
|
||||
|
||||
uint8_t in8259(uint16_t portnum) {
|
||||
switch (portnum & 1) {
|
||||
case 0:
|
||||
if (i8259.readmode==0) return(i8259.irr); else return(i8259.isr);
|
||||
case 1: //read mask register
|
||||
return(i8259.imr);
|
||||
}
|
||||
return(0); //can't get here, but the compiler bitches
|
||||
}
|
||||
|
||||
extern uint32_t makeupticks;
|
||||
void out8259(uint16_t portnum, uint8_t value) {
|
||||
uint8_t i;
|
||||
switch (portnum & 1) {
|
||||
case 0:
|
||||
if (value & 0x10) { //begin initialization sequence
|
||||
i8259.icwstep = 1;
|
||||
i8259.imr = 0; //clear interrupt mask register
|
||||
i8259.icw[i8259.icwstep++] = value;
|
||||
return;
|
||||
}
|
||||
if ((value & 0x98)==8) { //it's an OCW3
|
||||
if (value & 2) i8259.readmode = value & 2;
|
||||
}
|
||||
if (value & 0x20) { //EOI command
|
||||
for (i=0; i<8; i++)
|
||||
if ((i8259.isr >> i) & 1) {
|
||||
i8259.isr ^= (1 << i);
|
||||
if ((i==0) && (makeupticks>0)) { makeupticks = 0; i8259.irr |= 1; }
|
||||
return;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
if ((i8259.icwstep==3) && (i8259.icw[1] & 2)) i8259.icwstep = 4; //single mode, so don't read ICW3
|
||||
if (i8259.icwstep<5) { i8259.icw[i8259.icwstep++] = value; return; }
|
||||
//if we get to this point, this is just a new IMR value
|
||||
i8259.imr = value;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t nextintr() {
|
||||
uint8_t i, tmpirr;
|
||||
tmpirr = i8259.irr & (~i8259.imr); //XOR request register with inverted mask register
|
||||
for (i=0; i<8; i++)
|
||||
if ((tmpirr >> i) & 1) {
|
||||
i8259.irr ^= (1 << i);
|
||||
i8259.isr |= (1 << i);
|
||||
return(i8259.icw[2] + i);
|
||||
}
|
||||
return(0); //can't get here, but the compiler bitches
|
||||
}
|
||||
|
||||
void doirq(uint8_t irqnum) {
|
||||
i8259.irr |= (1 << irqnum);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,680 @@
|
|||
/*
|
||||
ILI9341 SPI driver inspired from the Teensy version of Frank Bösing, 2017
|
||||
*/
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
|
||||
#include "esp_system.h"
|
||||
#include "driver/spi_master.h"
|
||||
#include "soc/gpio_struct.h"
|
||||
#include "driver/gpio.h"
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "ili9341_t3dma.h"
|
||||
#include "font8x8.h"
|
||||
|
||||
|
||||
|
||||
static spi_device_handle_t lcdspi;
|
||||
static spi_transaction_t trans[MAX_SPI_TRANS];
|
||||
|
||||
static uint16_t *blocks[NR_OF_BLOCK];
|
||||
static uint8_t _rst, _cs, _dc;
|
||||
static uint8_t _miso, _mosi, _clk;
|
||||
static uint8_t _touch_irq, _touch_cs;
|
||||
|
||||
//DRAM_ATTR static uint16_t block0[320*LINES_PER_BLOCK];
|
||||
//DRAM_ATTR static uint16_t block1[320*LINES_PER_BLOCK];
|
||||
|
||||
static const lcd_init_cmd_t ili_init_cmds[]={
|
||||
{0xEF, {0x03, 0x80, 0x02}, 3},
|
||||
{0xCF, {0x00, 0XC1, 0X30}, 3},
|
||||
{0xED, {0x64, 0x03, 0X12, 0X81}, 4},
|
||||
{0xE8, {0x85, 0x00, 0x78}, 3},
|
||||
{0xCB, {0x39, 0x2C, 0x00, 0x34, 0x02}, 5},
|
||||
{0xF7, {0x20}, 1},
|
||||
{0xEA, {0x00, 0x00}, 2},
|
||||
{ILI9341_PWCTR1, {0x23}, 1}, // Power control
|
||||
{ILI9341_PWCTR2, {0x10}, 1}, // Power control
|
||||
{ILI9341_VMCTR1, {0x3e, 0x28}, 2}, // VCM control
|
||||
{ILI9341_VMCTR2, {0x86}, 1}, // VCM control2
|
||||
{ILI9341_MADCTL, {0x48}, 1}, // Memory Access Control
|
||||
{ILI9341_PIXFMT, {0x55}, 1},
|
||||
{ILI9341_FRMCTR1, {0x00, 0x18}, 2},
|
||||
{ILI9341_DFUNCTR, {0x08, 0x82, 0x27}, 3}, // Display Function Control
|
||||
{0xF2, {0x00}, 1}, // Gamma Function Disable
|
||||
{ILI9341_GAMMASET, {0x01}, 1}, // Gamma curve selected
|
||||
{ILI9341_GMCTRP1, {0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08,
|
||||
0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00}, 15}, // Set Gamma
|
||||
{ILI9341_GMCTRN1, {0x00, 0x0E, 0x14, 0x03, 0x11, 0x07,
|
||||
0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F}, 15}, // Set Gamma
|
||||
// 3, 0xb1, 0x00, 0x1f, // FrameRate Control 61Hz
|
||||
{0xb1, {0x00, 0x10}, 2}, // FrameRate Control 119Hz
|
||||
{ILI9341_MADCTL, {MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR}, 1},
|
||||
|
||||
/* Sleep out */
|
||||
{ILI9341_SLPOUT, {0}, 0x80},
|
||||
/* Display on */
|
||||
{ILI9341_DISPON, {0}, 0x80},
|
||||
|
||||
|
||||
// Area width, hight
|
||||
{ILI9341_CASET, {0, 0, (ILI9341_TFTREALWIDTH)>>8, (ILI9341_TFTREALWIDTH)&0xff}, 4},
|
||||
{ILI9341_PASET, {0, 0, (ILI9341_TFTREALHEIGHT)>>8, (ILI9341_TFTREALHEIGHT)&0xff}, 4},
|
||||
|
||||
{0, {0}, 0xff},
|
||||
};
|
||||
|
||||
static void lcd_cmd(spi_device_handle_t spi, const uint8_t cmd)
|
||||
{
|
||||
esp_err_t ret;
|
||||
spi_transaction_t t;
|
||||
memset(&t, 0, sizeof(t)); //Zero out the transaction
|
||||
t.length=8; //Command is 8 bits
|
||||
t.tx_buffer=&cmd; //The data is the cmd itself
|
||||
t.user=(void*)0; //D/C needs to be set to 0
|
||||
t.flags=0;
|
||||
ret=spi_device_polling_transmit(spi, &t); //Transmit!
|
||||
assert(ret==ESP_OK); //Should have had no issues.
|
||||
}
|
||||
|
||||
|
||||
static void lcd_data(spi_device_handle_t spi, const uint8_t *data, int len)
|
||||
{
|
||||
esp_err_t ret;
|
||||
spi_transaction_t t;
|
||||
if (len==0) return; //no need to send anything
|
||||
memset(&t, 0, sizeof(t)); //Zero out the transaction
|
||||
t.length=len*8; //Len is in bytes, transaction length is in bits.
|
||||
t.tx_buffer=data; //Data
|
||||
t.user=(void*)1; //D/C needs to be set to 1
|
||||
t.flags=0;
|
||||
ret=spi_device_polling_transmit(spi, &t); //Transmit!
|
||||
assert(ret==ESP_OK); //Should have had no issues.
|
||||
}
|
||||
|
||||
//This function is called (in irq context!) just before a transmission starts. It will
|
||||
//set the D/C line to the value indicated in the user field.
|
||||
static void lcd_spi_pre_transfer_callback(spi_transaction_t *t)
|
||||
{
|
||||
int dc=(int)t->user;
|
||||
gpio_set_level((gpio_num_t)_dc, dc);
|
||||
}
|
||||
|
||||
|
||||
//Initialize the display
|
||||
static void lcd_init(spi_device_handle_t spi)
|
||||
{
|
||||
//Initialize non-SPI GPIOs
|
||||
gpio_set_direction((gpio_num_t)_dc, GPIO_MODE_OUTPUT);
|
||||
|
||||
printf("LCD ILI9341 initialization.\n");
|
||||
//Send all the commands
|
||||
|
||||
|
||||
//memcpy(ili_init_cmds, ili_init_cmdos, sizeof(ili_init_cmdos));
|
||||
int cmd=0;
|
||||
while (ili_init_cmds[cmd].databytes!=0xff) {
|
||||
lcd_cmd(spi, ili_init_cmds[cmd].cmd);
|
||||
lcd_data(spi, ili_init_cmds[cmd].data, ili_init_cmds[cmd].databytes&0x1F);
|
||||
if (ili_init_cmds[cmd].databytes&0x80) {
|
||||
vTaskDelay(100 / portTICK_RATE_MS);
|
||||
}
|
||||
cmd++;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//Allocate memory block buffers and DMA transactions
|
||||
printf("Allocate video mem and DMA transactions\n");
|
||||
|
||||
int i=0;
|
||||
trans[i].tx_data[0]=ILI9341_RAMWR;
|
||||
trans[i].length=8;
|
||||
trans[i].user=(void*)0;
|
||||
trans[i++].flags=SPI_TRANS_USE_TXDATA;
|
||||
|
||||
//blocks[0]= &block0[0];
|
||||
//blocks[1]= &block1[0];
|
||||
|
||||
int remaininglines=ILI9341_TFTREALHEIGHT;
|
||||
for (int j=0; j<NR_OF_BLOCK; j++)
|
||||
{
|
||||
int lines_per_block = LINES_PER_BLOCK;
|
||||
if ((remaininglines - LINES_PER_BLOCK) < 0) {
|
||||
lines_per_block = remaininglines;
|
||||
}
|
||||
remaininglines -= LINES_PER_BLOCK;
|
||||
/*if (j > 1)*/ blocks[j]= (uint16_t*)heap_caps_malloc(ILI9341_TFTREALWIDTH*lines_per_block*sizeof(uint16_t), MALLOC_CAP_DMA);
|
||||
assert(blocks[j]!=NULL);
|
||||
|
||||
trans[i].tx_buffer=blocks[j];
|
||||
trans[i].length=ILI9341_TFTREALWIDTH*2*8*lines_per_block;
|
||||
trans[i].user=(void*)1;
|
||||
trans[i++].flags=0; //undo SPI_TRANS_USE_TXDATA flag
|
||||
|
||||
uint16_t color;
|
||||
switch (j) {
|
||||
case 0:
|
||||
color=0xf000;
|
||||
break;
|
||||
case 1:
|
||||
color=0x0f00;
|
||||
break;
|
||||
case 2:
|
||||
color=0x00f0;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
color=0x000f;
|
||||
break;
|
||||
}
|
||||
uint16_t * fb = blocks[j];
|
||||
for (int y=0;y<lines_per_block;y++)
|
||||
for (int x=0;x<ILI9341_TFTREALWIDTH;x++)
|
||||
*fb++=color;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void send_blocks(spi_device_handle_t spi)
|
||||
{
|
||||
esp_err_t ret;
|
||||
//Queue all transactions.
|
||||
for (int j=0; j<(NR_OF_BLOCK+1); j++) {
|
||||
ret=spi_device_queue_trans(spi, &trans[j], portMAX_DELAY);
|
||||
assert(ret==ESP_OK);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void send_blocks_finish(spi_device_handle_t spi)
|
||||
{
|
||||
spi_transaction_t *rtrans;
|
||||
esp_err_t ret;
|
||||
for (int j=0; j<(NR_OF_BLOCK+1); j++) {
|
||||
ret=spi_device_get_trans_result(spi, &rtrans, portMAX_DELAY);
|
||||
assert(ret==ESP_OK);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
ILI9341_t3DMA::ILI9341_t3DMA(uint8_t cs, uint8_t dc, uint8_t rst, uint8_t mosi, uint8_t clk, uint8_t miso, uint8_t touch_cs, uint8_t touch_irq)
|
||||
{
|
||||
_cs = cs;
|
||||
_dc = dc;
|
||||
_rst = rst;
|
||||
_mosi = mosi;
|
||||
_clk = clk;
|
||||
_miso = miso;
|
||||
_touch_irq = touch_irq;
|
||||
_touch_cs = touch_cs;
|
||||
}
|
||||
|
||||
|
||||
void ILI9341_t3DMA::begin(void) {
|
||||
esp_err_t ret;
|
||||
|
||||
spi_bus_config_t buscfg;
|
||||
memset(&buscfg, 0, sizeof(buscfg));
|
||||
buscfg.miso_io_num=_miso;
|
||||
buscfg.mosi_io_num=_mosi;
|
||||
buscfg.sclk_io_num=_clk;
|
||||
buscfg.quadwp_io_num=-1;
|
||||
buscfg.quadhd_io_num=-1;
|
||||
buscfg.max_transfer_sz=LINES_PER_BLOCK*ILI9341_TFTREALWIDTH*2+8;
|
||||
|
||||
spi_device_interface_config_t devcfg;
|
||||
memset(&devcfg, 0, sizeof(devcfg));
|
||||
devcfg.clock_speed_hz=60*1000*1000; //Clock out
|
||||
devcfg.mode=0; //SPI mode 0
|
||||
devcfg.spics_io_num=_cs; //CS pin
|
||||
devcfg.queue_size=MAX_SPI_TRANS;
|
||||
devcfg.pre_cb=lcd_spi_pre_transfer_callback; //Specify pre-transfer callback to handle D/C line
|
||||
devcfg.flags = SPI_DEVICE_HALFDUPLEX ; //With IOMUX and half duplex can go faster
|
||||
|
||||
//Initialize the SPI bus
|
||||
ret=spi_bus_initialize(VSPI_HOST, &buscfg, 1);
|
||||
ESP_ERROR_CHECK(ret);
|
||||
//Attach the LCD to the SPI bus
|
||||
ret=spi_bus_add_device(VSPI_HOST, &devcfg, &lcdspi);
|
||||
ESP_ERROR_CHECK(ret);
|
||||
};
|
||||
|
||||
void ILI9341_t3DMA::start(void) {
|
||||
lcd_init(lcdspi);
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::refresh(void) {
|
||||
send_blocks(lcdspi);
|
||||
send_blocks_finish(lcdspi);
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::refreshPrepare(void) {
|
||||
send_blocks(lcdspi);
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::refreshFinish(void) {
|
||||
send_blocks_finish(lcdspi);
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::flipscreen(bool flip)
|
||||
{
|
||||
if (flip) {
|
||||
flipped=true;
|
||||
}
|
||||
else {
|
||||
flipped=false;
|
||||
}
|
||||
}
|
||||
|
||||
bool ILI9341_t3DMA::isflipped(void)
|
||||
{
|
||||
return(flipped);
|
||||
}
|
||||
|
||||
uint16_t * ILI9341_t3DMA::getLineBuffer(int j)
|
||||
{
|
||||
uint16_t * block=blocks[j>>6];
|
||||
return(&block[(j&0x3F)*ILI9341_TFTREALWIDTH]);
|
||||
}
|
||||
|
||||
|
||||
void ILI9341_t3DMA::fillScreen(uint16_t color) {
|
||||
int i,j;
|
||||
color=SPI_SWAP_DATA_TX(color,16);
|
||||
for (j=0; j<ILI9341_TFTREALHEIGHT; j++)
|
||||
{
|
||||
uint16_t * block=blocks[j>>6];
|
||||
uint16_t * dst=&block[(j&0x3F)*ILI9341_TFTREALWIDTH];
|
||||
for (i=0; i<ILI9341_TFTREALWIDTH; i++)
|
||||
{
|
||||
*dst++ = color;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::writeScreen(int width, int height, int stride, uint8_t *buf, uint16_t *palette16) {
|
||||
uint8_t *buffer=buf;
|
||||
uint8_t *src;
|
||||
|
||||
int i,j,y=0;
|
||||
if (width*2 <= ILI9341_TFTREALWIDTH) {
|
||||
for (j=0; j<height; j++)
|
||||
{
|
||||
uint16_t * block=blocks[y>>6];
|
||||
uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH];
|
||||
src=buffer;
|
||||
for (i=0; i<width; i++)
|
||||
{
|
||||
uint16_t val = SPI_SWAP_DATA_TX(palette16[*src++],16);
|
||||
*dst++ = val;
|
||||
*dst++ = val;
|
||||
}
|
||||
y++;
|
||||
if (height*2 <= ILI9341_TFTREALHEIGHT) {
|
||||
block=blocks[y>>6];
|
||||
dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH];
|
||||
src=buffer;
|
||||
for (i=0; i<width; i++)
|
||||
{
|
||||
uint16_t val = SPI_SWAP_DATA_TX(palette16[*src++],16);
|
||||
*dst++ = val;
|
||||
*dst++ = val;
|
||||
}
|
||||
y++;
|
||||
}
|
||||
buffer += stride;
|
||||
}
|
||||
}
|
||||
else if (width <= ILI9341_TFTREALWIDTH) {
|
||||
//dst += (ILI9341_TFTWIDTH-width)/2;
|
||||
for (j=0; j<height; j++)
|
||||
{
|
||||
uint16_t * block=blocks[y>>6];
|
||||
uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH+(ILI9341_TFTREALWIDTH-width)/2];
|
||||
src=buffer;
|
||||
for (i=0; i<width; i++)
|
||||
{
|
||||
uint16_t val = SPI_SWAP_DATA_TX(palette16[*src++],16);
|
||||
*dst++ = val;
|
||||
}
|
||||
y++;
|
||||
if (height*2 <= ILI9341_TFTREALHEIGHT) {
|
||||
block=blocks[y>>6];
|
||||
dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH+(ILI9341_TFTREALWIDTH-width)/2];
|
||||
src=buffer;
|
||||
for (i=0; i<width; i++)
|
||||
{
|
||||
uint16_t val = SPI_SWAP_DATA_TX(palette16[*src++],16);
|
||||
*dst++ = val;
|
||||
}
|
||||
y++;
|
||||
}
|
||||
buffer += stride;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::writeLine(int width, int height, int y, uint8_t *buf, uint16_t *palette16) {
|
||||
if (ILI9341_TFTHEIGHT > height)
|
||||
y += (ILI9341_TFTHEIGHT - height)/2;
|
||||
uint8_t * src=buf;
|
||||
uint16_t * block=blocks[y>>6];
|
||||
uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH];
|
||||
if (ILI9341_TFTWIDTH > width)
|
||||
dst += (ILI9341_TFTWIDTH - width)/2;
|
||||
for (int i=0; i<width; i++)
|
||||
{
|
||||
uint8_t val = *src++;
|
||||
*dst++=SPI_SWAP_DATA_TX(palette16[val],16);
|
||||
}
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::writeLine(int width, int height, int y, uint16_t *buf) {
|
||||
if (ILI9341_TFTHEIGHT > height)
|
||||
y += (ILI9341_TFTHEIGHT - height)/2;
|
||||
uint16_t * src=buf;
|
||||
uint16_t * block=blocks[y>>6];
|
||||
uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH];
|
||||
if (ILI9341_TFTWIDTH > width)
|
||||
dst += (ILI9341_TFTWIDTH - width)/2;
|
||||
for (int i=0; i<width; i++)
|
||||
{
|
||||
*dst++=SPI_SWAP_DATA_TX(*src++,16);
|
||||
}
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color) {
|
||||
|
||||
int i,j,l=y;
|
||||
color=SPI_SWAP_DATA_TX(color,16);
|
||||
for (j=0; j<h; j++)
|
||||
{
|
||||
uint16_t * block=blocks[l>>6];
|
||||
uint16_t * dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x];
|
||||
for (i=0; i<w; i++)
|
||||
{
|
||||
*dst++ = color;
|
||||
}
|
||||
l++;
|
||||
}
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::drawSprite(int16_t x, int16_t y, const uint16_t *bitmap) {
|
||||
drawSprite(x,y,bitmap, 0,0,0,0);
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t arx, uint16_t ary, uint16_t arw, uint16_t arh)
|
||||
{
|
||||
int bmp_offx = 0;
|
||||
int bmp_offy = 0;
|
||||
uint16_t *bmp_ptr;
|
||||
|
||||
int w =*bitmap++;
|
||||
int h = *bitmap++;
|
||||
|
||||
|
||||
if ( (arw == 0) || (arh == 0) ) {
|
||||
// no crop window
|
||||
arx = x;
|
||||
ary = y;
|
||||
arw = w;
|
||||
arh = h;
|
||||
}
|
||||
else {
|
||||
if ( (x>(arx+arw)) || ((x+w)<arx) || (y>(ary+arh)) || ((y+h)<ary) ) {
|
||||
return;
|
||||
}
|
||||
|
||||
// crop area
|
||||
if ( (x > arx) && (x<(arx+arw)) ) {
|
||||
arw = arw - (x-arx);
|
||||
arx = arx + (x-arx);
|
||||
} else {
|
||||
bmp_offx = arx;
|
||||
}
|
||||
if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) {
|
||||
arw -= (arx+arw-x-w);
|
||||
}
|
||||
if ( (y > ary) && (y<(ary+arh)) ) {
|
||||
arh = arh - (y-ary);
|
||||
ary = ary + (y-ary);
|
||||
} else {
|
||||
bmp_offy = ary;
|
||||
}
|
||||
if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) {
|
||||
arh -= (ary+arh-y-h);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int l=ary;
|
||||
bitmap = bitmap + bmp_offy*w + bmp_offx;
|
||||
for (int row=0;row<arh; row++)
|
||||
{
|
||||
uint16_t * block=blocks[l>>6];
|
||||
uint16_t * dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+arx];
|
||||
bmp_ptr = (uint16_t*)bitmap;
|
||||
for (int col=0;col<arw; col++)
|
||||
{
|
||||
*dst++ = SPI_SWAP_DATA_TX(*bmp_ptr++,16);
|
||||
}
|
||||
bitmap += w;
|
||||
l++;
|
||||
}
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::drawText(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize) {
|
||||
uint16_t c;
|
||||
uint16_t * block;
|
||||
uint16_t * dst;
|
||||
fgcolor = SPI_SWAP_DATA_TX(fgcolor,16);
|
||||
bgcolor = SPI_SWAP_DATA_TX(bgcolor,16);
|
||||
|
||||
while ((c = *text++)) {
|
||||
const unsigned char * charpt=&font8x8[c][0];
|
||||
|
||||
int l=y;
|
||||
for (int i=0;i<8;i++)
|
||||
{
|
||||
unsigned char bits;
|
||||
if (doublesize) {
|
||||
block=blocks[l>>6];
|
||||
dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x];
|
||||
bits = *charpt;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
l++;
|
||||
}
|
||||
block=blocks[l>>6];
|
||||
dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x];
|
||||
bits = *charpt++;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
bits = bits >> 1;
|
||||
if (bits&0x01) *dst++=fgcolor;
|
||||
else *dst++=bgcolor;
|
||||
l++;
|
||||
}
|
||||
x +=8;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
// TOUCH
|
||||
#define _BV(bit) (1 << (bit))
|
||||
#define XPT2046_CFG_START _BV(7)
|
||||
#define XPT2046_CFG_MUX(v) ((v&0b111) << (4))
|
||||
#define XPT2046_CFG_8BIT _BV(3)
|
||||
#define XPT2046_CFG_12BIT (0)
|
||||
#define XPT2046_CFG_SER _BV(2)
|
||||
#define XPT2046_CFG_DFR (0)
|
||||
#define XPT2046_CFG_PWR(v) ((v&0b11))
|
||||
#define XPT2046_MUX_Y 0b101
|
||||
#define XPT2046_MUX_X 0b001
|
||||
#define XPT2046_MUX_Z1 0b011
|
||||
#define XPT2046_MUX_Z2 0b100
|
||||
|
||||
|
||||
|
||||
static spi_device_handle_t touchspi;
|
||||
|
||||
//void ILI9341_t3DMA::touchBegin(uint8_t mosi, uint8_t miso, uint8_t clk, uint8_t cs) {
|
||||
void ILI9341_t3DMA::touchBegin() {
|
||||
esp_err_t ret;
|
||||
|
||||
gpio_set_direction((gpio_num_t)_touch_irq, GPIO_MODE_INPUT);
|
||||
gpio_set_pull_mode((gpio_num_t)_touch_irq, GPIO_PULLUP_ONLY);
|
||||
|
||||
spi_device_interface_config_t devcfg;
|
||||
memset(&devcfg, 0, sizeof(devcfg));
|
||||
devcfg.clock_speed_hz=2500000;
|
||||
devcfg.mode=0;
|
||||
devcfg.spics_io_num=_touch_cs;
|
||||
devcfg.queue_size=2;
|
||||
devcfg.flags = SPI_DEVICE_HALFDUPLEX ;
|
||||
|
||||
/*
|
||||
spi_bus_config_t buscfg;
|
||||
memset(&buscfg, 0, sizeof(buscfg));
|
||||
buscfg.miso_io_num=miso;
|
||||
buscfg.mosi_io_num=mosi;
|
||||
buscfg.sclk_io_num=clk;
|
||||
buscfg.quadwp_io_num=-1;
|
||||
buscfg.quadhd_io_num=-1;
|
||||
buscfg.max_transfer_sz=48;
|
||||
|
||||
ret=spi_bus_initialize(HSPI_HOST, &buscfg, 2);
|
||||
ESP_ERROR_CHECK(ret);
|
||||
*/
|
||||
|
||||
ret=spi_bus_add_device(HSPI_HOST, &devcfg, &touchspi);
|
||||
ESP_ERROR_CHECK(ret);
|
||||
}
|
||||
|
||||
|
||||
uint16_t touch_get_data(spi_device_handle_t spi, const uint8_t cmd)
|
||||
{
|
||||
spi_transaction_t t;
|
||||
memset(&t, 0, sizeof(t)); //Zero out the transaction
|
||||
t.length=8; //Command is 8 bits
|
||||
t.tx_buffer=&cmd; //The data is the cmd itself
|
||||
esp_err_t ret=spi_device_polling_transmit(spi, &t); //Transmit!
|
||||
if (ret==ESP_OK) {
|
||||
memset(&t, 0, sizeof(t));
|
||||
t.rxlength=8*2;
|
||||
t.flags = SPI_TRANS_USE_RXDATA;
|
||||
ret = spi_device_polling_transmit(spi, &t);
|
||||
if (ret==ESP_OK) {
|
||||
printf("touch data failed\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
else {
|
||||
printf("touch cmd failed\n");
|
||||
}
|
||||
return *(uint16_t*)t.rx_data;
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool ILI9341_t3DMA::isTouching()
|
||||
{
|
||||
return ((gpio_get_level((gpio_num_t)_touch_irq) == 0 ? true : false));
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::readRo(uint16_t * oX, uint16_t * oY, uint16_t * oZ) {
|
||||
uint16_t x = 0;
|
||||
uint16_t y = 0;
|
||||
uint16_t z1 = 0;
|
||||
uint16_t z2 = 0;
|
||||
uint8_t i = 0;
|
||||
int16_t xraw=0, yraw=0;
|
||||
|
||||
|
||||
for(; i < 15; i++) {
|
||||
y += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3)));
|
||||
x += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3)));
|
||||
z1 += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3)));
|
||||
z2 += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3)));
|
||||
}
|
||||
printf("%d %d %d %d \n",x/15,y/15,z1/15,z2/15);
|
||||
/*
|
||||
SPI.beginTransaction(SPI_SETTING);
|
||||
digitalWrite(_touch_cs, LOW);
|
||||
|
||||
for(; i < 15; i++) {
|
||||
// SPI requirer 32bit aliment
|
||||
uint8_t buf[12] = {
|
||||
(XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3)), 0x00, 0x00,
|
||||
(XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3)), 0x00, 0x00,
|
||||
(XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3)), 0x00, 0x00,
|
||||
(XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3)), 0x00, 0x00
|
||||
};
|
||||
SPI.transfer(&buf[0], &buf[0], 12);
|
||||
y += (buf[1] << 8 | buf[2])>>3;
|
||||
x += (buf[4] << 8 | buf[5])>>3;
|
||||
z1 += (buf[7] << 8 | buf[8])>>3;
|
||||
z2 += (buf[10] << 8 | buf[11])>>3;
|
||||
}
|
||||
*/
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ) {
|
||||
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ){
|
||||
|
||||
}
|
||||
|
||||
void ILI9341_t3DMA::callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax){
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
ILI9341 SPI driver inspired from the Teensy version of Frank Bösing, 2017
|
||||
*/
|
||||
|
||||
#ifndef _ILI9341_T3DMAH_
|
||||
#define _ILI9341_T3DMAH_
|
||||
|
||||
|
||||
#define FLIP_SCREEN 1
|
||||
|
||||
|
||||
#define RGBVAL32(r,g,b) ( (r<<16) | (g<<8) | b )
|
||||
#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) )
|
||||
#define RGBVAL8(r,g,b) ( (((r>>5)&0x07)<<5) | (((g>>5)&0x07)<<2) | (((b>>6)&0x3)<<0) )
|
||||
|
||||
|
||||
#define ILI9341_TFTWIDTH 320
|
||||
#define ILI9341_TFTHEIGHT 200
|
||||
#define ILI9341_TFTREALWIDTH 320
|
||||
#define ILI9341_TFTREALHEIGHT 240
|
||||
|
||||
|
||||
#define ILI9341_NOP 0x00
|
||||
#define ILI9341_SWRESET 0x01
|
||||
#define ILI9341_RDDID 0x04
|
||||
#define ILI9341_RDDST 0x09
|
||||
|
||||
#define ILI9341_SLPIN 0x10
|
||||
#define ILI9341_SLPOUT 0x11
|
||||
#define ILI9341_PTLON 0x12
|
||||
#define ILI9341_NORON 0x13
|
||||
|
||||
#define ILI9341_RDMODE 0x0A
|
||||
#define ILI9341_RDMADCTL 0x0B
|
||||
#define ILI9341_RDPIXFMT 0x0C
|
||||
#define ILI9341_RDIMGFMT 0x0D
|
||||
#define ILI9341_RDSELFDIAG 0x0F
|
||||
|
||||
#define ILI9341_INVOFF 0x20
|
||||
#define ILI9341_INVON 0x21
|
||||
#define ILI9341_GAMMASET 0x26
|
||||
#define ILI9341_DISPOFF 0x28
|
||||
#define ILI9341_DISPON 0x29
|
||||
|
||||
#define ILI9341_CASET 0x2A
|
||||
#define ILI9341_PASET 0x2B
|
||||
#define ILI9341_RAMWR 0x2C
|
||||
#define ILI9341_RAMRD 0x2E
|
||||
|
||||
#define ILI9341_PTLAR 0x30
|
||||
#define ILI9341_MADCTL 0x36
|
||||
#define ILI9341_VSCRSADD 0x37
|
||||
#define ILI9341_PIXFMT 0x3A
|
||||
|
||||
#define ILI9341_FRMCTR1 0xB1
|
||||
#define ILI9341_FRMCTR2 0xB2
|
||||
#define ILI9341_FRMCTR3 0xB3
|
||||
#define ILI9341_INVCTR 0xB4
|
||||
#define ILI9341_DFUNCTR 0xB6
|
||||
|
||||
#define ILI9341_PWCTR1 0xC0
|
||||
#define ILI9341_PWCTR2 0xC1
|
||||
#define ILI9341_PWCTR3 0xC2
|
||||
#define ILI9341_PWCTR4 0xC3
|
||||
#define ILI9341_PWCTR5 0xC4
|
||||
#define ILI9341_VMCTR1 0xC5
|
||||
#define ILI9341_VMCTR2 0xC7
|
||||
|
||||
#define ILI9341_RDID1 0xDA
|
||||
#define ILI9341_RDID2 0xDB
|
||||
#define ILI9341_RDID3 0xDC
|
||||
#define ILI9341_RDID4 0xDD
|
||||
|
||||
#define ILI9341_GMCTRP1 0xE0
|
||||
#define ILI9341_GMCTRN1 0xE1
|
||||
|
||||
#define MADCTL_MY 0x80
|
||||
#define MADCTL_MX 0x40
|
||||
#define MADCTL_MV 0x20
|
||||
#define MADCTL_ML 0x10
|
||||
#define MADCTL_RGB 0x00
|
||||
#define MADCTL_BGR 0x08
|
||||
#define MADCTL_MH 0x04
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
|
||||
#define MAX_SPI_TRANS 7
|
||||
#define NR_OF_BLOCK 4
|
||||
#define LINES_PER_BLOCK 64 //(ILI9341_TFTREALHEIGHT/4)
|
||||
|
||||
typedef struct {
|
||||
uint8_t cmd;
|
||||
uint8_t data[16];
|
||||
uint8_t databytes; //No of data in data; bit 7 = delay after set; 0xFF = end of cmds.
|
||||
} lcd_init_cmd_t;
|
||||
|
||||
|
||||
class ILI9341_t3DMA
|
||||
{
|
||||
public:
|
||||
ILI9341_t3DMA(uint8_t _CS = 17, uint8_t _DC = 18, uint8_t _RST = 255, uint8_t _MOSI=23, uint8_t _CLK=18, uint8_t _MISO=19, uint8_t touch_cs=32, uint8_t touch_irq=33);
|
||||
|
||||
//void setFrameBuffer(uint16_t * fb);
|
||||
//static uint16_t * getFrameBuffer(void);
|
||||
|
||||
void begin(void);
|
||||
void flipscreen(bool flip);
|
||||
bool isflipped(void);
|
||||
void start(void);
|
||||
void refresh(void);
|
||||
void refreshPrepare(void);
|
||||
void refreshFinish(void);
|
||||
//void stop();
|
||||
//void wait(void);
|
||||
uint16_t * getLineBuffer(int j);
|
||||
|
||||
void fillScreen(uint16_t color);
|
||||
void writeScreen(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16);
|
||||
void writeLine(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16);
|
||||
void writeLine(int width, int height, int stride, uint16_t *buffer);
|
||||
void drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);
|
||||
void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap);
|
||||
void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh);
|
||||
void drawText(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize);
|
||||
|
||||
void fillScreenNoDma(uint16_t color) { fillScreen(color); };
|
||||
void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap) { drawSprite(x,y,bitmap); };
|
||||
void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh) { drawSprite(x,y,bitmap,croparx,cropary,croparw,croparh); };
|
||||
void drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color) { drawRect(x,y,w,h,color); };
|
||||
void drawTextNoDma(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize) { drawText(x,y,text,fgcolor,bgcolor,doublesize); };
|
||||
|
||||
/*
|
||||
void writeScreenNoDma(const uint16_t *pcolors);
|
||||
void drawPixel(int16_t x, int16_t y, uint16_t color);
|
||||
uint16_t getPixel(int16_t x, int16_t y);
|
||||
*/
|
||||
|
||||
|
||||
void touchBegin();
|
||||
void readRo(uint16_t * oX, uint16_t * oY, uint16_t * oZ);
|
||||
bool isTouching();
|
||||
void readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ);
|
||||
void readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ);
|
||||
void callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax);
|
||||
|
||||
protected:
|
||||
bool flipped=false;
|
||||
void enableTouchIrq();
|
||||
};
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
#ifndef IOPINS_H
|
||||
#define IOPINS_H
|
||||
|
||||
// ILI9341
|
||||
//#define PIN_NUM_CS (gpio_num_t)15
|
||||
//#define PIN_NUM_CLK (gpio_num_t)14
|
||||
//#define PIN_NUM_MISO (gpio_num_t)12
|
||||
//#define PIN_NUM_MOSI (gpio_num_t)13
|
||||
//#define PIN_NUM_DC (gpio_num_t)16
|
||||
|
||||
#define TPIN_NUM_CS (gpio_num_t)32
|
||||
#define TPIN_NUM_IRQ (gpio_num_t)33
|
||||
|
||||
|
||||
#define PIN_NUM_CS (gpio_num_t)22 //17
|
||||
#define PIN_NUM_CLK (gpio_num_t)18
|
||||
#define PIN_NUM_MISO (gpio_num_t)19
|
||||
#define PIN_NUM_MOSI (gpio_num_t)23
|
||||
#define PIN_NUM_DC (gpio_num_t)21
|
||||
|
||||
// SD card SPI
|
||||
#define SPIN_NUM_CS (gpio_num_t)15
|
||||
#define SPIN_NUM_CLK (gpio_num_t)14
|
||||
#define SPIN_NUM_MISO (gpio_num_t)12
|
||||
#define SPIN_NUM_MOSI (gpio_num_t)13
|
||||
|
||||
|
||||
// I2C keyboard
|
||||
#define I2C_SCL_IO (gpio_num_t)5
|
||||
#define I2C_SDA_IO (gpio_num_t)4
|
||||
|
||||
|
||||
// Analog joystick (primary) for JOY2 and 5 extra buttons
|
||||
#define PIN_JOY2_A1X ADC2_CHANNEL_7 // 27 //ADC1_CHANNEL_0
|
||||
#define PIN_JOY2_A2Y ADC2_CHANNEL_2 // 2 //ADC1_CHANNEL_3
|
||||
#define PIN_JOY2_BTN 32
|
||||
|
||||
#define PIN_KEY_USER1 35
|
||||
#define PIN_KEY_USER2 34
|
||||
#define PIN_KEY_USER3 39
|
||||
#define PIN_KEY_USER4 36
|
||||
/*
|
||||
#define PIN_KEY_ESCAPE 23
|
||||
*/
|
||||
|
||||
// Second joystick
|
||||
/*
|
||||
#define PIN_JOY1_BTN 30
|
||||
#define PIN_JOY1_1 16
|
||||
#define PIN_JOY1_2 17
|
||||
#define PIN_JOY1_3 18
|
||||
#define PIN_JOY1_4 19
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
|
||||
#ifndef keyboard_osd_h_
|
||||
#define keyboard_osd_h_
|
||||
|
||||
extern bool virtualkeyboardIsActive(void);
|
||||
extern void drawVirtualkeyboard(void);
|
||||
extern void toggleVirtualkeyboard(bool keepOn);
|
||||
extern void handleVirtualkeyboard(void);
|
||||
|
||||
extern bool callibrationActive(void);
|
||||
extern int handleCallibration(uint16_t bClick);
|
||||
|
||||
extern bool menuActive(void);
|
||||
extern char * menuSelection(void);
|
||||
extern void toggleMenu(bool on);
|
||||
extern int handleMenu(uint16_t bClick);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "esp_wifi.h"
|
||||
#include "esp_system.h"
|
||||
#include "esp_event.h"
|
||||
#include "esp_event_loop.h"
|
||||
#include "nvs_flash.h"
|
||||
#include "driver/gpio.h"
|
||||
#include "esp_partition.h"
|
||||
|
||||
#include "go.h"
|
||||
|
||||
|
||||
int app_main(void)
|
||||
{
|
||||
printf("Test start!\n");
|
||||
|
||||
setup();
|
||||
while(1) {
|
||||
loop();
|
||||
}
|
||||
|
||||
for (int i = 10; i >= 0; i--) {
|
||||
printf("Restarting in %d seconds...\n", i);
|
||||
vTaskDelay(1000 / portTICK_PERIOD_MS);
|
||||
}
|
||||
printf("Restarting now.\n");
|
||||
fflush(stdout);
|
||||
esp_restart();
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "emu.h"
|
||||
|
||||
|
||||
#ifdef USE_ENC28J60
|
||||
#include <enc28j60.h>
|
||||
|
||||
byte ENC28J60::buffer[1514];
|
||||
//uint8_t net_mac[6] = { 0x90, 0xAD, 0xBE, 0xEF, 0x13, 0x37 };
|
||||
uint8_t net_mac[6] = { 0x2C, 0xFD, 0x13, 0x37, 0x13, 0x37 };
|
||||
|
||||
extern union _bytewordregs_ regs;
|
||||
extern uint16_t segregs[6];
|
||||
|
||||
struct netstruct {
|
||||
uint8_t enabled;
|
||||
uint8_t canrecv;
|
||||
uint16_t pktlen;
|
||||
} net;
|
||||
|
||||
void net_handler() {
|
||||
uint32_t i;
|
||||
uint16_t j;
|
||||
//if (ethif==254) return; //networking not enabled
|
||||
switch (regs.byteregs[regah]) { //function number
|
||||
case 0x00: //enable packet reception
|
||||
net.enabled = 1;
|
||||
net.canrecv = 1;
|
||||
return;
|
||||
case 0x01: //send packet of CX at DS:SI
|
||||
//if (verbose) {
|
||||
//Serial.println("Sending packet of %u bytes.", regs.wordregs[regcx]);
|
||||
//}
|
||||
//sendpkt (&RAM[ ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi]], regs.wordregs[regcx]);
|
||||
i = ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi];
|
||||
for (j=0; j<net.pktlen; j++) {
|
||||
ENC28J60::buffer[j] = read86(i++);
|
||||
}
|
||||
SPI.setClockDivider(SPI_CLOCK_ENC28J60);
|
||||
ENC28J60::packetSend(segregs[regcx]);
|
||||
SPI.setClockDivider(SPI_CLOCK_SPIRAM);
|
||||
return;
|
||||
case 0x02: //return packet info (packet buffer in DS:SI, length in CX)
|
||||
segregs[regds] = 0xD000;
|
||||
regs.wordregs[regsi] = 0x0000;
|
||||
regs.wordregs[regcx] = net.pktlen;
|
||||
return;
|
||||
case 0x03: //copy packet to final destination (given in ES:DI)
|
||||
//memcpy (&RAM[ ( (uint32_t) segregs[reges] << 4) + (uint32_t) regs.wordregs[regdi]], &RAM[0xD0000], net.pktlen);
|
||||
i = ( (uint32_t) segregs[reges] << 4) + (uint32_t) regs.wordregs[regdi];
|
||||
for (j=0; j<net.pktlen; j++) {
|
||||
write86(i++, ENC28J60::buffer[j]);
|
||||
}
|
||||
net.canrecv = 1;
|
||||
net.pktlen = 0;
|
||||
return;
|
||||
case 0x04: //disable packets
|
||||
net.enabled = 0;
|
||||
net.canrecv = 0;
|
||||
return;
|
||||
case 0x05: //DEBUG: dump packet (DS:SI) of CX bytes to stdout
|
||||
/*for (i=0; i<regs.wordregs[regcx]; i++) {
|
||||
printf ("%c", RAM[ ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi] + i]);
|
||||
}*/
|
||||
return;
|
||||
case 0x06: //DEBUG: print milestone string
|
||||
//print("PACKET DRIVER MILESTONE REACHED\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t net_read_ram(uint32_t addr32) {
|
||||
if (addr32 < 1514) return ENC28J60::buffer[addr32];
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*void net_write_ram(uint32_t addr32, uint8_t value) {
|
||||
if (addr32 < 1514) ENC28J60::buffer[addr32] = value;
|
||||
}*/
|
||||
|
||||
void net_loop() {
|
||||
uint16_t i, len;
|
||||
uint8_t cc;
|
||||
if (!net.enabled || !net.canrecv) return;
|
||||
SPI.setClockDivider(SPI_CLOCK_ENC28J60);
|
||||
len = ENC28J60::packetReceive();
|
||||
SPI.setClockDivider(SPI_CLOCK_SPIRAM);
|
||||
if (len > 0) {
|
||||
for (i=0; i<len; i++) {
|
||||
Serial.print(ENC28J60::buffer[i], HEX);
|
||||
Serial.write(' ');
|
||||
}
|
||||
Serial.println("");
|
||||
Serial.println("");
|
||||
net.canrecv = 0;
|
||||
net.pktlen = len;
|
||||
doirq(6);
|
||||
}
|
||||
}
|
||||
|
||||
void net_init() {
|
||||
uint8_t ret;
|
||||
Serial.println("enter net_init");
|
||||
//SPI.setClockDivider(SPI_CLOCK_ENC28J60);
|
||||
ret = ENC28J60::initialize(1514, net_mac, NET_PIN);
|
||||
//SPI.setClockDivider(SPI_CLOCK_LCD);
|
||||
Serial.print("net init result = ");
|
||||
Serial.println(ret);
|
||||
ENC28J60::enablePromiscuous();
|
||||
//ENC28J60::broadcast_enabled = true;
|
||||
while(1) {
|
||||
uint16_t len, i;
|
||||
//delay(100);
|
||||
//SPI.setClockDivider(SPI_CLOCK_ENC28J60);
|
||||
len = ENC28J60::packetReceive();
|
||||
//SPI.setClockDivider(SPI_CLOCK_LCD);
|
||||
if (len > 0) {
|
||||
for (i=0; i<len; i++) {
|
||||
Serial.print(ENC28J60::buffer[i], HEX);
|
||||
Serial.write(' ');
|
||||
}
|
||||
Serial.println("");
|
||||
Serial.println("");
|
||||
}
|
||||
}
|
||||
}
|
||||
#else
|
||||
uint8_t net_mac[6] = { 0x2C, 0xFD, 0x13, 0x37, 0x13, 0x37 };
|
||||
|
||||
|
||||
void net_init() {
|
||||
}
|
||||
|
||||
void net_loop() {
|
||||
}
|
||||
|
||||
void net_handler() {
|
||||
}
|
||||
uint8_t net_read_ram(uint32_t addr32) {
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/* ports.c - handles port I/O for Fake86 CPU core. it's ugly, will fix up later. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include "emu.h"
|
||||
|
||||
volatile uint16_t pit0counter = 65535;
|
||||
volatile uint32_t speakercountdown, latch42, pit0latch, pit0command, pit0divisor;
|
||||
uint8_t portram[0x400];
|
||||
uint8_t crt_controller_idx, crt_controller[256], port3D9 = 0;
|
||||
|
||||
void portout(uint16_t portnum, uint16_t value) {
|
||||
if (portnum < 0x400) portram[portnum] = value;
|
||||
switch (portnum) {
|
||||
case 0x20:
|
||||
case 0x21: //i8259
|
||||
out8259(portnum, value);
|
||||
return;
|
||||
case 0x40:
|
||||
case 0x41:
|
||||
case 0x42:
|
||||
case 0x43: //i8253
|
||||
out8253(portnum, value);
|
||||
break;
|
||||
case 0x3D4:
|
||||
crt_controller_idx = value;
|
||||
break;
|
||||
case 0x3D5:
|
||||
crt_controller[crt_controller_idx] = value;
|
||||
if ((crt_controller_idx == 0x0E) || (crt_controller_idx == 0x0F)) {
|
||||
//setcursor(((uint16_t)crt_controller[0x0E] << 8) | crt_controller[0x0F]);
|
||||
//Serial.write(27); Serial.write('['); Serial.print(crt_controller[0x0E] + 1); Serial.write(';'); Serial.print(crt_controller[0x0F] + 1); Serial.write('H');
|
||||
}
|
||||
break;
|
||||
case 0x3D9:
|
||||
port3D9 = value;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ADVANCED_CLIENT
|
||||
if ((portnum >= 0x3C0) && (portnum <= 0x3DA)) {
|
||||
uint8_t chksum;
|
||||
Serial.write(0xFF);
|
||||
Serial.write(0x04);
|
||||
outByte(portnum & 0xFF); chksum = portnum & 0xFF;
|
||||
outByte(portnum >> 8); chksum += portnum >> 8;
|
||||
outByte(value); chksum += value;
|
||||
outByte(chksum);
|
||||
Serial.write(0xFE);
|
||||
Serial.write(0x02);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef VGA
|
||||
if ((portnum >= 0x3C0) && (portnum <= 0x3DA)) outVGA(portnum, value);
|
||||
#endif
|
||||
}
|
||||
|
||||
uint16_t portin(uint16_t portnum) {
|
||||
#ifdef VGA
|
||||
if ((portnum >= 0x3C0) && (portnum <= 0x3DA)) return inVGA(portnum);
|
||||
#endif
|
||||
/* uint8_t chksum;
|
||||
Serial.write(0xFF);
|
||||
Serial.write(0x07);
|
||||
outByte(portnum & 0xFF); chksum = portnum & 0xFF;
|
||||
outByte((portnum >> 8) & 0xFF); chksum += (portnum >> 8) & 0xFF;
|
||||
outByte(chksum);
|
||||
Serial.write(0xFE);
|
||||
Serial.write(0x02);*/
|
||||
switch (portnum) {
|
||||
case 0x20:
|
||||
case 0x21: //i8259
|
||||
return (in8259(portnum));
|
||||
case 0x40:
|
||||
case 0x41:
|
||||
case 0x42:
|
||||
case 0x43: //i8253
|
||||
return in8253(portnum);
|
||||
case 0x60:
|
||||
case 0x64:
|
||||
return portram[portnum];
|
||||
case 0x3D4:
|
||||
return crt_controller_idx;
|
||||
break;
|
||||
case 0x3D5:
|
||||
return crt_controller[crt_controller_idx];
|
||||
break;
|
||||
case 0x3DA:
|
||||
port3da ^= 1;
|
||||
if (!(port3da & 1)) port3da ^= 8;
|
||||
//port3da = random(256) & 9;
|
||||
return (port3da);
|
||||
default:
|
||||
return (0xFF);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
uint8_t translatescancode(uint32_t keysym) {
|
||||
if ((keysym >= 'a') && (keysym <= 'z')) {
|
||||
keysym -= 0x20;
|
||||
}
|
||||
switch (keysym) {
|
||||
case 0xFF08: return 0x0E; //backspace
|
||||
case 0xFF09: return 0x0F; //tab
|
||||
case 0xFF0D: return 0x1C; //enter
|
||||
case 0xFF1B: return 0x01; //escape
|
||||
case 0xFF63: return 0x52; //KP 0 / insert
|
||||
case 0xFFFF: return 0x53; //KP . / delete
|
||||
case 0xFF55: return 0x49; //pgup
|
||||
case 0xFF56: return 0x51; //pgdn
|
||||
case 0xFF50: return 0x47; //home
|
||||
case 0xFF57: return 0x4F; //end
|
||||
case 'A': return 0x1E;
|
||||
case 'B': return 0x30;
|
||||
case 'C': return 0x2E;
|
||||
case 'D': return 0x20;
|
||||
case 'E': return 0x12;
|
||||
case 'F': return 0x21;
|
||||
case 'G': return 0x22;
|
||||
case 'H': return 0x23;
|
||||
case 'I': return 0x17;
|
||||
case 'J': return 0x24;
|
||||
case 'K': return 0x25;
|
||||
case 'L': return 0x26;
|
||||
case 'M': return 0x32;
|
||||
case 'N': return 0x31;
|
||||
case 'O': return 0x18;
|
||||
case 'P': return 0x19;
|
||||
case 'Q': return 0x10;
|
||||
case 'R': return 0x13;
|
||||
case 'S': return 0x1F;
|
||||
case 'T': return 0x14;
|
||||
case 'U': return 0x16;
|
||||
case 'V': return 0x2F;
|
||||
case 'W': return 0x11;
|
||||
case 'X': return 0x2D;
|
||||
case 'Y': return 0x15;
|
||||
case 'Z': return 0x2C;
|
||||
case '0': case ')': return 0x0B;
|
||||
case '1': case '!': return 0x02;
|
||||
case '2': case '@': return 0x03;
|
||||
case '3': case '#': return 0x04;
|
||||
case '4': case '$': return 0x05;
|
||||
case '5': case '%': return 0x06;
|
||||
case '6': case '^': return 0x07;
|
||||
case '7': case '&': return 0x08;
|
||||
case '8': case '*': return 0x09;
|
||||
case '9': case '(': return 0x0A;
|
||||
case '`': case '~': return 0x29;
|
||||
case '-': case '_': return 0x0C;
|
||||
case '=': case '+': return 0x0D;
|
||||
case '[': case '{': return 0x1A;
|
||||
case ']': case '}': return 0x1B;
|
||||
case '\\': case '|': return 0x2B;
|
||||
case ';': case ':': return 0x27;
|
||||
case '\'': case '"': return 0x28;
|
||||
case ' ': return 0x39;
|
||||
case ',': case '<': return 0x33;
|
||||
case '.': case '>': return 0x34;
|
||||
case '/': case '?': return 0x35;
|
||||
case 0xFFBE: return 0x3B; //F1
|
||||
case 0xFFBF: return 0x3C; //F2
|
||||
case 0xFFC0: return 0x3D; //F3
|
||||
case 0xFFC1: return 0x3E; //F4
|
||||
case 0xFFC2: return 0x3F; //F5
|
||||
case 0xFFC3: return 0x40; //F6
|
||||
case 0xFFC4: return 0x41; //F7
|
||||
case 0xFFC5: return 0x42; //F8
|
||||
case 0xFFC6: return 0x43; //F9
|
||||
case 0xFFC7: return 0x44; //F10
|
||||
case 0xFFC8: return 0x57; //F11
|
||||
case 0xFFC9: return 0x58; //F12
|
||||
case 0xFFE1: return 0x2A; //left shift
|
||||
case 0xFFE2: return 0x36; //right shift
|
||||
case 0xFFE3: case 0xFFE4: return 0x1D; //control
|
||||
case 0xFFE9: case 0xFFEA: return 0x38; //alt
|
||||
case 0xFF51: return 0x4B; //left
|
||||
case 0xFF52: return 0x48; //up
|
||||
case 0xFF53: return 0x4D; //right
|
||||
case 0xFF54: return 0x50; //down
|
||||
}
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
|
||||
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,5 @@
|
|||
# Name, Type, SubType, Offset, Size
|
||||
# Note: if you change the phy_init or app partition offset, make sure to change the offset in Kconfig.projbuild
|
||||
nvs, data, nvs, 0x9000, 0x6000
|
||||
phy_init, data, phy, 0xf000, 0x1000
|
||||
factory, app, factory, 0x10000, 2M,
|
||||
|
|
|
@ -0,0 +1,721 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Espressif IoT Development Framework Configuration
|
||||
#
|
||||
CONFIG_IDF_TARGET="esp32"
|
||||
|
||||
#
|
||||
# SDK tool configuration
|
||||
#
|
||||
CONFIG_TOOLPREFIX="xtensa-esp32-elf-"
|
||||
CONFIG_PYTHON="python"
|
||||
CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y
|
||||
|
||||
#
|
||||
# Application manager
|
||||
#
|
||||
CONFIG_APP_COMPILE_TIME_DATE=y
|
||||
CONFIG_APP_EXCLUDE_PROJECT_VER_VAR=
|
||||
CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR=
|
||||
|
||||
#
|
||||
# Bootloader config
|
||||
#
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_NONE=
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_ERROR=
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_WARN=
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG=
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE=
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL=3
|
||||
CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V=
|
||||
CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y
|
||||
CONFIG_BOOTLOADER_FACTORY_RESET=
|
||||
CONFIG_BOOTLOADER_APP_TEST=
|
||||
CONFIG_BOOTLOADER_WDT_ENABLE=y
|
||||
CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE=
|
||||
CONFIG_BOOTLOADER_WDT_TIME_MS=9000
|
||||
CONFIG_APP_ROLLBACK_ENABLE=
|
||||
|
||||
#
|
||||
# Security features
|
||||
#
|
||||
CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT=
|
||||
CONFIG_SECURE_BOOT_ENABLED=
|
||||
CONFIG_FLASH_ENCRYPTION_ENABLED=
|
||||
|
||||
#
|
||||
# Serial flasher config
|
||||
#
|
||||
CONFIG_ESPTOOLPY_PORT="/dev/cu.SLAB_USBtoUART"
|
||||
CONFIG_ESPTOOLPY_BAUD_115200B=y
|
||||
CONFIG_ESPTOOLPY_BAUD_230400B=
|
||||
CONFIG_ESPTOOLPY_BAUD_921600B=
|
||||
CONFIG_ESPTOOLPY_BAUD_2MB=
|
||||
CONFIG_ESPTOOLPY_BAUD_OTHER=
|
||||
CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
|
||||
CONFIG_ESPTOOLPY_BAUD=115200
|
||||
CONFIG_ESPTOOLPY_COMPRESSED=y
|
||||
CONFIG_FLASHMODE_QIO=
|
||||
CONFIG_FLASHMODE_QOUT=
|
||||
CONFIG_FLASHMODE_DIO=y
|
||||
CONFIG_FLASHMODE_DOUT=
|
||||
CONFIG_ESPTOOLPY_FLASHMODE="dio"
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ_80M=
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ_26M=
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ_20M=
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ="40m"
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_1MB=
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_2MB=
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_8MB=
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_16MB=
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
|
||||
CONFIG_ESPTOOLPY_BEFORE_RESET=y
|
||||
CONFIG_ESPTOOLPY_BEFORE_NORESET=
|
||||
CONFIG_ESPTOOLPY_BEFORE="default_reset"
|
||||
CONFIG_ESPTOOLPY_AFTER_RESET=y
|
||||
CONFIG_ESPTOOLPY_AFTER_NORESET=
|
||||
CONFIG_ESPTOOLPY_AFTER="hard_reset"
|
||||
CONFIG_MONITOR_BAUD_9600B=
|
||||
CONFIG_MONITOR_BAUD_57600B=
|
||||
CONFIG_MONITOR_BAUD_115200B=y
|
||||
CONFIG_MONITOR_BAUD_230400B=
|
||||
CONFIG_MONITOR_BAUD_921600B=
|
||||
CONFIG_MONITOR_BAUD_2MB=
|
||||
CONFIG_MONITOR_BAUD_OTHER=
|
||||
CONFIG_MONITOR_BAUD_OTHER_VAL=115200
|
||||
CONFIG_MONITOR_BAUD=115200
|
||||
|
||||
#
|
||||
# Partition Table
|
||||
#
|
||||
CONFIG_PARTITION_TABLE_SINGLE_APP=
|
||||
CONFIG_PARTITION_TABLE_TWO_OTA=
|
||||
CONFIG_PARTITION_TABLE_CUSTOM=y
|
||||
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
|
||||
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
|
||||
CONFIG_PARTITION_TABLE_OFFSET=0x8000
|
||||
CONFIG_PARTITION_TABLE_MD5=y
|
||||
|
||||
#
|
||||
# Compiler options
|
||||
#
|
||||
CONFIG_OPTIMIZATION_LEVEL_DEBUG=
|
||||
CONFIG_OPTIMIZATION_LEVEL_RELEASE=y
|
||||
CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
|
||||
CONFIG_OPTIMIZATION_ASSERTIONS_SILENT=
|
||||
CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED=
|
||||
CONFIG_CXX_EXCEPTIONS=
|
||||
CONFIG_STACK_CHECK_NONE=y
|
||||
CONFIG_STACK_CHECK_NORM=
|
||||
CONFIG_STACK_CHECK_STRONG=
|
||||
CONFIG_STACK_CHECK_ALL=
|
||||
CONFIG_STACK_CHECK=
|
||||
CONFIG_WARN_WRITE_STRINGS=
|
||||
CONFIG_DISABLE_GCC8_WARNINGS=
|
||||
|
||||
#
|
||||
# Component config
|
||||
#
|
||||
|
||||
#
|
||||
# Application Level Tracing
|
||||
#
|
||||
CONFIG_ESP32_APPTRACE_DEST_TRAX=
|
||||
CONFIG_ESP32_APPTRACE_DEST_NONE=y
|
||||
CONFIG_ESP32_APPTRACE_ENABLE=
|
||||
CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
|
||||
CONFIG_AWS_IOT_SDK=
|
||||
|
||||
#
|
||||
# Bluetooth
|
||||
#
|
||||
CONFIG_BT_ENABLED=
|
||||
CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0
|
||||
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0
|
||||
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0
|
||||
CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0
|
||||
CONFIG_BT_RESERVE_DRAM=0
|
||||
|
||||
#
|
||||
# Driver configurations
|
||||
#
|
||||
|
||||
#
|
||||
# ADC configuration
|
||||
#
|
||||
CONFIG_ADC_FORCE_XPD_FSM=
|
||||
CONFIG_ADC2_DISABLE_DAC=y
|
||||
|
||||
#
|
||||
# SPI configuration
|
||||
#
|
||||
CONFIG_SPI_MASTER_IN_IRAM=
|
||||
CONFIG_SPI_MASTER_ISR_IN_IRAM=y
|
||||
CONFIG_SPI_SLAVE_IN_IRAM=
|
||||
CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
|
||||
|
||||
#
|
||||
# eFuse Bit Manager
|
||||
#
|
||||
CONFIG_EFUSE_CUSTOM_TABLE=
|
||||
CONFIG_EFUSE_VIRTUAL=
|
||||
CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE=
|
||||
CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y
|
||||
CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT=
|
||||
CONFIG_EFUSE_MAX_BLK_LEN=192
|
||||
|
||||
#
|
||||
# ESP32-specific
|
||||
#
|
||||
CONFIG_IDF_TARGET_ESP32=y
|
||||
CONFIG_ESP32_DEFAULT_CPU_FREQ_80=
|
||||
CONFIG_ESP32_DEFAULT_CPU_FREQ_160=
|
||||
CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
|
||||
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
|
||||
CONFIG_SPIRAM_SUPPORT=y
|
||||
|
||||
#
|
||||
# SPI RAM config
|
||||
#
|
||||
CONFIG_SPIRAM_BOOT_INIT=y
|
||||
CONFIG_SPIRAM_IGNORE_NOTFOUND=
|
||||
CONFIG_SPIRAM_USE_MEMMAP=
|
||||
CONFIG_SPIRAM_USE_CAPS_ALLOC=y
|
||||
CONFIG_SPIRAM_USE_MALLOC=
|
||||
CONFIG_SPIRAM_TYPE_AUTO=y
|
||||
CONFIG_SPIRAM_TYPE_ESPPSRAM32=
|
||||
CONFIG_SPIRAM_TYPE_ESPPSRAM64=
|
||||
CONFIG_SPIRAM_SIZE=-1
|
||||
CONFIG_SPIRAM_SPEED_40M=y
|
||||
CONFIG_SPIRAM_MEMTEST=y
|
||||
CONFIG_SPIRAM_CACHE_WORKAROUND=y
|
||||
CONFIG_SPIRAM_BANKSWITCH_ENABLE=y
|
||||
CONFIG_SPIRAM_BANKSWITCH_RESERVE=8
|
||||
CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST=
|
||||
CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=
|
||||
CONFIG_PICO_PSRAM_CS_IO=10
|
||||
CONFIG_MEMMAP_TRACEMEM=
|
||||
CONFIG_MEMMAP_TRACEMEM_TWOBANKS=
|
||||
CONFIG_ESP32_TRAX=
|
||||
CONFIG_TRACEMEM_RESERVE_DRAM=0x0
|
||||
CONFIG_TWO_UNIVERSAL_MAC_ADDRESS=
|
||||
CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y
|
||||
CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4
|
||||
CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
|
||||
CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
|
||||
CONFIG_MAIN_TASK_STACK_SIZE=3584
|
||||
CONFIG_IPC_TASK_STACK_SIZE=1024
|
||||
CONFIG_TIMER_TASK_STACK_SIZE=3584
|
||||
CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
|
||||
CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF=
|
||||
CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR=
|
||||
CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF=
|
||||
CONFIG_NEWLIB_STDIN_LINE_ENDING_LF=
|
||||
CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
|
||||
CONFIG_NEWLIB_NANO_FORMAT=
|
||||
CONFIG_CONSOLE_UART_DEFAULT=y
|
||||
CONFIG_CONSOLE_UART_CUSTOM=
|
||||
CONFIG_CONSOLE_UART_NONE=
|
||||
CONFIG_CONSOLE_UART_NUM=0
|
||||
CONFIG_CONSOLE_UART_BAUDRATE=115200
|
||||
CONFIG_ULP_COPROC_ENABLED=
|
||||
CONFIG_ULP_COPROC_RESERVE_MEM=0
|
||||
CONFIG_ESP32_PANIC_PRINT_HALT=
|
||||
CONFIG_ESP32_PANIC_PRINT_REBOOT=y
|
||||
CONFIG_ESP32_PANIC_SILENT_REBOOT=
|
||||
CONFIG_ESP32_PANIC_GDBSTUB=
|
||||
CONFIG_ESP32_DEBUG_OCDAWARE=y
|
||||
CONFIG_ESP32_DEBUG_STUBS_ENABLE=y
|
||||
CONFIG_INT_WDT=y
|
||||
CONFIG_INT_WDT_TIMEOUT_MS=300
|
||||
CONFIG_INT_WDT_CHECK_CPU1=y
|
||||
CONFIG_TASK_WDT=y
|
||||
CONFIG_TASK_WDT_PANIC=
|
||||
CONFIG_TASK_WDT_TIMEOUT_S=5
|
||||
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
|
||||
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
|
||||
CONFIG_BROWNOUT_DET=y
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_0=y
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_1=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_2=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_3=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_4=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_5=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_6=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_7=
|
||||
CONFIG_BROWNOUT_DET_LVL=0
|
||||
CONFIG_REDUCE_PHY_TX_POWER=y
|
||||
CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
|
||||
CONFIG_ESP32_TIME_SYSCALL_USE_RTC=
|
||||
CONFIG_ESP32_TIME_SYSCALL_USE_FRC1=
|
||||
CONFIG_ESP32_TIME_SYSCALL_USE_NONE=
|
||||
CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
|
||||
CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL=
|
||||
CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC=
|
||||
CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256=
|
||||
CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
CONFIG_ESP32_XTAL_FREQ_26=
|
||||
CONFIG_ESP32_XTAL_FREQ_AUTO=
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_DISABLE_BASIC_ROM_CONSOLE=
|
||||
CONFIG_NO_BLOBS=
|
||||
CONFIG_ESP_TIMER_PROFILING=
|
||||
CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS=
|
||||
CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
|
||||
|
||||
#
|
||||
# Wi-Fi
|
||||
#
|
||||
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
|
||||
CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
|
||||
CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
|
||||
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=
|
||||
CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
|
||||
CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
|
||||
CONFIG_ESP32_WIFI_CSI_ENABLED=
|
||||
CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
|
||||
CONFIG_ESP32_WIFI_TX_BA_WIN=6
|
||||
CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
|
||||
CONFIG_ESP32_WIFI_RX_BA_WIN=6
|
||||
CONFIG_ESP32_WIFI_NVS_ENABLED=y
|
||||
CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
|
||||
CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1=
|
||||
CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
|
||||
CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
|
||||
CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE=
|
||||
CONFIG_ESP32_WIFI_IRAM_OPT=y
|
||||
|
||||
#
|
||||
# PHY
|
||||
#
|
||||
CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
|
||||
CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION=
|
||||
CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
|
||||
CONFIG_ESP32_PHY_MAX_TX_POWER=20
|
||||
|
||||
#
|
||||
# Power Management
|
||||
#
|
||||
CONFIG_PM_ENABLE=
|
||||
|
||||
#
|
||||
# ADC-Calibration
|
||||
#
|
||||
CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
|
||||
CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
|
||||
CONFIG_ADC_CAL_LUT_ENABLE=y
|
||||
|
||||
#
|
||||
# Event Loop Library
|
||||
#
|
||||
CONFIG_EVENT_LOOP_PROFILING=
|
||||
|
||||
#
|
||||
# ESP HTTP client
|
||||
#
|
||||
CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=
|
||||
|
||||
#
|
||||
# HTTP Server
|
||||
#
|
||||
CONFIG_HTTPD_MAX_REQ_HDR_LEN=512
|
||||
CONFIG_HTTPD_MAX_URI_LEN=512
|
||||
CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
|
||||
|
||||
#
|
||||
# ESP HTTPS OTA
|
||||
#
|
||||
CONFIG_OTA_ALLOW_HTTP=
|
||||
|
||||
#
|
||||
# Core dump
|
||||
#
|
||||
CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=
|
||||
CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=
|
||||
CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
|
||||
CONFIG_ESP32_ENABLE_COREDUMP=
|
||||
|
||||
#
|
||||
# Ethernet
|
||||
#
|
||||
CONFIG_DMA_RX_BUF_NUM=10
|
||||
CONFIG_DMA_TX_BUF_NUM=10
|
||||
CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y
|
||||
CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000
|
||||
CONFIG_EMAC_TASK_PRIORITY=20
|
||||
CONFIG_EMAC_TASK_STACK_SIZE=3072
|
||||
|
||||
#
|
||||
# FAT Filesystem support
|
||||
#
|
||||
CONFIG_FATFS_CODEPAGE_DYNAMIC=
|
||||
CONFIG_FATFS_CODEPAGE_437=y
|
||||
CONFIG_FATFS_CODEPAGE_720=
|
||||
CONFIG_FATFS_CODEPAGE_737=
|
||||
CONFIG_FATFS_CODEPAGE_771=
|
||||
CONFIG_FATFS_CODEPAGE_775=
|
||||
CONFIG_FATFS_CODEPAGE_850=
|
||||
CONFIG_FATFS_CODEPAGE_852=
|
||||
CONFIG_FATFS_CODEPAGE_855=
|
||||
CONFIG_FATFS_CODEPAGE_857=
|
||||
CONFIG_FATFS_CODEPAGE_860=
|
||||
CONFIG_FATFS_CODEPAGE_861=
|
||||
CONFIG_FATFS_CODEPAGE_862=
|
||||
CONFIG_FATFS_CODEPAGE_863=
|
||||
CONFIG_FATFS_CODEPAGE_864=
|
||||
CONFIG_FATFS_CODEPAGE_865=
|
||||
CONFIG_FATFS_CODEPAGE_866=
|
||||
CONFIG_FATFS_CODEPAGE_869=
|
||||
CONFIG_FATFS_CODEPAGE_932=
|
||||
CONFIG_FATFS_CODEPAGE_936=
|
||||
CONFIG_FATFS_CODEPAGE_949=
|
||||
CONFIG_FATFS_CODEPAGE_950=
|
||||
CONFIG_FATFS_CODEPAGE=437
|
||||
CONFIG_FATFS_LFN_NONE=
|
||||
CONFIG_FATFS_LFN_HEAP=
|
||||
CONFIG_FATFS_LFN_STACK=y
|
||||
CONFIG_FATFS_MAX_LFN=255
|
||||
CONFIG_FATFS_API_ENCODING_ANSI_OEM=y
|
||||
CONFIG_FATFS_API_ENCODING_UTF_16=
|
||||
CONFIG_FATFS_API_ENCODING_UTF_8=
|
||||
CONFIG_FATFS_FS_LOCK=0
|
||||
CONFIG_FATFS_TIMEOUT_MS=10000
|
||||
CONFIG_FATFS_PER_FILE_CACHE=y
|
||||
CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y
|
||||
|
||||
#
|
||||
# Modbus configuration
|
||||
#
|
||||
CONFIG_MB_QUEUE_LENGTH=20
|
||||
CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048
|
||||
CONFIG_MB_SERIAL_BUF_SIZE=256
|
||||
CONFIG_MB_SERIAL_TASK_PRIO=10
|
||||
CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=
|
||||
CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
|
||||
CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
|
||||
CONFIG_MB_CONTROLLER_STACK_SIZE=4096
|
||||
CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
|
||||
CONFIG_MB_TIMER_PORT_ENABLED=y
|
||||
CONFIG_MB_TIMER_GROUP=0
|
||||
CONFIG_MB_TIMER_INDEX=0
|
||||
|
||||
#
|
||||
# FreeRTOS
|
||||
#
|
||||
CONFIG_FREERTOS_UNICORE=
|
||||
CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
|
||||
CONFIG_FREERTOS_CORETIMER_0=y
|
||||
CONFIG_FREERTOS_CORETIMER_1=
|
||||
CONFIG_FREERTOS_HZ=100
|
||||
CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
|
||||
CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE=
|
||||
CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL=
|
||||
CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
|
||||
CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=
|
||||
CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
|
||||
CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
|
||||
CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
|
||||
CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE=
|
||||
CONFIG_FREERTOS_ASSERT_DISABLE=
|
||||
CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
|
||||
CONFIG_FREERTOS_ISR_STACKSIZE=1536
|
||||
CONFIG_FREERTOS_LEGACY_HOOKS=
|
||||
CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
|
||||
CONFIG_SUPPORT_STATIC_ALLOCATION=y
|
||||
CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK=
|
||||
CONFIG_TIMER_TASK_PRIORITY=1
|
||||
CONFIG_TIMER_TASK_STACK_DEPTH=2048
|
||||
CONFIG_TIMER_QUEUE_LENGTH=10
|
||||
CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
|
||||
CONFIG_FREERTOS_USE_TRACE_FACILITY=
|
||||
CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=
|
||||
CONFIG_FREERTOS_DEBUG_INTERNALS=
|
||||
|
||||
#
|
||||
# Heap memory debugging
|
||||
#
|
||||
CONFIG_HEAP_POISONING_DISABLED=y
|
||||
CONFIG_HEAP_POISONING_LIGHT=
|
||||
CONFIG_HEAP_POISONING_COMPREHENSIVE=
|
||||
CONFIG_HEAP_TRACING=
|
||||
|
||||
#
|
||||
# libsodium
|
||||
#
|
||||
CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y
|
||||
|
||||
#
|
||||
# Log output
|
||||
#
|
||||
CONFIG_LOG_DEFAULT_LEVEL_NONE=
|
||||
CONFIG_LOG_DEFAULT_LEVEL_ERROR=
|
||||
CONFIG_LOG_DEFAULT_LEVEL_WARN=
|
||||
CONFIG_LOG_DEFAULT_LEVEL_INFO=y
|
||||
CONFIG_LOG_DEFAULT_LEVEL_DEBUG=
|
||||
CONFIG_LOG_DEFAULT_LEVEL_VERBOSE=
|
||||
CONFIG_LOG_DEFAULT_LEVEL=3
|
||||
CONFIG_LOG_COLORS=y
|
||||
|
||||
#
|
||||
# LWIP
|
||||
#
|
||||
CONFIG_L2_TO_L3_COPY=
|
||||
CONFIG_LWIP_IRAM_OPTIMIZATION=
|
||||
CONFIG_LWIP_MAX_SOCKETS=10
|
||||
CONFIG_USE_ONLY_LWIP_SELECT=
|
||||
CONFIG_LWIP_SO_REUSE=y
|
||||
CONFIG_LWIP_SO_REUSE_RXTOALL=y
|
||||
CONFIG_LWIP_SO_RCVBUF=
|
||||
CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1
|
||||
CONFIG_LWIP_IP_FRAG=
|
||||
CONFIG_LWIP_IP_REASSEMBLY=
|
||||
CONFIG_LWIP_STATS=
|
||||
CONFIG_LWIP_ETHARP_TRUST_IP_MAC=
|
||||
CONFIG_ESP_GRATUITOUS_ARP=y
|
||||
CONFIG_GARP_TMR_INTERVAL=60
|
||||
CONFIG_TCPIP_RECVMBOX_SIZE=32
|
||||
CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
|
||||
CONFIG_LWIP_DHCP_RESTORE_LAST_IP=
|
||||
|
||||
#
|
||||
# DHCP server
|
||||
#
|
||||
CONFIG_LWIP_DHCPS_LEASE_UNIT=60
|
||||
CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
|
||||
CONFIG_LWIP_AUTOIP=
|
||||
CONFIG_LWIP_NETIF_LOOPBACK=y
|
||||
CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8
|
||||
|
||||
#
|
||||
# TCP
|
||||
#
|
||||
CONFIG_LWIP_MAX_ACTIVE_TCP=16
|
||||
CONFIG_LWIP_MAX_LISTENING_TCP=16
|
||||
CONFIG_TCP_MAXRTX=12
|
||||
CONFIG_TCP_SYNMAXRTX=6
|
||||
CONFIG_TCP_MSS=1436
|
||||
CONFIG_TCP_MSL=60000
|
||||
CONFIG_TCP_SND_BUF_DEFAULT=5744
|
||||
CONFIG_TCP_WND_DEFAULT=5744
|
||||
CONFIG_TCP_RECVMBOX_SIZE=6
|
||||
CONFIG_TCP_QUEUE_OOSEQ=y
|
||||
CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES=
|
||||
CONFIG_TCP_OVERSIZE_MSS=y
|
||||
CONFIG_TCP_OVERSIZE_QUARTER_MSS=
|
||||
CONFIG_TCP_OVERSIZE_DISABLE=
|
||||
|
||||
#
|
||||
# UDP
|
||||
#
|
||||
CONFIG_LWIP_MAX_UDP_PCBS=16
|
||||
CONFIG_UDP_RECVMBOX_SIZE=6
|
||||
CONFIG_TCPIP_TASK_STACK_SIZE=3072
|
||||
CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
|
||||
CONFIG_TCPIP_TASK_AFFINITY_CPU0=
|
||||
CONFIG_TCPIP_TASK_AFFINITY_CPU1=
|
||||
CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
|
||||
CONFIG_PPP_SUPPORT=
|
||||
|
||||
#
|
||||
# ICMP
|
||||
#
|
||||
CONFIG_LWIP_MULTICAST_PING=
|
||||
CONFIG_LWIP_BROADCAST_PING=
|
||||
|
||||
#
|
||||
# LWIP RAW API
|
||||
#
|
||||
CONFIG_LWIP_MAX_RAW_PCBS=16
|
||||
|
||||
#
|
||||
# mbedTLS
|
||||
#
|
||||
CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y
|
||||
CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC=
|
||||
CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC=
|
||||
CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC=
|
||||
CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384
|
||||
CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=
|
||||
CONFIG_MBEDTLS_DEBUG=
|
||||
CONFIG_MBEDTLS_HARDWARE_AES=y
|
||||
CONFIG_MBEDTLS_HARDWARE_MPI=
|
||||
CONFIG_MBEDTLS_HARDWARE_SHA=
|
||||
CONFIG_MBEDTLS_HAVE_TIME=y
|
||||
CONFIG_MBEDTLS_HAVE_TIME_DATE=
|
||||
CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y
|
||||
CONFIG_MBEDTLS_TLS_SERVER_ONLY=
|
||||
CONFIG_MBEDTLS_TLS_CLIENT_ONLY=
|
||||
CONFIG_MBEDTLS_TLS_DISABLED=
|
||||
CONFIG_MBEDTLS_TLS_SERVER=y
|
||||
CONFIG_MBEDTLS_TLS_CLIENT=y
|
||||
CONFIG_MBEDTLS_TLS_ENABLED=y
|
||||
|
||||
#
|
||||
# TLS Key Exchange Methods
|
||||
#
|
||||
CONFIG_MBEDTLS_PSK_MODES=
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
|
||||
CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
|
||||
CONFIG_MBEDTLS_SSL_PROTO_SSL3=
|
||||
CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
|
||||
CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
|
||||
CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
|
||||
CONFIG_MBEDTLS_SSL_PROTO_DTLS=
|
||||
CONFIG_MBEDTLS_SSL_ALPN=y
|
||||
CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y
|
||||
|
||||
#
|
||||
# Symmetric Ciphers
|
||||
#
|
||||
CONFIG_MBEDTLS_AES_C=y
|
||||
CONFIG_MBEDTLS_CAMELLIA_C=
|
||||
CONFIG_MBEDTLS_DES_C=
|
||||
CONFIG_MBEDTLS_RC4_DISABLED=y
|
||||
CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT=
|
||||
CONFIG_MBEDTLS_RC4_ENABLED=
|
||||
CONFIG_MBEDTLS_BLOWFISH_C=
|
||||
CONFIG_MBEDTLS_XTEA_C=
|
||||
CONFIG_MBEDTLS_CCM_C=y
|
||||
CONFIG_MBEDTLS_GCM_C=y
|
||||
CONFIG_MBEDTLS_RIPEMD160_C=
|
||||
|
||||
#
|
||||
# Certificates
|
||||
#
|
||||
CONFIG_MBEDTLS_PEM_PARSE_C=y
|
||||
CONFIG_MBEDTLS_PEM_WRITE_C=y
|
||||
CONFIG_MBEDTLS_X509_CRL_PARSE_C=y
|
||||
CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
|
||||
CONFIG_MBEDTLS_ECP_C=y
|
||||
CONFIG_MBEDTLS_ECDH_C=y
|
||||
CONFIG_MBEDTLS_ECDSA_C=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
|
||||
|
||||
#
|
||||
# mDNS
|
||||
#
|
||||
CONFIG_MDNS_MAX_SERVICES=10
|
||||
|
||||
#
|
||||
# ESP-MQTT Configurations
|
||||
#
|
||||
CONFIG_MQTT_PROTOCOL_311=y
|
||||
CONFIG_MQTT_TRANSPORT_SSL=y
|
||||
CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
|
||||
CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
|
||||
CONFIG_MQTT_USE_CUSTOM_CONFIG=
|
||||
CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED=
|
||||
CONFIG_MQTT_CUSTOM_OUTBOX=
|
||||
|
||||
#
|
||||
# NVS
|
||||
#
|
||||
|
||||
#
|
||||
# OpenSSL
|
||||
#
|
||||
CONFIG_OPENSSL_DEBUG=
|
||||
CONFIG_OPENSSL_ASSERT_DO_NOTHING=y
|
||||
CONFIG_OPENSSL_ASSERT_EXIT=
|
||||
|
||||
#
|
||||
# PThreads
|
||||
#
|
||||
CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
|
||||
CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
|
||||
CONFIG_PTHREAD_STACK_MIN=768
|
||||
CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y
|
||||
CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0=
|
||||
CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1=
|
||||
CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
|
||||
CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
|
||||
|
||||
#
|
||||
# SPI Flash driver
|
||||
#
|
||||
CONFIG_SPI_FLASH_VERIFY_WRITE=
|
||||
CONFIG_SPI_FLASH_ENABLE_COUNTERS=
|
||||
CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
|
||||
|
||||
#
|
||||
# SPIFFS Configuration
|
||||
#
|
||||
CONFIG_SPIFFS_MAX_PARTITIONS=3
|
||||
|
||||
#
|
||||
# SPIFFS Cache Configuration
|
||||
#
|
||||
CONFIG_SPIFFS_CACHE=y
|
||||
CONFIG_SPIFFS_CACHE_WR=y
|
||||
CONFIG_SPIFFS_CACHE_STATS=
|
||||
CONFIG_SPIFFS_PAGE_CHECK=y
|
||||
CONFIG_SPIFFS_GC_MAX_RUNS=10
|
||||
CONFIG_SPIFFS_GC_STATS=
|
||||
CONFIG_SPIFFS_PAGE_SIZE=256
|
||||
CONFIG_SPIFFS_OBJ_NAME_LEN=32
|
||||
CONFIG_SPIFFS_USE_MAGIC=y
|
||||
CONFIG_SPIFFS_USE_MAGIC_LENGTH=y
|
||||
CONFIG_SPIFFS_META_LENGTH=4
|
||||
CONFIG_SPIFFS_USE_MTIME=y
|
||||
|
||||
#
|
||||
# Debug Configuration
|
||||
#
|
||||
CONFIG_SPIFFS_DBG=
|
||||
CONFIG_SPIFFS_API_DBG=
|
||||
CONFIG_SPIFFS_GC_DBG=
|
||||
CONFIG_SPIFFS_CACHE_DBG=
|
||||
CONFIG_SPIFFS_CHECK_DBG=
|
||||
CONFIG_SPIFFS_TEST_VISUALISATION=
|
||||
|
||||
#
|
||||
# TCP/IP Adapter
|
||||
#
|
||||
CONFIG_IP_LOST_TIMER_INTERVAL=120
|
||||
CONFIG_TCPIP_LWIP=y
|
||||
|
||||
#
|
||||
# Unity unit testing library
|
||||
#
|
||||
CONFIG_UNITY_ENABLE_FLOAT=y
|
||||
CONFIG_UNITY_ENABLE_DOUBLE=y
|
||||
CONFIG_UNITY_ENABLE_COLOR=
|
||||
CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
|
||||
CONFIG_UNITY_ENABLE_FIXTURE=
|
||||
|
||||
#
|
||||
# Virtual file system
|
||||
#
|
||||
CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
|
||||
CONFIG_SUPPORT_TERMIOS=y
|
||||
|
||||
#
|
||||
# Wear Levelling
|
||||
#
|
||||
CONFIG_WL_SECTOR_SIZE_512=
|
||||
CONFIG_WL_SECTOR_SIZE_4096=y
|
||||
CONFIG_WL_SECTOR_SIZE=4096
|
||||
|
|
@ -0,0 +1,705 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Espressif IoT Development Framework Configuration
|
||||
#
|
||||
CONFIG_IDF_TARGET="esp32"
|
||||
|
||||
#
|
||||
# SDK tool configuration
|
||||
#
|
||||
CONFIG_TOOLPREFIX="xtensa-esp32-elf-"
|
||||
CONFIG_PYTHON="python"
|
||||
CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y
|
||||
|
||||
#
|
||||
# Application manager
|
||||
#
|
||||
CONFIG_APP_COMPILE_TIME_DATE=y
|
||||
|
||||
#
|
||||
# Bootloader config
|
||||
#
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_NONE=
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_ERROR=
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_WARN=
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG=
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE=
|
||||
CONFIG_LOG_BOOTLOADER_LEVEL=3
|
||||
CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V=
|
||||
CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y
|
||||
CONFIG_BOOTLOADER_FACTORY_RESET=
|
||||
CONFIG_BOOTLOADER_APP_TEST=
|
||||
CONFIG_BOOTLOADER_WDT_ENABLE=y
|
||||
CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE=
|
||||
CONFIG_BOOTLOADER_WDT_TIME_MS=9000
|
||||
|
||||
#
|
||||
# Security features
|
||||
#
|
||||
CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT=
|
||||
CONFIG_SECURE_BOOT_ENABLED=
|
||||
CONFIG_FLASH_ENCRYPTION_ENABLED=
|
||||
|
||||
#
|
||||
# Serial flasher config
|
||||
#
|
||||
CONFIG_ESPTOOLPY_PORT="/dev/cu.SLAB_USBtoUART"
|
||||
CONFIG_ESPTOOLPY_BAUD_115200B=y
|
||||
CONFIG_ESPTOOLPY_BAUD_230400B=
|
||||
CONFIG_ESPTOOLPY_BAUD_921600B=
|
||||
CONFIG_ESPTOOLPY_BAUD_2MB=
|
||||
CONFIG_ESPTOOLPY_BAUD_OTHER=
|
||||
CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
|
||||
CONFIG_ESPTOOLPY_BAUD=115200
|
||||
CONFIG_ESPTOOLPY_COMPRESSED=y
|
||||
CONFIG_FLASHMODE_QIO=
|
||||
CONFIG_FLASHMODE_QOUT=
|
||||
CONFIG_FLASHMODE_DIO=y
|
||||
CONFIG_FLASHMODE_DOUT=
|
||||
CONFIG_ESPTOOLPY_FLASHMODE="dio"
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ_80M=
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ_26M=
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ_20M=
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ="40m"
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_1MB=
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_2MB=
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_8MB=
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_16MB=
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
|
||||
CONFIG_ESPTOOLPY_BEFORE_RESET=y
|
||||
CONFIG_ESPTOOLPY_BEFORE_NORESET=
|
||||
CONFIG_ESPTOOLPY_BEFORE="default_reset"
|
||||
CONFIG_ESPTOOLPY_AFTER_RESET=y
|
||||
CONFIG_ESPTOOLPY_AFTER_NORESET=
|
||||
CONFIG_ESPTOOLPY_AFTER="hard_reset"
|
||||
CONFIG_MONITOR_BAUD_9600B=
|
||||
CONFIG_MONITOR_BAUD_57600B=
|
||||
CONFIG_MONITOR_BAUD_115200B=y
|
||||
CONFIG_MONITOR_BAUD_230400B=
|
||||
CONFIG_MONITOR_BAUD_921600B=
|
||||
CONFIG_MONITOR_BAUD_2MB=
|
||||
CONFIG_MONITOR_BAUD_OTHER=
|
||||
CONFIG_MONITOR_BAUD_OTHER_VAL=115200
|
||||
CONFIG_MONITOR_BAUD=115200
|
||||
|
||||
#
|
||||
# Partition Table
|
||||
#
|
||||
CONFIG_PARTITION_TABLE_SINGLE_APP=
|
||||
CONFIG_PARTITION_TABLE_TWO_OTA=
|
||||
CONFIG_PARTITION_TABLE_CUSTOM=y
|
||||
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
|
||||
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
|
||||
CONFIG_PARTITION_TABLE_OFFSET=0x8000
|
||||
CONFIG_PARTITION_TABLE_MD5=y
|
||||
|
||||
#
|
||||
# Compiler options
|
||||
#
|
||||
CONFIG_OPTIMIZATION_LEVEL_DEBUG=
|
||||
CONFIG_OPTIMIZATION_LEVEL_RELEASE=y
|
||||
CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
|
||||
CONFIG_OPTIMIZATION_ASSERTIONS_SILENT=
|
||||
CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED=
|
||||
CONFIG_CXX_EXCEPTIONS=
|
||||
CONFIG_STACK_CHECK_NONE=y
|
||||
CONFIG_STACK_CHECK_NORM=
|
||||
CONFIG_STACK_CHECK_STRONG=
|
||||
CONFIG_STACK_CHECK_ALL=
|
||||
CONFIG_STACK_CHECK=
|
||||
CONFIG_WARN_WRITE_STRINGS=
|
||||
CONFIG_DISABLE_GCC8_WARNINGS=
|
||||
|
||||
#
|
||||
# Component config
|
||||
#
|
||||
|
||||
#
|
||||
# Application Level Tracing
|
||||
#
|
||||
CONFIG_ESP32_APPTRACE_DEST_TRAX=
|
||||
CONFIG_ESP32_APPTRACE_DEST_NONE=y
|
||||
CONFIG_ESP32_APPTRACE_ENABLE=
|
||||
CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
|
||||
CONFIG_AWS_IOT_SDK=
|
||||
|
||||
#
|
||||
# Bluetooth
|
||||
#
|
||||
CONFIG_BT_ENABLED=
|
||||
CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0
|
||||
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0
|
||||
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0
|
||||
CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0
|
||||
CONFIG_BT_RESERVE_DRAM=0
|
||||
|
||||
#
|
||||
# Driver configurations
|
||||
#
|
||||
|
||||
#
|
||||
# ADC configuration
|
||||
#
|
||||
CONFIG_ADC_FORCE_XPD_FSM=
|
||||
CONFIG_ADC2_DISABLE_DAC=y
|
||||
|
||||
#
|
||||
# SPI configuration
|
||||
#
|
||||
CONFIG_SPI_MASTER_IN_IRAM=
|
||||
CONFIG_SPI_MASTER_ISR_IN_IRAM=y
|
||||
CONFIG_SPI_SLAVE_IN_IRAM=
|
||||
CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
|
||||
|
||||
#
|
||||
# ESP32-specific
|
||||
#
|
||||
CONFIG_IDF_TARGET_ESP32=y
|
||||
CONFIG_ESP32_DEFAULT_CPU_FREQ_80=
|
||||
CONFIG_ESP32_DEFAULT_CPU_FREQ_160=
|
||||
CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
|
||||
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
|
||||
CONFIG_SPIRAM_SUPPORT=y
|
||||
|
||||
#
|
||||
# SPI RAM config
|
||||
#
|
||||
CONFIG_SPIRAM_BOOT_INIT=y
|
||||
CONFIG_SPIRAM_IGNORE_NOTFOUND=
|
||||
CONFIG_SPIRAM_USE_MEMMAP=
|
||||
CONFIG_SPIRAM_USE_CAPS_ALLOC=y
|
||||
CONFIG_SPIRAM_USE_MALLOC=
|
||||
CONFIG_SPIRAM_TYPE_AUTO=y
|
||||
CONFIG_SPIRAM_TYPE_ESPPSRAM32=
|
||||
CONFIG_SPIRAM_TYPE_ESPPSRAM64=
|
||||
CONFIG_SPIRAM_SIZE=-1
|
||||
CONFIG_SPIRAM_SPEED_40M=y
|
||||
CONFIG_SPIRAM_MEMTEST=y
|
||||
CONFIG_SPIRAM_CACHE_WORKAROUND=y
|
||||
CONFIG_SPIRAM_BANKSWITCH_ENABLE=y
|
||||
CONFIG_SPIRAM_BANKSWITCH_RESERVE=8
|
||||
CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST=
|
||||
CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=
|
||||
CONFIG_MEMMAP_TRACEMEM=
|
||||
CONFIG_MEMMAP_TRACEMEM_TWOBANKS=
|
||||
CONFIG_ESP32_TRAX=
|
||||
CONFIG_TRACEMEM_RESERVE_DRAM=0x0
|
||||
|
||||
#
|
||||
# Core dump
|
||||
#
|
||||
CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=
|
||||
CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=
|
||||
CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
|
||||
CONFIG_ESP32_ENABLE_COREDUMP=
|
||||
CONFIG_TWO_UNIVERSAL_MAC_ADDRESS=
|
||||
CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y
|
||||
CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4
|
||||
CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
|
||||
CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
|
||||
CONFIG_MAIN_TASK_STACK_SIZE=3584
|
||||
CONFIG_IPC_TASK_STACK_SIZE=1024
|
||||
CONFIG_TIMER_TASK_STACK_SIZE=3584
|
||||
CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
|
||||
CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF=
|
||||
CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR=
|
||||
CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF=
|
||||
CONFIG_NEWLIB_STDIN_LINE_ENDING_LF=
|
||||
CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
|
||||
CONFIG_NEWLIB_NANO_FORMAT=
|
||||
CONFIG_CONSOLE_UART_DEFAULT=y
|
||||
CONFIG_CONSOLE_UART_CUSTOM=
|
||||
CONFIG_CONSOLE_UART_NONE=
|
||||
CONFIG_CONSOLE_UART_NUM=0
|
||||
CONFIG_CONSOLE_UART_BAUDRATE=115200
|
||||
CONFIG_ULP_COPROC_ENABLED=
|
||||
CONFIG_ULP_COPROC_RESERVE_MEM=0
|
||||
CONFIG_ESP32_PANIC_PRINT_HALT=
|
||||
CONFIG_ESP32_PANIC_PRINT_REBOOT=y
|
||||
CONFIG_ESP32_PANIC_SILENT_REBOOT=
|
||||
CONFIG_ESP32_PANIC_GDBSTUB=
|
||||
CONFIG_ESP32_DEBUG_OCDAWARE=y
|
||||
CONFIG_ESP32_DEBUG_STUBS_ENABLE=y
|
||||
CONFIG_INT_WDT=y
|
||||
CONFIG_INT_WDT_TIMEOUT_MS=300
|
||||
CONFIG_INT_WDT_CHECK_CPU1=y
|
||||
CONFIG_TASK_WDT=y
|
||||
CONFIG_TASK_WDT_PANIC=
|
||||
CONFIG_TASK_WDT_TIMEOUT_S=5
|
||||
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
|
||||
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
|
||||
CONFIG_BROWNOUT_DET=y
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_0=y
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_1=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_2=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_3=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_4=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_5=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_6=
|
||||
CONFIG_BROWNOUT_DET_LVL_SEL_7=
|
||||
CONFIG_BROWNOUT_DET_LVL=0
|
||||
CONFIG_REDUCE_PHY_TX_POWER=y
|
||||
CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
|
||||
CONFIG_ESP32_TIME_SYSCALL_USE_RTC=
|
||||
CONFIG_ESP32_TIME_SYSCALL_USE_FRC1=
|
||||
CONFIG_ESP32_TIME_SYSCALL_USE_NONE=
|
||||
CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
|
||||
CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL=
|
||||
CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC=
|
||||
CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256=
|
||||
CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
CONFIG_ESP32_XTAL_FREQ_26=
|
||||
CONFIG_ESP32_XTAL_FREQ_AUTO=
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_DISABLE_BASIC_ROM_CONSOLE=
|
||||
CONFIG_NO_BLOBS=
|
||||
CONFIG_ESP_TIMER_PROFILING=
|
||||
CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS=
|
||||
CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
|
||||
|
||||
#
|
||||
# Wi-Fi
|
||||
#
|
||||
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
|
||||
CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
|
||||
CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
|
||||
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=
|
||||
CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
|
||||
CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
|
||||
CONFIG_ESP32_WIFI_CSI_ENABLED=
|
||||
CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
|
||||
CONFIG_ESP32_WIFI_TX_BA_WIN=6
|
||||
CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
|
||||
CONFIG_ESP32_WIFI_RX_BA_WIN=6
|
||||
CONFIG_ESP32_WIFI_NVS_ENABLED=y
|
||||
CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
|
||||
CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1=
|
||||
CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
|
||||
CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE=
|
||||
|
||||
#
|
||||
# PHY
|
||||
#
|
||||
CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
|
||||
CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION=
|
||||
CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
|
||||
CONFIG_ESP32_PHY_MAX_TX_POWER=20
|
||||
|
||||
#
|
||||
# Power Management
|
||||
#
|
||||
CONFIG_PM_ENABLE=
|
||||
|
||||
#
|
||||
# ADC-Calibration
|
||||
#
|
||||
CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
|
||||
CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
|
||||
CONFIG_ADC_CAL_LUT_ENABLE=y
|
||||
|
||||
#
|
||||
# Event Loop Library
|
||||
#
|
||||
CONFIG_EVENT_LOOP_PROFILING=
|
||||
|
||||
#
|
||||
# ESP HTTP client
|
||||
#
|
||||
CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=
|
||||
|
||||
#
|
||||
# HTTP Server
|
||||
#
|
||||
CONFIG_HTTPD_MAX_REQ_HDR_LEN=512
|
||||
CONFIG_HTTPD_MAX_URI_LEN=512
|
||||
|
||||
#
|
||||
# Ethernet
|
||||
#
|
||||
CONFIG_DMA_RX_BUF_NUM=10
|
||||
CONFIG_DMA_TX_BUF_NUM=10
|
||||
CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y
|
||||
CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000
|
||||
CONFIG_EMAC_TASK_PRIORITY=20
|
||||
CONFIG_EMAC_TASK_STACK_SIZE=3072
|
||||
|
||||
#
|
||||
# FAT Filesystem support
|
||||
#
|
||||
CONFIG_FATFS_CODEPAGE_DYNAMIC=
|
||||
CONFIG_FATFS_CODEPAGE_437=y
|
||||
CONFIG_FATFS_CODEPAGE_720=
|
||||
CONFIG_FATFS_CODEPAGE_737=
|
||||
CONFIG_FATFS_CODEPAGE_771=
|
||||
CONFIG_FATFS_CODEPAGE_775=
|
||||
CONFIG_FATFS_CODEPAGE_850=
|
||||
CONFIG_FATFS_CODEPAGE_852=
|
||||
CONFIG_FATFS_CODEPAGE_855=
|
||||
CONFIG_FATFS_CODEPAGE_857=
|
||||
CONFIG_FATFS_CODEPAGE_860=
|
||||
CONFIG_FATFS_CODEPAGE_861=
|
||||
CONFIG_FATFS_CODEPAGE_862=
|
||||
CONFIG_FATFS_CODEPAGE_863=
|
||||
CONFIG_FATFS_CODEPAGE_864=
|
||||
CONFIG_FATFS_CODEPAGE_865=
|
||||
CONFIG_FATFS_CODEPAGE_866=
|
||||
CONFIG_FATFS_CODEPAGE_869=
|
||||
CONFIG_FATFS_CODEPAGE_932=
|
||||
CONFIG_FATFS_CODEPAGE_936=
|
||||
CONFIG_FATFS_CODEPAGE_949=
|
||||
CONFIG_FATFS_CODEPAGE_950=
|
||||
CONFIG_FATFS_CODEPAGE=437
|
||||
CONFIG_FATFS_LFN_NONE=
|
||||
CONFIG_FATFS_LFN_HEAP=
|
||||
CONFIG_FATFS_LFN_STACK=y
|
||||
CONFIG_FATFS_MAX_LFN=255
|
||||
CONFIG_FATFS_API_ENCODING_ANSI_OEM=y
|
||||
CONFIG_FATFS_API_ENCODING_UTF_16=
|
||||
CONFIG_FATFS_API_ENCODING_UTF_8=
|
||||
CONFIG_FATFS_FS_LOCK=0
|
||||
CONFIG_FATFS_TIMEOUT_MS=10000
|
||||
CONFIG_FATFS_PER_FILE_CACHE=y
|
||||
CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y
|
||||
|
||||
#
|
||||
# Modbus configuration
|
||||
#
|
||||
CONFIG_MB_UART_RXD=22
|
||||
CONFIG_MB_UART_TXD=23
|
||||
CONFIG_MB_UART_RTS=18
|
||||
CONFIG_MB_QUEUE_LENGTH=20
|
||||
CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048
|
||||
CONFIG_MB_SERIAL_BUF_SIZE=256
|
||||
CONFIG_MB_SERIAL_TASK_PRIO=10
|
||||
CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=
|
||||
CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
|
||||
CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
|
||||
CONFIG_MB_CONTROLLER_STACK_SIZE=4096
|
||||
CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
|
||||
CONFIG_MB_TIMER_PORT_ENABLED=y
|
||||
CONFIG_MB_TIMER_GROUP=0
|
||||
CONFIG_MB_TIMER_INDEX=0
|
||||
|
||||
#
|
||||
# FreeRTOS
|
||||
#
|
||||
CONFIG_FREERTOS_UNICORE=
|
||||
CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
|
||||
CONFIG_FREERTOS_CORETIMER_0=y
|
||||
CONFIG_FREERTOS_CORETIMER_1=
|
||||
CONFIG_FREERTOS_HZ=100
|
||||
CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
|
||||
CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE=
|
||||
CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL=
|
||||
CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
|
||||
CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=
|
||||
CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
|
||||
CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
|
||||
CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
|
||||
CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE=
|
||||
CONFIG_FREERTOS_ASSERT_DISABLE=
|
||||
CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
|
||||
CONFIG_FREERTOS_ISR_STACKSIZE=1536
|
||||
CONFIG_FREERTOS_LEGACY_HOOKS=
|
||||
CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
|
||||
CONFIG_SUPPORT_STATIC_ALLOCATION=y
|
||||
CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK=
|
||||
CONFIG_TIMER_TASK_PRIORITY=1
|
||||
CONFIG_TIMER_TASK_STACK_DEPTH=2048
|
||||
CONFIG_TIMER_QUEUE_LENGTH=10
|
||||
CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
|
||||
CONFIG_FREERTOS_USE_TRACE_FACILITY=
|
||||
CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=
|
||||
CONFIG_FREERTOS_DEBUG_INTERNALS=
|
||||
|
||||
#
|
||||
# Heap memory debugging
|
||||
#
|
||||
CONFIG_HEAP_POISONING_DISABLED=y
|
||||
CONFIG_HEAP_POISONING_LIGHT=
|
||||
CONFIG_HEAP_POISONING_COMPREHENSIVE=
|
||||
CONFIG_HEAP_TRACING=
|
||||
|
||||
#
|
||||
# libsodium
|
||||
#
|
||||
CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y
|
||||
|
||||
#
|
||||
# Log output
|
||||
#
|
||||
CONFIG_LOG_DEFAULT_LEVEL_NONE=
|
||||
CONFIG_LOG_DEFAULT_LEVEL_ERROR=
|
||||
CONFIG_LOG_DEFAULT_LEVEL_WARN=
|
||||
CONFIG_LOG_DEFAULT_LEVEL_INFO=y
|
||||
CONFIG_LOG_DEFAULT_LEVEL_DEBUG=
|
||||
CONFIG_LOG_DEFAULT_LEVEL_VERBOSE=
|
||||
CONFIG_LOG_DEFAULT_LEVEL=3
|
||||
CONFIG_LOG_COLORS=y
|
||||
|
||||
#
|
||||
# LWIP
|
||||
#
|
||||
CONFIG_L2_TO_L3_COPY=
|
||||
CONFIG_LWIP_IRAM_OPTIMIZATION=
|
||||
CONFIG_LWIP_MAX_SOCKETS=10
|
||||
CONFIG_USE_ONLY_LWIP_SELECT=
|
||||
CONFIG_LWIP_SO_REUSE=y
|
||||
CONFIG_LWIP_SO_REUSE_RXTOALL=y
|
||||
CONFIG_LWIP_SO_RCVBUF=
|
||||
CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1
|
||||
CONFIG_LWIP_IP_FRAG=
|
||||
CONFIG_LWIP_IP_REASSEMBLY=
|
||||
CONFIG_LWIP_STATS=
|
||||
CONFIG_LWIP_ETHARP_TRUST_IP_MAC=
|
||||
CONFIG_ESP_GRATUITOUS_ARP=y
|
||||
CONFIG_GARP_TMR_INTERVAL=60
|
||||
CONFIG_TCPIP_RECVMBOX_SIZE=32
|
||||
CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
|
||||
CONFIG_LWIP_DHCP_RESTORE_LAST_IP=
|
||||
|
||||
#
|
||||
# DHCP server
|
||||
#
|
||||
CONFIG_LWIP_DHCPS_LEASE_UNIT=60
|
||||
CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
|
||||
CONFIG_LWIP_AUTOIP=
|
||||
CONFIG_LWIP_NETIF_LOOPBACK=y
|
||||
CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8
|
||||
|
||||
#
|
||||
# TCP
|
||||
#
|
||||
CONFIG_LWIP_MAX_ACTIVE_TCP=16
|
||||
CONFIG_LWIP_MAX_LISTENING_TCP=16
|
||||
CONFIG_TCP_MAXRTX=12
|
||||
CONFIG_TCP_SYNMAXRTX=6
|
||||
CONFIG_TCP_MSS=1436
|
||||
CONFIG_TCP_MSL=60000
|
||||
CONFIG_TCP_SND_BUF_DEFAULT=5744
|
||||
CONFIG_TCP_WND_DEFAULT=5744
|
||||
CONFIG_TCP_RECVMBOX_SIZE=6
|
||||
CONFIG_TCP_QUEUE_OOSEQ=y
|
||||
CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES=
|
||||
CONFIG_TCP_OVERSIZE_MSS=y
|
||||
CONFIG_TCP_OVERSIZE_QUARTER_MSS=
|
||||
CONFIG_TCP_OVERSIZE_DISABLE=
|
||||
|
||||
#
|
||||
# UDP
|
||||
#
|
||||
CONFIG_LWIP_MAX_UDP_PCBS=16
|
||||
CONFIG_UDP_RECVMBOX_SIZE=6
|
||||
CONFIG_TCPIP_TASK_STACK_SIZE=3072
|
||||
CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
|
||||
CONFIG_TCPIP_TASK_AFFINITY_CPU0=
|
||||
CONFIG_TCPIP_TASK_AFFINITY_CPU1=
|
||||
CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
|
||||
CONFIG_PPP_SUPPORT=
|
||||
|
||||
#
|
||||
# ICMP
|
||||
#
|
||||
CONFIG_LWIP_MULTICAST_PING=
|
||||
CONFIG_LWIP_BROADCAST_PING=
|
||||
|
||||
#
|
||||
# LWIP RAW API
|
||||
#
|
||||
CONFIG_LWIP_MAX_RAW_PCBS=16
|
||||
|
||||
#
|
||||
# mbedTLS
|
||||
#
|
||||
CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y
|
||||
CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC=
|
||||
CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC=
|
||||
CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC=
|
||||
CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384
|
||||
CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=
|
||||
CONFIG_MBEDTLS_DEBUG=
|
||||
CONFIG_MBEDTLS_HARDWARE_AES=y
|
||||
CONFIG_MBEDTLS_HARDWARE_MPI=
|
||||
CONFIG_MBEDTLS_HARDWARE_SHA=
|
||||
CONFIG_MBEDTLS_HAVE_TIME=y
|
||||
CONFIG_MBEDTLS_HAVE_TIME_DATE=
|
||||
CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y
|
||||
CONFIG_MBEDTLS_TLS_SERVER_ONLY=
|
||||
CONFIG_MBEDTLS_TLS_CLIENT_ONLY=
|
||||
CONFIG_MBEDTLS_TLS_DISABLED=
|
||||
CONFIG_MBEDTLS_TLS_SERVER=y
|
||||
CONFIG_MBEDTLS_TLS_CLIENT=y
|
||||
CONFIG_MBEDTLS_TLS_ENABLED=y
|
||||
|
||||
#
|
||||
# TLS Key Exchange Methods
|
||||
#
|
||||
CONFIG_MBEDTLS_PSK_MODES=
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y
|
||||
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
|
||||
CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
|
||||
CONFIG_MBEDTLS_SSL_PROTO_SSL3=
|
||||
CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
|
||||
CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
|
||||
CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
|
||||
CONFIG_MBEDTLS_SSL_PROTO_DTLS=
|
||||
CONFIG_MBEDTLS_SSL_ALPN=y
|
||||
CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y
|
||||
|
||||
#
|
||||
# Symmetric Ciphers
|
||||
#
|
||||
CONFIG_MBEDTLS_AES_C=y
|
||||
CONFIG_MBEDTLS_CAMELLIA_C=
|
||||
CONFIG_MBEDTLS_DES_C=
|
||||
CONFIG_MBEDTLS_RC4_DISABLED=y
|
||||
CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT=
|
||||
CONFIG_MBEDTLS_RC4_ENABLED=
|
||||
CONFIG_MBEDTLS_BLOWFISH_C=
|
||||
CONFIG_MBEDTLS_XTEA_C=
|
||||
CONFIG_MBEDTLS_CCM_C=y
|
||||
CONFIG_MBEDTLS_GCM_C=y
|
||||
CONFIG_MBEDTLS_RIPEMD160_C=
|
||||
|
||||
#
|
||||
# Certificates
|
||||
#
|
||||
CONFIG_MBEDTLS_PEM_PARSE_C=y
|
||||
CONFIG_MBEDTLS_PEM_WRITE_C=y
|
||||
CONFIG_MBEDTLS_X509_CRL_PARSE_C=y
|
||||
CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
|
||||
CONFIG_MBEDTLS_ECP_C=y
|
||||
CONFIG_MBEDTLS_ECDH_C=y
|
||||
CONFIG_MBEDTLS_ECDSA_C=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
|
||||
|
||||
#
|
||||
# mDNS
|
||||
#
|
||||
CONFIG_MDNS_MAX_SERVICES=10
|
||||
|
||||
#
|
||||
# ESP-MQTT Configurations
|
||||
#
|
||||
CONFIG_MQTT_PROTOCOL_311=y
|
||||
CONFIG_MQTT_TRANSPORT_SSL=y
|
||||
CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
|
||||
CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
|
||||
CONFIG_MQTT_USE_CUSTOM_CONFIG=
|
||||
CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED=
|
||||
CONFIG_MQTT_CUSTOM_OUTBOX=
|
||||
|
||||
#
|
||||
# NVS
|
||||
#
|
||||
|
||||
#
|
||||
# OpenSSL
|
||||
#
|
||||
CONFIG_OPENSSL_DEBUG=
|
||||
CONFIG_OPENSSL_ASSERT_DO_NOTHING=y
|
||||
CONFIG_OPENSSL_ASSERT_EXIT=
|
||||
|
||||
#
|
||||
# PThreads
|
||||
#
|
||||
CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
|
||||
CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
|
||||
CONFIG_PTHREAD_STACK_MIN=768
|
||||
CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y
|
||||
CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0=
|
||||
CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1=
|
||||
CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
|
||||
CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
|
||||
|
||||
#
|
||||
# SPI Flash driver
|
||||
#
|
||||
CONFIG_SPI_FLASH_VERIFY_WRITE=
|
||||
CONFIG_SPI_FLASH_ENABLE_COUNTERS=
|
||||
CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
|
||||
CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
|
||||
CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS=
|
||||
CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED=
|
||||
|
||||
#
|
||||
# SPIFFS Configuration
|
||||
#
|
||||
CONFIG_SPIFFS_MAX_PARTITIONS=3
|
||||
|
||||
#
|
||||
# SPIFFS Cache Configuration
|
||||
#
|
||||
CONFIG_SPIFFS_CACHE=y
|
||||
CONFIG_SPIFFS_CACHE_WR=y
|
||||
CONFIG_SPIFFS_CACHE_STATS=
|
||||
CONFIG_SPIFFS_PAGE_CHECK=y
|
||||
CONFIG_SPIFFS_GC_MAX_RUNS=10
|
||||
CONFIG_SPIFFS_GC_STATS=
|
||||
CONFIG_SPIFFS_PAGE_SIZE=256
|
||||
CONFIG_SPIFFS_OBJ_NAME_LEN=32
|
||||
CONFIG_SPIFFS_USE_MAGIC=y
|
||||
CONFIG_SPIFFS_USE_MAGIC_LENGTH=y
|
||||
CONFIG_SPIFFS_META_LENGTH=4
|
||||
CONFIG_SPIFFS_USE_MTIME=y
|
||||
|
||||
#
|
||||
# Debug Configuration
|
||||
#
|
||||
CONFIG_SPIFFS_DBG=
|
||||
CONFIG_SPIFFS_API_DBG=
|
||||
CONFIG_SPIFFS_GC_DBG=
|
||||
CONFIG_SPIFFS_CACHE_DBG=
|
||||
CONFIG_SPIFFS_CHECK_DBG=
|
||||
CONFIG_SPIFFS_TEST_VISUALISATION=
|
||||
|
||||
#
|
||||
# TCP/IP Adapter
|
||||
#
|
||||
CONFIG_IP_LOST_TIMER_INTERVAL=120
|
||||
CONFIG_TCPIP_LWIP=y
|
||||
|
||||
#
|
||||
# Unity unit testing library
|
||||
#
|
||||
CONFIG_UNITY_ENABLE_FLOAT=y
|
||||
CONFIG_UNITY_ENABLE_DOUBLE=y
|
||||
CONFIG_UNITY_ENABLE_COLOR=
|
||||
CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
|
||||
CONFIG_UNITY_ENABLE_FIXTURE=
|
||||
|
||||
#
|
||||
# Virtual file system
|
||||
#
|
||||
CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
|
||||
CONFIG_SUPPORT_TERMIOS=y
|
||||
|
||||
#
|
||||
# Wear Levelling
|
||||
#
|
||||
CONFIG_WL_SECTOR_SIZE_512=
|
||||
CONFIG_WL_SECTOR_SIZE_4096=y
|
||||
CONFIG_WL_SECTOR_SIZE=4096
|
||||
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,9 @@
|
|||
#
|
||||
# This is a project Makefile. It is assumed the directory this Makefile resides in is a
|
||||
# project subdirectory.
|
||||
#
|
||||
|
||||
PROJECT_NAME := espcastaway
|
||||
|
||||
include $(IDF_PATH)/make/project.mk
|
||||
|
||||
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,11 @@
|
|||
#
|
||||
# Main component makefile.
|
||||
#
|
||||
# This Makefile can be left empty. By default, it will take the sources in the
|
||||
# src/ directory, compile them and link them into lib(subdirectory_name).a
|
||||
# in the build directory. This behaviour is entirely configurable,
|
||||
# please read the ESP-IDF documents if you need to do this.
|
||||
#
|
||||
|
||||
COMPONENT_ADD_INCLUDEDIRS := .
|
||||
COMPONENT_SRCDIRS := .
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "esp32-hal-dac.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "rom/ets_sys.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_intr.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/sens_reg.h"
|
||||
#include "esp32-hal-gpio.h"
|
||||
|
||||
|
||||
void IRAM_ATTR __dacWrite(uint8_t pin, uint8_t value)
|
||||
{
|
||||
if(pin < 25 || pin > 26){
|
||||
return;//not dac pin
|
||||
}
|
||||
pinMode(pin, ANALOG);
|
||||
uint8_t channel = pin - 25;
|
||||
|
||||
|
||||
//Disable Tone
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL1_REG, SENS_SW_TONE_EN);
|
||||
|
||||
if (channel) {
|
||||
//Disable Channel Tone
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN2_M);
|
||||
//Set the Dac value
|
||||
SET_PERI_REG_BITS(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_DAC, value, RTC_IO_PDAC2_DAC_S); //dac_output
|
||||
//Channel output enable
|
||||
SET_PERI_REG_MASK(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_XPD_DAC | RTC_IO_PDAC2_DAC_XPD_FORCE);
|
||||
} else {
|
||||
//Disable Channel Tone
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN1_M);
|
||||
//Set the Dac value
|
||||
SET_PERI_REG_BITS(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_DAC, value, RTC_IO_PDAC1_DAC_S); //dac_output
|
||||
//Channel output enable
|
||||
SET_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_XPD_DAC | RTC_IO_PDAC1_DAC_XPD_FORCE);
|
||||
}
|
||||
}
|
||||
|
||||
extern void dacWrite(uint8_t pin, uint8_t value) __attribute__ ((weak, alias("__dacWrite")));
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
Arduino.h - Main include file for the Arduino SDK
|
||||
Copyright (c) 2005-2013 Arduino Team. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef MAIN_ESP32_HAL_DAC_H_
|
||||
#define MAIN_ESP32_HAL_DAC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//#include "esp32-hal.h"
|
||||
#include "driver/gpio.h"
|
||||
|
||||
void dacWrite(uint8_t pin, uint8_t value);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* MAIN_ESP32_HAL_DAC_H_ */
|
||||
|
|
@ -0,0 +1,293 @@
|
|||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "esp32-hal-timer.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/xtensa_api.h"
|
||||
#include "freertos/task.h"
|
||||
#include "rom/ets_sys.h"
|
||||
#include "soc/timer_group_struct.h"
|
||||
#include "soc/dport_reg.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_intr.h"
|
||||
|
||||
#define HWTIMER_LOCK() portENTER_CRITICAL(timer->lock)
|
||||
#define HWTIMER_UNLOCK() portEXIT_CRITICAL(timer->lock)
|
||||
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t alarm_en: 1; /*When set alarm is enabled*/
|
||||
uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/
|
||||
uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/
|
||||
uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/
|
||||
uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/
|
||||
uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/
|
||||
uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/
|
||||
};
|
||||
uint32_t val;
|
||||
} config;
|
||||
uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
|
||||
uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/
|
||||
uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
|
||||
uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
|
||||
uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
|
||||
uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
|
||||
uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/
|
||||
uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/
|
||||
} hw_timer_reg_t;
|
||||
|
||||
typedef struct hw_timer_s {
|
||||
hw_timer_reg_t * dev;
|
||||
uint8_t num;
|
||||
uint8_t group;
|
||||
uint8_t timer;
|
||||
portMUX_TYPE lock;
|
||||
} hw_timer_t;
|
||||
|
||||
static hw_timer_t hw_timer[4] = {
|
||||
{(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE),0,0,0,portMUX_INITIALIZER_UNLOCKED},
|
||||
{(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x0024),1,0,1,portMUX_INITIALIZER_UNLOCKED},
|
||||
{(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1000),2,1,0,portMUX_INITIALIZER_UNLOCKED},
|
||||
{(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1024),3,1,1,portMUX_INITIALIZER_UNLOCKED}
|
||||
};
|
||||
|
||||
typedef void (*voidFuncPtr)(void);
|
||||
static voidFuncPtr __timerInterruptHandlers[4] = {0,0,0,0};
|
||||
|
||||
void IRAM_ATTR __timerISR(void * arg){
|
||||
uint32_t s0 = TIMERG0.int_st_timers.val;
|
||||
uint32_t s1 = TIMERG1.int_st_timers.val;
|
||||
TIMERG0.int_clr_timers.val = s0;
|
||||
TIMERG1.int_clr_timers.val = s1;
|
||||
uint8_t status = (s1 & 3) << 2 | (s0 & 3);
|
||||
uint8_t i = 4;
|
||||
//restart the timers that should autoreload
|
||||
while(i--){
|
||||
hw_timer_reg_t * dev = hw_timer[i].dev;
|
||||
if((status & (1 << i)) && dev->config.autoreload){
|
||||
dev->config.alarm_en = 1;
|
||||
}
|
||||
}
|
||||
i = 4;
|
||||
//call callbacks
|
||||
while(i--){
|
||||
if(__timerInterruptHandlers[i] && status & (1 << i)){
|
||||
__timerInterruptHandlers[i]();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t timerRead(hw_timer_t *timer){
|
||||
timer->dev->update = 1;
|
||||
uint64_t h = timer->dev->cnt_high;
|
||||
uint64_t l = timer->dev->cnt_low;
|
||||
return (h << 32) | l;
|
||||
}
|
||||
|
||||
uint64_t timerAlarmRead(hw_timer_t *timer){
|
||||
uint64_t h = timer->dev->alarm_high;
|
||||
uint64_t l = timer->dev->alarm_low;
|
||||
return (h << 32) | l;
|
||||
}
|
||||
|
||||
void timerWrite(hw_timer_t *timer, uint64_t val){
|
||||
timer->dev->load_high = (uint32_t) (val >> 32);
|
||||
timer->dev->load_low = (uint32_t) (val);
|
||||
timer->dev->reload = 1;
|
||||
}
|
||||
|
||||
void timerAlarmWrite(hw_timer_t *timer, uint64_t alarm_value, bool autoreload){
|
||||
timer->dev->alarm_high = (uint32_t) (alarm_value >> 32);
|
||||
timer->dev->alarm_low = (uint32_t) alarm_value;
|
||||
timer->dev->config.autoreload = autoreload;
|
||||
}
|
||||
|
||||
void timerSetConfig(hw_timer_t *timer, uint32_t config){
|
||||
timer->dev->config.val = config;
|
||||
}
|
||||
|
||||
uint32_t timerGetConfig(hw_timer_t *timer){
|
||||
return timer->dev->config.val;
|
||||
}
|
||||
|
||||
void timerSetCountUp(hw_timer_t *timer, bool countUp){
|
||||
timer->dev->config.increase = countUp;
|
||||
}
|
||||
|
||||
bool timerGetCountUp(hw_timer_t *timer){
|
||||
return timer->dev->config.increase;
|
||||
}
|
||||
|
||||
void timerSetAutoReload(hw_timer_t *timer, bool autoreload){
|
||||
timer->dev->config.autoreload = autoreload;
|
||||
}
|
||||
|
||||
bool timerGetAutoReload(hw_timer_t *timer){
|
||||
return timer->dev->config.autoreload;
|
||||
}
|
||||
|
||||
void timerSetDivider(hw_timer_t *timer, uint16_t divider){//2 to 65536
|
||||
if(!divider){
|
||||
divider = 0xFFFF;
|
||||
} else if(divider == 1){
|
||||
divider = 2;
|
||||
}
|
||||
int timer_en = timer->dev->config.enable;
|
||||
timer->dev->config.enable = 0;
|
||||
timer->dev->config.divider = divider;
|
||||
timer->dev->config.enable = timer_en;
|
||||
}
|
||||
|
||||
uint16_t timerGetDivider(hw_timer_t *timer){
|
||||
return timer->dev->config.divider;
|
||||
}
|
||||
|
||||
void timerStart(hw_timer_t *timer){
|
||||
timer->dev->config.enable = 1;
|
||||
}
|
||||
|
||||
void timerStop(hw_timer_t *timer){
|
||||
timer->dev->config.enable = 0;
|
||||
}
|
||||
|
||||
void timerRestart(hw_timer_t *timer){
|
||||
timer->dev->config.enable = 0;
|
||||
timer->dev->config.enable = 1;
|
||||
}
|
||||
|
||||
bool timerStarted(hw_timer_t *timer){
|
||||
return timer->dev->config.enable;
|
||||
}
|
||||
|
||||
void timerAlarmEnable(hw_timer_t *timer){
|
||||
timer->dev->config.alarm_en = 1;
|
||||
}
|
||||
|
||||
void timerAlarmDisable(hw_timer_t *timer){
|
||||
timer->dev->config.alarm_en = 0;
|
||||
}
|
||||
|
||||
bool timerAlarmEnabled(hw_timer_t *timer){
|
||||
return timer->dev->config.alarm_en;
|
||||
}
|
||||
|
||||
hw_timer_t * timerBegin(uint8_t num, uint16_t divider, bool countUp){
|
||||
if(num > 3){
|
||||
return NULL;
|
||||
}
|
||||
hw_timer_t * timer = &hw_timer[num];
|
||||
if(timer->group) {
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN);
|
||||
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST);
|
||||
TIMERG1.int_ena.val &= ~BIT(timer->timer);
|
||||
} else {
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN);
|
||||
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST);
|
||||
TIMERG0.int_ena.val &= ~BIT(timer->timer);
|
||||
}
|
||||
timer->dev->config.enable = 0;
|
||||
timerSetDivider(timer, divider);
|
||||
timerSetCountUp(timer, countUp);
|
||||
timerSetAutoReload(timer, false);
|
||||
timerAttachInterrupt(timer, NULL, false);
|
||||
timerWrite(timer, 0);
|
||||
timer->dev->config.enable = 1;
|
||||
return timer;
|
||||
}
|
||||
|
||||
void timerEnd(hw_timer_t *timer){
|
||||
timer->dev->config.enable = 0;
|
||||
timerAttachInterrupt(timer, NULL, false);
|
||||
}
|
||||
|
||||
void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge){
|
||||
static bool initialized = false;
|
||||
static intr_handle_t intr_handle = NULL;
|
||||
if(intr_handle){
|
||||
esp_intr_disable(intr_handle);
|
||||
}
|
||||
if(fn == NULL){
|
||||
timer->dev->config.level_int_en = 0;
|
||||
timer->dev->config.edge_int_en = 0;
|
||||
timer->dev->config.alarm_en = 0;
|
||||
if(timer->num & 2){
|
||||
TIMERG1.int_ena.val &= ~BIT(timer->timer);
|
||||
} else {
|
||||
TIMERG0.int_ena.val &= ~BIT(timer->timer);
|
||||
}
|
||||
__timerInterruptHandlers[timer->num] = NULL;
|
||||
} else {
|
||||
__timerInterruptHandlers[timer->num] = fn;
|
||||
timer->dev->config.level_int_en = edge?0:1;//When set, an alarm will generate a level type interrupt.
|
||||
timer->dev->config.edge_int_en = edge?1:0;//When set, an alarm will generate an edge type interrupt.
|
||||
int intr_source = 0;
|
||||
if(!edge){
|
||||
if(timer->group){
|
||||
intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer->timer;
|
||||
} else {
|
||||
intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer->timer;
|
||||
}
|
||||
} else {
|
||||
if(timer->group){
|
||||
intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer->timer;
|
||||
} else {
|
||||
intr_source = ETS_TG0_T0_EDGE_INTR_SOURCE + timer->timer;
|
||||
}
|
||||
}
|
||||
if(!initialized){
|
||||
initialized = true;
|
||||
esp_intr_alloc(intr_source, (int)(ESP_INTR_FLAG_IRAM|ESP_INTR_FLAG_LOWMED|ESP_INTR_FLAG_EDGE), __timerISR, NULL, &intr_handle);
|
||||
} else {
|
||||
intr_matrix_set(esp_intr_get_cpu(intr_handle), intr_source, esp_intr_get_intno(intr_handle));
|
||||
}
|
||||
if(timer->group){
|
||||
TIMERG1.int_ena.val |= BIT(timer->timer);
|
||||
} else {
|
||||
TIMERG0.int_ena.val |= BIT(timer->timer);
|
||||
}
|
||||
}
|
||||
if(intr_handle){
|
||||
esp_intr_enable(intr_handle);
|
||||
}
|
||||
}
|
||||
|
||||
void timerDetachInterrupt(hw_timer_t *timer){
|
||||
timerAttachInterrupt(timer, NULL, false);
|
||||
}
|
||||
|
||||
uint64_t timerReadMicros(hw_timer_t *timer){
|
||||
uint64_t timer_val = timerRead(timer);
|
||||
uint16_t div = timerGetDivider(timer);
|
||||
return timer_val * div / 80;
|
||||
}
|
||||
|
||||
double timerReadSeconds(hw_timer_t *timer){
|
||||
uint64_t timer_val = timerRead(timer);
|
||||
uint16_t div = timerGetDivider(timer);
|
||||
return (double)timer_val * div / 80000000;
|
||||
}
|
||||
|
||||
uint64_t timerAlarmReadMicros(hw_timer_t *timer){
|
||||
uint64_t timer_val = timerAlarmRead(timer);
|
||||
uint16_t div = timerGetDivider(timer);
|
||||
return timer_val * div / 80;
|
||||
}
|
||||
|
||||
double timerAlarmReadSeconds(hw_timer_t *timer){
|
||||
uint64_t timer_val = timerAlarmRead(timer);
|
||||
uint16_t div = timerGetDivider(timer);
|
||||
return (double)timer_val * div / 80000000;
|
||||
}
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
Arduino.h - Main include file for the Arduino SDK
|
||||
Copyright (c) 2005-2013 Arduino Team. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef MAIN_ESP32_HAL_TIMER_H_
|
||||
#define MAIN_ESP32_HAL_TIMER_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//#include "esp32-hal.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
|
||||
struct hw_timer_s;
|
||||
typedef struct hw_timer_s hw_timer_t;
|
||||
|
||||
hw_timer_t * timerBegin(uint8_t timer, uint16_t divider, bool countUp);
|
||||
void timerEnd(hw_timer_t *timer);
|
||||
|
||||
void timerSetConfig(hw_timer_t *timer, uint32_t config);
|
||||
uint32_t timerGetConfig(hw_timer_t *timer);
|
||||
|
||||
void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge);
|
||||
void timerDetachInterrupt(hw_timer_t *timer);
|
||||
|
||||
void timerStart(hw_timer_t *timer);
|
||||
void timerStop(hw_timer_t *timer);
|
||||
void timerRestart(hw_timer_t *timer);
|
||||
void timerWrite(hw_timer_t *timer, uint64_t val);
|
||||
void timerSetDivider(hw_timer_t *timer, uint16_t divider);
|
||||
void timerSetCountUp(hw_timer_t *timer, bool countUp);
|
||||
void timerSetAutoReload(hw_timer_t *timer, bool autoreload);
|
||||
|
||||
bool timerStarted(hw_timer_t *timer);
|
||||
uint64_t timerRead(hw_timer_t *timer);
|
||||
uint64_t timerReadMicros(hw_timer_t *timer);
|
||||
double timerReadSeconds(hw_timer_t *timer);
|
||||
uint16_t timerGetDivider(hw_timer_t *timer);
|
||||
bool timerGetCountUp(hw_timer_t *timer);
|
||||
bool timerGetAutoReload(hw_timer_t *timer);
|
||||
|
||||
void timerAlarmEnable(hw_timer_t *timer);
|
||||
void timerAlarmDisable(hw_timer_t *timer);
|
||||
void timerAlarmWrite(hw_timer_t *timer, uint64_t interruptAt, bool autoreload);
|
||||
|
||||
bool timerAlarmEnabled(hw_timer_t *timer);
|
||||
uint64_t timerAlarmRead(hw_timer_t *timer);
|
||||
uint64_t timerAlarmReadMicros(hw_timer_t *timer);
|
||||
double timerAlarmReadSeconds(hw_timer_t *timer);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* MAIN_ESP32_HAL_TIMER_H_ */
|
||||
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,368 @@
|
|||
/*
|
||||
TwoWire.cpp - TWI/I2C library for Arduino & Wiring
|
||||
Copyright (c) 2006 Nicholas Zambetti. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts
|
||||
Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support
|
||||
Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support
|
||||
Modified Nov 2017 by Chuck Todd (ctodd@cableone.net) - ESP32 ISR Support
|
||||
*/
|
||||
|
||||
extern "C" {
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <inttypes.h>
|
||||
}
|
||||
|
||||
#include "esp32-hal-i2c.h"
|
||||
#include "Wire.h"
|
||||
//#include "Arduino.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
TwoWire::TwoWire(uint8_t bus_num)
|
||||
:num(bus_num & 1)
|
||||
,sda(-1)
|
||||
,scl(-1)
|
||||
,i2c(NULL)
|
||||
,rxIndex(0)
|
||||
,rxLength(0)
|
||||
,rxQueued(0)
|
||||
,txIndex(0)
|
||||
,txLength(0)
|
||||
,txAddress(0)
|
||||
,txQueued(0)
|
||||
,transmitting(0)
|
||||
,last_error(I2C_ERROR_OK)
|
||||
,_timeOutMillis(50)
|
||||
{}
|
||||
|
||||
TwoWire::~TwoWire()
|
||||
{
|
||||
flush();
|
||||
if(i2c) {
|
||||
i2cRelease(i2c);
|
||||
i2c=NULL;
|
||||
}
|
||||
}
|
||||
|
||||
bool TwoWire::begin(int sdaPin, int sclPin, uint32_t frequency)
|
||||
{
|
||||
if(sdaPin < 0) { // default param passed
|
||||
if(num == 0) {
|
||||
if(sda==-1) {
|
||||
sdaPin = SDA; //use Default Pin
|
||||
} else {
|
||||
sdaPin = sda; // reuse prior pin
|
||||
}
|
||||
} else {
|
||||
if(sda==-1) {
|
||||
//log_e("no Default SDA Pin for Second Peripheral");
|
||||
return false; //no Default pin for Second Peripheral
|
||||
} else {
|
||||
sdaPin = sda; // reuse prior pin
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(sclPin < 0) { // default param passed
|
||||
if(num == 0) {
|
||||
if(scl == -1) {
|
||||
sclPin = SCL; // use Default pin
|
||||
} else {
|
||||
sclPin = scl; // reuse prior pin
|
||||
}
|
||||
} else {
|
||||
if(scl == -1) {
|
||||
//log_e("no Default SCL Pin for Second Peripheral");
|
||||
return false; //no Default pin for Second Peripheral
|
||||
} else {
|
||||
sclPin = scl; // reuse prior pin
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
sda = sdaPin;
|
||||
scl = sclPin;
|
||||
i2c = i2cInit(num, sdaPin, sclPin, frequency);
|
||||
if(!i2c) {
|
||||
printf("I2C init failed");
|
||||
return false;
|
||||
}
|
||||
|
||||
flush();
|
||||
return true;
|
||||
|
||||
}
|
||||
|
||||
void TwoWire::setTimeOut(uint16_t timeOutMillis)
|
||||
{
|
||||
_timeOutMillis = timeOutMillis;
|
||||
}
|
||||
|
||||
uint16_t TwoWire::getTimeOut()
|
||||
{
|
||||
return _timeOutMillis;
|
||||
}
|
||||
|
||||
void TwoWire::setClock(uint32_t frequency)
|
||||
{
|
||||
i2cSetFrequency(i2c, frequency);
|
||||
}
|
||||
|
||||
size_t TwoWire::getClock()
|
||||
{
|
||||
return i2cGetFrequency(i2c);
|
||||
}
|
||||
|
||||
/* stickBreaker Nov 2017 ISR, and bigblock 64k-1
|
||||
*/
|
||||
i2c_err_t TwoWire::writeTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop)
|
||||
{
|
||||
last_error = i2cWrite(i2c, address, buff, size, sendStop, _timeOutMillis);
|
||||
return last_error;
|
||||
}
|
||||
|
||||
i2c_err_t TwoWire::readTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop, uint32_t *readCount)
|
||||
{
|
||||
last_error = i2cRead(i2c, address, buff, size, sendStop, _timeOutMillis, readCount);
|
||||
return last_error;
|
||||
}
|
||||
|
||||
void TwoWire::beginTransmission(uint16_t address)
|
||||
{
|
||||
transmitting = 1;
|
||||
txAddress = address;
|
||||
txIndex = txQueued; // allow multiple beginTransmission(),write(),endTransmission(false) until endTransmission(true)
|
||||
txLength = txQueued;
|
||||
last_error = I2C_ERROR_OK;
|
||||
}
|
||||
|
||||
/*stickbreaker isr
|
||||
*/
|
||||
uint8_t TwoWire::endTransmission(bool sendStop) // Assumes Wire.beginTransaction(), Wire.write()
|
||||
{
|
||||
if(transmitting == 1) {
|
||||
last_error = writeTransmission(txAddress, &txBuffer[txQueued], txLength - txQueued, sendStop);
|
||||
rxIndex = 0;
|
||||
rxLength = rxQueued;
|
||||
rxQueued = 0;
|
||||
txQueued = 0; // the SendStop=true will restart all Queueing
|
||||
if(last_error == I2C_ERROR_CONTINUE){
|
||||
// txlength is howmany bytes in txbuffer have been use
|
||||
txQueued = txLength;
|
||||
}
|
||||
} else {
|
||||
last_error = I2C_ERROR_NO_BEGIN;
|
||||
flush();
|
||||
}
|
||||
txIndex = 0;
|
||||
txLength = 0;
|
||||
transmitting = 0;
|
||||
return last_error;
|
||||
}
|
||||
|
||||
/* @stickBreaker 11/2017 fix for ReSTART timeout, ISR
|
||||
*/
|
||||
uint8_t TwoWire::requestFrom(uint16_t address, uint8_t size, bool sendStop)
|
||||
{
|
||||
//use internal Wire rxBuffer, multiple requestFrom()'s may be pending, try to share rxBuffer
|
||||
uint32_t cnt = rxQueued; // currently queued reads, next available position in rxBuffer
|
||||
if(cnt < (I2C_BUFFER_LENGTH-1) && (size + cnt) <= I2C_BUFFER_LENGTH) { // any room left in rxBuffer
|
||||
rxQueued += size;
|
||||
} else { // no room to receive more!
|
||||
//log_e("rxBuff overflow %d", cnt + size);
|
||||
cnt = 0;
|
||||
last_error = I2C_ERROR_MEMORY;
|
||||
flush();
|
||||
return cnt;
|
||||
}
|
||||
|
||||
last_error = readTransmission(address, &rxBuffer[cnt], size, sendStop, &cnt);
|
||||
rxIndex = 0;
|
||||
rxLength = rxQueued;
|
||||
rxQueued = 0;
|
||||
txQueued = 0; // the SendStop=true will restart all Queueing
|
||||
if(last_error != I2C_ERROR_OK){
|
||||
cnt = 0;
|
||||
}
|
||||
return cnt;
|
||||
}
|
||||
|
||||
size_t TwoWire::write(uint8_t data)
|
||||
{
|
||||
if(transmitting) {
|
||||
if(txLength >= I2C_BUFFER_LENGTH) {
|
||||
last_error = I2C_ERROR_MEMORY;
|
||||
return 0;
|
||||
}
|
||||
txBuffer[txIndex] = data;
|
||||
++txIndex;
|
||||
txLength = txIndex;
|
||||
return 1;
|
||||
}
|
||||
last_error = I2C_ERROR_NO_BEGIN; // no begin, not transmitting
|
||||
return 0;
|
||||
}
|
||||
|
||||
size_t TwoWire::write(const uint8_t *data, size_t quantity)
|
||||
{
|
||||
for(size_t i = 0; i < quantity; ++i) {
|
||||
if(!write(data[i])) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return quantity;
|
||||
|
||||
}
|
||||
|
||||
int TwoWire::available(void)
|
||||
{
|
||||
int result = rxLength - rxIndex;
|
||||
return result;
|
||||
}
|
||||
|
||||
int TwoWire::read(void)
|
||||
{
|
||||
int value = -1;
|
||||
if(rxIndex < rxLength) {
|
||||
value = rxBuffer[rxIndex];
|
||||
++rxIndex;
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
int TwoWire::peek(void)
|
||||
{
|
||||
int value = -1;
|
||||
if(rxIndex < rxLength) {
|
||||
value = rxBuffer[rxIndex];
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
void TwoWire::flush(void)
|
||||
{
|
||||
rxIndex = 0;
|
||||
rxLength = 0;
|
||||
txIndex = 0;
|
||||
txLength = 0;
|
||||
rxQueued = 0;
|
||||
txQueued = 0;
|
||||
i2cFlush(i2c); // cleanup
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop)
|
||||
{
|
||||
return requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), static_cast<bool>(sendStop));
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity, uint8_t sendStop)
|
||||
{
|
||||
return requestFrom(address, static_cast<size_t>(quantity), static_cast<bool>(sendStop));
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity)
|
||||
{
|
||||
return requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), true);
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity)
|
||||
{
|
||||
return requestFrom(address, static_cast<size_t>(quantity), true);
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(int address, int quantity)
|
||||
{
|
||||
return requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), true);
|
||||
}
|
||||
|
||||
uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop)
|
||||
{
|
||||
return static_cast<uint8_t>(requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), static_cast<bool>(sendStop)));
|
||||
}
|
||||
|
||||
void TwoWire::beginTransmission(int address)
|
||||
{
|
||||
beginTransmission(static_cast<uint16_t>(address));
|
||||
}
|
||||
|
||||
void TwoWire::beginTransmission(uint8_t address)
|
||||
{
|
||||
beginTransmission(static_cast<uint16_t>(address));
|
||||
}
|
||||
|
||||
uint8_t TwoWire::endTransmission(void)
|
||||
{
|
||||
return endTransmission(true);
|
||||
}
|
||||
|
||||
/* stickbreaker Nov2017 better error reporting
|
||||
*/
|
||||
uint8_t TwoWire::lastError()
|
||||
{
|
||||
return (uint8_t)last_error;
|
||||
}
|
||||
|
||||
const char ERRORTEXT[] =
|
||||
"OK\0"
|
||||
"DEVICE\0"
|
||||
"ACK\0"
|
||||
"TIMEOUT\0"
|
||||
"BUS\0"
|
||||
"BUSY\0"
|
||||
"MEMORY\0"
|
||||
"CONTINUE\0"
|
||||
"NO_BEGIN\0"
|
||||
"\0";
|
||||
|
||||
|
||||
char * TwoWire::getErrorText(uint8_t err)
|
||||
{
|
||||
uint8_t t = 0;
|
||||
bool found = false;
|
||||
char * message = (char*)&ERRORTEXT;
|
||||
|
||||
while(!found && message[0]) {
|
||||
found = t == err;
|
||||
if(!found) {
|
||||
message = message + strlen(message) + 1;
|
||||
t++;
|
||||
}
|
||||
}
|
||||
if(!found) {
|
||||
return NULL;
|
||||
} else {
|
||||
return message;
|
||||
}
|
||||
}
|
||||
|
||||
/*stickbreaker Dump i2c Interrupt buffer, i2c isr Debugging
|
||||
*/
|
||||
|
||||
uint32_t TwoWire::setDebugFlags( uint32_t setBits, uint32_t resetBits){
|
||||
return i2cDebug(i2c,setBits,resetBits);
|
||||
}
|
||||
|
||||
bool TwoWire::busy(void){
|
||||
return ((i2cGetStatus(i2c) & 16 )==16);
|
||||
}
|
||||
|
||||
TwoWire Wire = TwoWire(0);
|
||||
TwoWire Wire1 = TwoWire(1);
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
TwoWire.h - TWI/I2C library for Arduino & Wiring
|
||||
Copyright (c) 2006 Nicholas Zambetti. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts
|
||||
Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support
|
||||
Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support
|
||||
Modified November 2017 by Chuck Todd <stickbreaker on GitHub> to use ISR and increase stability.
|
||||
*/
|
||||
|
||||
#ifndef TwoWire_h
|
||||
#define TwoWire_h
|
||||
|
||||
#include "esp32-hal-i2c.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/queue.h"
|
||||
|
||||
|
||||
|
||||
#define SDA (gpio_num_t)4
|
||||
#define SCL (gpio_num_t)5
|
||||
|
||||
|
||||
#define STICKBREAKER V1.0.1
|
||||
#define I2C_BUFFER_LENGTH 128
|
||||
typedef void(*user_onRequest)(void);
|
||||
typedef void(*user_onReceive)(uint8_t*, int);
|
||||
|
||||
class TwoWire
|
||||
{
|
||||
protected:
|
||||
uint8_t num;
|
||||
int8_t sda;
|
||||
int8_t scl;
|
||||
i2c_t * i2c;
|
||||
|
||||
uint8_t rxBuffer[I2C_BUFFER_LENGTH];
|
||||
uint16_t rxIndex;
|
||||
uint16_t rxLength;
|
||||
uint16_t rxQueued; //@stickBreaker
|
||||
|
||||
uint8_t txBuffer[I2C_BUFFER_LENGTH];
|
||||
uint16_t txIndex;
|
||||
uint16_t txLength;
|
||||
uint16_t txAddress;
|
||||
uint16_t txQueued; //@stickbreaker
|
||||
|
||||
uint8_t transmitting;
|
||||
/* slave Mode, not yet Stickbreaker
|
||||
static user_onRequest uReq[2];
|
||||
static user_onReceive uRcv[2];
|
||||
void onRequestService(void);
|
||||
void onReceiveService(uint8_t*, int);
|
||||
*/
|
||||
i2c_err_t last_error; // @stickBreaker from esp32-hal-i2c.h
|
||||
uint16_t _timeOutMillis;
|
||||
|
||||
public:
|
||||
TwoWire(uint8_t bus_num);
|
||||
~TwoWire();
|
||||
bool begin(int sda=-1, int scl=-1, uint32_t frequency=0);
|
||||
|
||||
void setClock(uint32_t frequency); // change bus clock without initing hardware
|
||||
size_t getClock(); // current bus clock rate in hz
|
||||
|
||||
void setTimeOut(uint16_t timeOutMillis);
|
||||
uint16_t getTimeOut();
|
||||
|
||||
uint8_t lastError();
|
||||
char * getErrorText(uint8_t err);
|
||||
|
||||
//@stickBreaker for big blocks and ISR model
|
||||
i2c_err_t writeTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true);
|
||||
i2c_err_t readTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true, uint32_t *readCount=NULL);
|
||||
|
||||
void beginTransmission(uint16_t address);
|
||||
void beginTransmission(uint8_t address);
|
||||
void beginTransmission(int address);
|
||||
|
||||
uint8_t endTransmission(bool sendStop);
|
||||
uint8_t endTransmission(void);
|
||||
|
||||
uint8_t requestFrom(uint16_t address, uint8_t size, bool sendStop);
|
||||
uint8_t requestFrom(uint16_t address, uint8_t size, uint8_t sendStop);
|
||||
uint8_t requestFrom(uint16_t address, uint8_t size);
|
||||
uint8_t requestFrom(uint8_t address, uint8_t size, uint8_t sendStop);
|
||||
uint8_t requestFrom(uint8_t address, uint8_t size);
|
||||
uint8_t requestFrom(int address, int size, int sendStop);
|
||||
uint8_t requestFrom(int address, int size);
|
||||
|
||||
size_t write(uint8_t);
|
||||
size_t write(const uint8_t *, size_t);
|
||||
int available(void);
|
||||
int read(void);
|
||||
int peek(void);
|
||||
void flush(void);
|
||||
|
||||
|
||||
|
||||
void onReceive( void (*)(int) );
|
||||
void onRequest( void (*)(void) );
|
||||
|
||||
uint32_t setDebugFlags( uint32_t setBits, uint32_t resetBits);
|
||||
bool busy();
|
||||
};
|
||||
|
||||
extern TwoWire Wire;
|
||||
extern TwoWire Wire1;
|
||||
|
||||
|
||||
/*
|
||||
V1.0.1 02AUG2018 First Fix after release, Correct ReSTART handling, change Debug control, change begin()
|
||||
to a function, this allow reporting if bus cannot be initialized, Wire.begin() can be used to recover
|
||||
a hung bus busy condition.
|
||||
V0.2.2 13APR2018 preserve custom SCL,SDA,Frequency when no parameters passed to begin()
|
||||
V0.2.1 15MAR2018 Hardware reset, Glitch prevention, adding destructor for second i2c testing
|
||||
*/
|
||||
#endif
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#
|
||||
# Main component makefile.
|
||||
#
|
||||
# This Makefile can be left empty. By default, it will take the sources in the
|
||||
# src/ directory, compile them and link them into lib(subdirectory_name).a
|
||||
# in the build directory. This behaviour is entirely configurable,
|
||||
# please read the ESP-IDF documents if you need to do this.
|
||||
#
|
||||
|
||||
COMPONENT_ADD_INCLUDEDIRS := .
|
||||
COMPONENT_SRCDIRS := .
|
||||
|
|
@ -0,0 +1,309 @@
|
|||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
|
||||
#include "stdint.h"
|
||||
#include "esp32-hal-gpio.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "rom/ets_sys.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_intr.h"
|
||||
#include "rom/gpio.h"
|
||||
#include "soc/gpio_reg.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/gpio_struct.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "esp_system.h"
|
||||
|
||||
#define ESP_REG(addr) *((volatile uint32_t *)(addr))
|
||||
|
||||
const int8_t esp32_adc2gpio[20] = {36, 37, 38, 39, 32, 33, 34, 35, -1, -1, 4, 0, 2, 15, 13, 12, 14, 27, 25, 26};
|
||||
|
||||
const DRAM_ATTR esp32_gpioMux_t esp32_gpioMux[GPIO_PIN_COUNT]={
|
||||
{0x44, 11, 11, 1},
|
||||
{0x88, -1, -1, -1},
|
||||
{0x40, 12, 12, 2},
|
||||
{0x84, -1, -1, -1},
|
||||
{0x48, 10, 10, 0},
|
||||
{0x6c, -1, -1, -1},
|
||||
{0x60, -1, -1, -1},
|
||||
{0x64, -1, -1, -1},
|
||||
{0x68, -1, -1, -1},
|
||||
{0x54, -1, -1, -1},
|
||||
{0x58, -1, -1, -1},
|
||||
{0x5c, -1, -1, -1},
|
||||
{0x34, 15, 15, 5},
|
||||
{0x38, 14, 14, 4},
|
||||
{0x30, 16, 16, 6},
|
||||
{0x3c, 13, 13, 3},
|
||||
{0x4c, -1, -1, -1},
|
||||
{0x50, -1, -1, -1},
|
||||
{0x70, -1, -1, -1},
|
||||
{0x74, -1, -1, -1},
|
||||
{0x78, -1, -1, -1},
|
||||
{0x7c, -1, -1, -1},
|
||||
{0x80, -1, -1, -1},
|
||||
{0x8c, -1, -1, -1},
|
||||
{0, -1, -1, -1},
|
||||
{0x24, 6, 18, -1}, //DAC1
|
||||
{0x28, 7, 19, -1}, //DAC2
|
||||
{0x2c, 17, 17, 7},
|
||||
{0, -1, -1, -1},
|
||||
{0, -1, -1, -1},
|
||||
{0, -1, -1, -1},
|
||||
{0, -1, -1, -1},
|
||||
{0x1c, 9, 4, 9},
|
||||
{0x20, 8, 5, 8},
|
||||
{0x14, 4, 6, -1},
|
||||
{0x18, 5, 7, -1},
|
||||
{0x04, 0, 0, -1},
|
||||
{0x08, 1, 1, -1},
|
||||
{0x0c, 2, 2, -1},
|
||||
{0x10, 3, 3, -1}
|
||||
};
|
||||
|
||||
typedef void (*voidFuncPtr)(void);
|
||||
typedef void (*voidFuncPtrArg)(void*);
|
||||
typedef struct {
|
||||
voidFuncPtr fn;
|
||||
void* arg;
|
||||
bool functional;
|
||||
} InterruptHandle_t;
|
||||
static InterruptHandle_t __pinInterruptHandlers[GPIO_PIN_COUNT] = {0,};
|
||||
|
||||
#include "driver/rtc_io.h"
|
||||
|
||||
extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode)
|
||||
{
|
||||
|
||||
if(!digitalPinIsValid(pin)) {
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t rtc_reg = rtc_gpio_desc[pin].reg;
|
||||
if(mode == ANALOG) {
|
||||
if(!rtc_reg) {
|
||||
return;//not rtc pin
|
||||
}
|
||||
//lock rtc
|
||||
uint32_t reg_val = ESP_REG(rtc_reg);
|
||||
if(reg_val & rtc_gpio_desc[pin].mux){
|
||||
return;//already in adc mode
|
||||
}
|
||||
reg_val &= ~(
|
||||
(RTC_IO_TOUCH_PAD1_FUN_SEL_V << rtc_gpio_desc[pin].func)
|
||||
|rtc_gpio_desc[pin].ie
|
||||
|rtc_gpio_desc[pin].pullup
|
||||
|rtc_gpio_desc[pin].pulldown);
|
||||
ESP_REG(RTC_GPIO_ENABLE_W1TC_REG) = (1 << (rtc_gpio_desc[pin].rtc_num + RTC_GPIO_ENABLE_W1TC_S));
|
||||
ESP_REG(rtc_reg) = reg_val | rtc_gpio_desc[pin].mux;
|
||||
//unlock rtc
|
||||
ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = ((uint32_t)2 << MCU_SEL_S) | ((uint32_t)2 << FUN_DRV_S) | FUN_IE;
|
||||
return;
|
||||
}
|
||||
|
||||
//RTC pins PULL settings
|
||||
if(rtc_reg) {
|
||||
//lock rtc
|
||||
ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].mux);
|
||||
if(mode & PULLUP) {
|
||||
ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pullup) & ~(rtc_gpio_desc[pin].pulldown);
|
||||
} else if(mode & PULLDOWN) {
|
||||
ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pulldown) & ~(rtc_gpio_desc[pin].pullup);
|
||||
} else {
|
||||
ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].pullup | rtc_gpio_desc[pin].pulldown);
|
||||
}
|
||||
//unlock rtc
|
||||
}
|
||||
|
||||
uint32_t pinFunction = 0, pinControl = 0;
|
||||
|
||||
//lock gpio
|
||||
if(mode & INPUT) {
|
||||
if(pin < 32) {
|
||||
GPIO.enable_w1tc = ((uint32_t)1 << pin);
|
||||
} else {
|
||||
GPIO.enable1_w1tc.val = ((uint32_t)1 << (pin - 32));
|
||||
}
|
||||
} else if(mode & OUTPUT) {
|
||||
if(pin > 33){
|
||||
//unlock gpio
|
||||
return;//pins above 33 can be only inputs
|
||||
} else if(pin < 32) {
|
||||
GPIO.enable_w1ts = ((uint32_t)1 << pin);
|
||||
} else {
|
||||
GPIO.enable1_w1ts.val = ((uint32_t)1 << (pin - 32));
|
||||
}
|
||||
}
|
||||
|
||||
if(mode & PULLUP) {
|
||||
pinFunction |= FUN_PU;
|
||||
} else if(mode & PULLDOWN) {
|
||||
pinFunction |= FUN_PD;
|
||||
}
|
||||
|
||||
pinFunction |= ((uint32_t)2 << FUN_DRV_S);//what are the drivers?
|
||||
pinFunction |= FUN_IE;//input enable but required for output as well?
|
||||
|
||||
if(mode & (INPUT | OUTPUT)) {
|
||||
pinFunction |= ((uint32_t)2 << MCU_SEL_S);
|
||||
} else if(mode == SPECIAL) {
|
||||
pinFunction |= ((uint32_t)(((pin)==1||(pin)==3)?0:1) << MCU_SEL_S);
|
||||
} else {
|
||||
pinFunction |= ((uint32_t)(mode >> 5) << MCU_SEL_S);
|
||||
}
|
||||
|
||||
ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = pinFunction;
|
||||
|
||||
if(mode & OPEN_DRAIN) {
|
||||
pinControl = (1 << GPIO_PIN0_PAD_DRIVER_S);
|
||||
}
|
||||
|
||||
GPIO.pin[pin].val = pinControl;
|
||||
//unlock gpio
|
||||
}
|
||||
|
||||
extern void IRAM_ATTR __digitalWrite(uint8_t pin, uint8_t val)
|
||||
{
|
||||
if(val) {
|
||||
if(pin < 32) {
|
||||
GPIO.out_w1ts = ((uint32_t)1 << pin);
|
||||
} else if(pin < 34) {
|
||||
GPIO.out1_w1ts.val = ((uint32_t)1 << (pin - 32));
|
||||
}
|
||||
} else {
|
||||
if(pin < 32) {
|
||||
GPIO.out_w1tc = ((uint32_t)1 << pin);
|
||||
} else if(pin < 34) {
|
||||
GPIO.out1_w1tc.val = ((uint32_t)1 << (pin - 32));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
extern int IRAM_ATTR __digitalRead(uint8_t pin)
|
||||
{
|
||||
if(pin < 32) {
|
||||
return (GPIO.in >> pin) & 0x1;
|
||||
} else if(pin < 40) {
|
||||
return (GPIO.in1.val >> (pin - 32)) & 0x1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static intr_handle_t gpio_intr_handle = NULL;
|
||||
|
||||
static void IRAM_ATTR __onPinInterrupt()
|
||||
{
|
||||
uint32_t gpio_intr_status_l=0;
|
||||
uint32_t gpio_intr_status_h=0;
|
||||
|
||||
gpio_intr_status_l = GPIO.status;
|
||||
gpio_intr_status_h = GPIO.status1.val;
|
||||
GPIO.status_w1tc = gpio_intr_status_l;//Clear intr for gpio0-gpio31
|
||||
GPIO.status1_w1tc.val = gpio_intr_status_h;//Clear intr for gpio32-39
|
||||
|
||||
uint8_t pin=0;
|
||||
if(gpio_intr_status_l) {
|
||||
do {
|
||||
if(gpio_intr_status_l & ((uint32_t)1 << pin)) {
|
||||
if(__pinInterruptHandlers[pin].fn) {
|
||||
if(__pinInterruptHandlers[pin].arg){
|
||||
((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg);
|
||||
} else {
|
||||
__pinInterruptHandlers[pin].fn();
|
||||
}
|
||||
}
|
||||
}
|
||||
} while(++pin<32);
|
||||
}
|
||||
if(gpio_intr_status_h) {
|
||||
pin=32;
|
||||
do {
|
||||
if(gpio_intr_status_h & ((uint32_t)1 << (pin - 32))) {
|
||||
if(__pinInterruptHandlers[pin].fn) {
|
||||
if(__pinInterruptHandlers[pin].arg){
|
||||
((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg);
|
||||
} else {
|
||||
__pinInterruptHandlers[pin].fn();
|
||||
}
|
||||
}
|
||||
}
|
||||
} while(++pin<GPIO_PIN_COUNT);
|
||||
}
|
||||
}
|
||||
|
||||
extern void cleanupFunctional(void* arg);
|
||||
|
||||
extern void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtrArg userFunc, void * arg, int intr_type, bool functional)
|
||||
{
|
||||
static bool interrupt_initialized = false;
|
||||
|
||||
if(!interrupt_initialized) {
|
||||
interrupt_initialized = true;
|
||||
esp_intr_alloc(ETS_GPIO_INTR_SOURCE, (int)ESP_INTR_FLAG_IRAM, __onPinInterrupt, NULL, &gpio_intr_handle);
|
||||
}
|
||||
|
||||
// if new attach without detach remove old info
|
||||
if (__pinInterruptHandlers[pin].functional && __pinInterruptHandlers[pin].arg)
|
||||
{
|
||||
cleanupFunctional(__pinInterruptHandlers[pin].arg);
|
||||
}
|
||||
__pinInterruptHandlers[pin].fn = (voidFuncPtr)userFunc;
|
||||
__pinInterruptHandlers[pin].arg = arg;
|
||||
__pinInterruptHandlers[pin].functional = functional;
|
||||
|
||||
esp_intr_disable(gpio_intr_handle);
|
||||
if(esp_intr_get_cpu(gpio_intr_handle)) { //APP_CPU
|
||||
GPIO.pin[pin].int_ena = 1;
|
||||
} else { //PRO_CPU
|
||||
GPIO.pin[pin].int_ena = 4;
|
||||
}
|
||||
GPIO.pin[pin].int_type = intr_type;
|
||||
esp_intr_enable(gpio_intr_handle);
|
||||
}
|
||||
|
||||
extern void __attachInterruptArg(uint8_t pin, voidFuncPtrArg userFunc, void * arg, int intr_type)
|
||||
{
|
||||
__attachInterruptFunctionalArg(pin, userFunc, arg, intr_type, false);
|
||||
}
|
||||
|
||||
extern void __attachInterrupt(uint8_t pin, voidFuncPtr userFunc, int intr_type) {
|
||||
__attachInterruptFunctionalArg(pin, (voidFuncPtrArg)userFunc, NULL, intr_type, false);
|
||||
}
|
||||
|
||||
extern void __detachInterrupt(uint8_t pin)
|
||||
{
|
||||
esp_intr_disable(gpio_intr_handle);
|
||||
if (__pinInterruptHandlers[pin].functional && __pinInterruptHandlers[pin].arg)
|
||||
{
|
||||
cleanupFunctional(__pinInterruptHandlers[pin].arg);
|
||||
}
|
||||
__pinInterruptHandlers[pin].fn = NULL;
|
||||
__pinInterruptHandlers[pin].arg = NULL;
|
||||
__pinInterruptHandlers[pin].arg = false;
|
||||
|
||||
GPIO.pin[pin].int_ena = 0;
|
||||
GPIO.pin[pin].int_type = 0;
|
||||
esp_intr_enable(gpio_intr_handle);
|
||||
}
|
||||
|
||||
|
||||
extern void pinMode(uint8_t pin, uint8_t mode) __attribute__ ((weak, alias("__pinMode")));
|
||||
extern void digitalWrite(uint8_t pin, uint8_t val) __attribute__ ((weak, alias("__digitalWrite")));
|
||||
extern int digitalRead(uint8_t pin) __attribute__ ((weak, alias("__digitalRead")));
|
||||
extern void attachInterrupt(uint8_t pin, voidFuncPtr handler, int mode) __attribute__ ((weak, alias("__attachInterrupt")));
|
||||
extern void attachInterruptArg(uint8_t pin, voidFuncPtrArg handler, void * arg, int mode) __attribute__ ((weak, alias("__attachInterruptArg")));
|
||||
extern void detachInterrupt(uint8_t pin) __attribute__ ((weak, alias("__detachInterrupt")));
|
||||
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
Arduino.h - Main include file for the Arduino SDK
|
||||
Copyright (c) 2005-2013 Arduino Team. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef MAIN_ESP32_HAL_GPIO_H_
|
||||
#define MAIN_ESP32_HAL_GPIO_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define LOW 0x0
|
||||
#define HIGH 0x1
|
||||
|
||||
//GPIO FUNCTIONS
|
||||
#define INPUT 0x01
|
||||
#define OUTPUT 0x02
|
||||
#define PULLUP 0x04
|
||||
#define INPUT_PULLUP 0x05
|
||||
#define PULLDOWN 0x08
|
||||
#define INPUT_PULLDOWN 0x09
|
||||
#define OPEN_DRAIN 0x10
|
||||
#define OUTPUT_OPEN_DRAIN 0x12
|
||||
#define SPECIAL 0xF0
|
||||
#define FUNCTION_1 0x00
|
||||
#define FUNCTION_2 0x20
|
||||
#define FUNCTION_3 0x40
|
||||
#define FUNCTION_4 0x60
|
||||
#define FUNCTION_5 0x80
|
||||
#define FUNCTION_6 0xA0
|
||||
#define ANALOG 0xC0
|
||||
|
||||
//Interrupt Modes
|
||||
#define DISABLED 0x00
|
||||
#define RISING 0x01
|
||||
#define FALLING 0x02
|
||||
#define CHANGE 0x03
|
||||
#define ONLOW 0x04
|
||||
#define ONHIGH 0x05
|
||||
#define ONLOW_WE 0x0C
|
||||
#define ONHIGH_WE 0x0D
|
||||
|
||||
typedef struct {
|
||||
uint8_t reg; /*!< GPIO register offset from DR_REG_IO_MUX_BASE */
|
||||
int8_t rtc; /*!< RTC GPIO number (-1 if not RTC GPIO pin) */
|
||||
int8_t adc; /*!< ADC Channel number (-1 if not ADC pin) */
|
||||
int8_t touch; /*!< Touch Channel number (-1 if not Touch pin) */
|
||||
} esp32_gpioMux_t;
|
||||
|
||||
extern const esp32_gpioMux_t esp32_gpioMux[40];
|
||||
extern const int8_t esp32_adc2gpio[20];
|
||||
|
||||
#define digitalPinIsValid(pin) ((pin) < 40 && esp32_gpioMux[(pin)].reg)
|
||||
#define digitalPinCanOutput(pin) ((pin) < 34 && esp32_gpioMux[(pin)].reg)
|
||||
#define digitalPinToRtcPin(pin) (((pin) < 40)?esp32_gpioMux[(pin)].rtc:-1)
|
||||
#define digitalPinToAnalogChannel(pin) (((pin) < 40)?esp32_gpioMux[(pin)].adc:-1)
|
||||
#define digitalPinToTouchChannel(pin) (((pin) < 40)?esp32_gpioMux[(pin)].touch:-1)
|
||||
#define digitalPinToDacChannel(pin) (((pin) == 25)?0:((pin) == 26)?1:-1)
|
||||
|
||||
void pinMode(uint8_t pin, uint8_t mode);
|
||||
void digitalWrite(uint8_t pin, uint8_t val);
|
||||
int digitalRead(uint8_t pin);
|
||||
|
||||
void attachInterrupt(uint8_t pin, void (*)(void), int mode);
|
||||
void attachInterruptArg(uint8_t pin, void (*)(void*), void * arg, int mode);
|
||||
void detachInterrupt(uint8_t pin);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* MAIN_ESP32_HAL_GPIO_H_ */
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,82 @@
|
|||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
// modified Nov 2017 by Chuck Todd <StickBreaker> to support Interrupt Driven I/O
|
||||
|
||||
#ifndef _ESP32_HAL_I2C_H_
|
||||
#define _ESP32_HAL_I2C_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/event_groups.h"
|
||||
|
||||
// External Wire.h equivalent error Codes
|
||||
typedef enum {
|
||||
I2C_ERROR_OK=0,
|
||||
I2C_ERROR_DEV,
|
||||
I2C_ERROR_ACK,
|
||||
I2C_ERROR_TIMEOUT,
|
||||
I2C_ERROR_BUS,
|
||||
I2C_ERROR_BUSY,
|
||||
I2C_ERROR_MEMORY,
|
||||
I2C_ERROR_CONTINUE,
|
||||
I2C_ERROR_NO_BEGIN
|
||||
} i2c_err_t;
|
||||
|
||||
struct i2c_struct_t;
|
||||
typedef struct i2c_struct_t i2c_t;
|
||||
|
||||
i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t clk_speed);
|
||||
void i2cRelease(i2c_t *i2c); // free ISR, Free DQ, Power off peripheral clock. Must call i2cInit() to recover
|
||||
i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis);
|
||||
i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount);
|
||||
i2c_err_t i2cFlush(i2c_t *i2c);
|
||||
i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed);
|
||||
uint32_t i2cGetFrequency(i2c_t * i2c);
|
||||
uint32_t i2cGetStatus(i2c_t * i2c); // Status register of peripheral
|
||||
|
||||
//Functions below should be used only if well understood
|
||||
//Might be deprecated and removed in future
|
||||
i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl);
|
||||
i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl);
|
||||
i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda);
|
||||
i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda);
|
||||
|
||||
//Stickbreakers ISR Support
|
||||
i2c_err_t i2cProcQueue(i2c_t *i2c, uint32_t *readCount, uint16_t timeOutMillis);
|
||||
i2c_err_t i2cAddQueueWrite(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event);
|
||||
i2c_err_t i2cAddQueueRead(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event);
|
||||
|
||||
//stickbreaker debug support
|
||||
uint32_t i2cDebug(i2c_t *, uint32_t setBits, uint32_t resetBits);
|
||||
// Debug actions have 3 currently defined locus
|
||||
// 0xXX------ : at entry of ProcQueue
|
||||
// 0x--XX---- : at exit of ProcQueue
|
||||
// 0x------XX : at entry of Flush
|
||||
//
|
||||
// bit 0 causes DumpI2c to execute
|
||||
// bit 1 causes DumpInts to execute
|
||||
// bit 2 causes DumpCmdqueue to execute
|
||||
// bit 3 causes DumpStatus to execute
|
||||
// bit 4 causes DumpFifo to execute
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ESP32_HAL_I2C_H_ */
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp32-hal-matrix.h"
|
||||
#include "esp_attr.h"
|
||||
#include "rom/gpio.h"
|
||||
|
||||
|
||||
|
||||
#define MATRIX_DETACH_OUT_SIG 0x100
|
||||
#define MATRIX_DETACH_IN_LOW_PIN 0x30
|
||||
#define MATRIX_DETACH_IN_LOW_HIGH 0x38
|
||||
|
||||
void IRAM_ATTR pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable)
|
||||
{
|
||||
gpio_matrix_out(pin, function, invertOut, invertEnable);
|
||||
}
|
||||
|
||||
void IRAM_ATTR pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable)
|
||||
{
|
||||
gpio_matrix_out(pin, MATRIX_DETACH_OUT_SIG, invertOut, invertEnable);
|
||||
}
|
||||
|
||||
void IRAM_ATTR pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted)
|
||||
{
|
||||
gpio_matrix_in(pin, signal, inverted);
|
||||
}
|
||||
|
||||
void IRAM_ATTR pinMatrixInDetach(uint8_t signal, bool high, bool inverted)
|
||||
{
|
||||
gpio_matrix_in(high?MATRIX_DETACH_IN_LOW_HIGH:MATRIX_DETACH_IN_LOW_PIN, signal, inverted);
|
||||
}
|
||||
/*
|
||||
void IRAM_ATTR intrMatrixAttach(uint32_t source, uint32_t inum){
|
||||
intr_matrix_set(PRO_CPU_NUM, source, inum);
|
||||
}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _ESP32_HAL_MATRIX_H_
|
||||
#define _ESP32_HAL_MATRIX_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//#include "esp32-hal.h"
|
||||
//#include "soc/gpio_sig_map.h"
|
||||
|
||||
void pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable);
|
||||
void pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable);
|
||||
void pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted);
|
||||
void pinMatrixInDetach(uint8_t signal, bool high, bool inverted);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* COMPONENTS_ARDUHAL_INCLUDE_ESP32_HAL_MATRIX_H_ */
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#!/bin/bash
|
||||
. ${IDF_PATH}/add_path.sh
|
||||
esptool.py --chip esp32 --port "/dev/cu.SLAB_USBtoUART" --baud $((230400*4)) write_flash -fs 4MB 0x10000 ../espcastaway/build/espcastaway.bin
|
||||
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,14 @@
|
|||
#
|
||||
# Component Makefile
|
||||
#
|
||||
# This Makefile can be left empty. By default, it will take the sources in the
|
||||
# src/ directory, compile them and link them into lib(subdirectory_name).a
|
||||
# in the build directory. This behaviour is entirely configurable,
|
||||
# please read the ESP-IDF documents if you need to do this.
|
||||
#
|
||||
|
||||
COMPONENT_ADD_INCLUDEDIRS := . ../..
|
||||
COMPONENT_SRCDIRS := .
|
||||
|
||||
CPPFLAGS += -O3 -ffast-math -DUSE_FAME_CORE_C -DUSE_FAME_CORE -DFAME_GLOBAL_CONTEXT
|
||||
CPPFLAGS += -DNO_SOUND #-DEMULATED_JOYSTICK -DUSE_SHORT_SLICE -DUSE_DOUBLE_BUFFER
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,190 @@
|
|||
/******************************************************************************/
|
||||
/* FAME Fast and Accurate Motorola 68000 Emulation Core */
|
||||
/* (c) 2002 Oscar Orallo Pelaez / Daniel Lancha Garcia */
|
||||
/* Version: 2.1 */
|
||||
/* Date: 11-26-2006 */
|
||||
/* See FAME.HTML for documentation and license information */
|
||||
/******************************************************************************/
|
||||
|
||||
#ifndef __FAME_H__
|
||||
#define __FAME_H__
|
||||
|
||||
#if defined(__cplusplus) && !defined(USE_FAME_CORE_C)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************************/
|
||||
/* General library defines */
|
||||
/************************************/
|
||||
|
||||
#ifndef M68K_OK
|
||||
#define M68K_OK 0
|
||||
#endif
|
||||
|
||||
#ifndef M68K_RUNNING
|
||||
#define M68K_RUNNING 1
|
||||
#endif
|
||||
|
||||
#ifndef M68K_NO_SUP_ADDR_SPACE
|
||||
#define M68K_NO_SUP_ADDR_SPACE 2
|
||||
#endif
|
||||
|
||||
#ifndef M68K_INV_REG
|
||||
#define M68K_INV_REG -1
|
||||
#endif
|
||||
|
||||
/* Hardware interrupt state */
|
||||
|
||||
#ifndef M68K_IRQ_LEVEL_ERROR
|
||||
#define M68K_IRQ_LEVEL_ERROR -1
|
||||
#endif
|
||||
|
||||
#ifndef M68K_IRQ_INV_PARAMS
|
||||
#define M68K_IRQ_INV_PARAMS -2
|
||||
#endif
|
||||
|
||||
/* Defines to specify hardware interrupt type */
|
||||
|
||||
#ifndef M68K_AUTOVECTORED_IRQ
|
||||
#define M68K_AUTOVECTORED_IRQ -1
|
||||
#endif
|
||||
|
||||
#ifndef M68K_SPURIOUS_IRQ
|
||||
#define M68K_SPURIOUS_IRQ -2
|
||||
#endif
|
||||
|
||||
/* Defines to specify address space */
|
||||
|
||||
#ifndef M68K_SUP_ADDR_SPACE
|
||||
#define M68K_SUP_ADDR_SPACE 0
|
||||
#endif
|
||||
|
||||
#ifndef M68K_USER_ADDR_SPACE
|
||||
#define M68K_USER_ADDR_SPACE 2
|
||||
#endif
|
||||
|
||||
#ifndef M68K_PROG_ADDR_SPACE
|
||||
#define M68K_PROG_ADDR_SPACE 0
|
||||
#endif
|
||||
|
||||
#ifndef M68K_DATA_ADDR_SPACE
|
||||
#define M68K_DATA_ADDR_SPACE 1
|
||||
#endif
|
||||
|
||||
|
||||
/*******************/
|
||||
/* Data definition */
|
||||
/*******************/
|
||||
|
||||
/* M68K registers */
|
||||
typedef enum
|
||||
{
|
||||
M68K_REG_D0=0,
|
||||
M68K_REG_D1,
|
||||
M68K_REG_D2,
|
||||
M68K_REG_D3,
|
||||
M68K_REG_D4,
|
||||
M68K_REG_D5,
|
||||
M68K_REG_D6,
|
||||
M68K_REG_D7,
|
||||
M68K_REG_A0,
|
||||
M68K_REG_A1,
|
||||
M68K_REG_A2,
|
||||
M68K_REG_A3,
|
||||
M68K_REG_A4,
|
||||
M68K_REG_A5,
|
||||
M68K_REG_A6,
|
||||
M68K_REG_A7,
|
||||
M68K_REG_ASP,
|
||||
M68K_REG_PC,
|
||||
M68K_REG_SR
|
||||
} m68k_register;
|
||||
|
||||
/* The memory blocks must be in native (Motorola) format */
|
||||
typedef struct
|
||||
{
|
||||
unsigned low_addr;
|
||||
unsigned high_addr;
|
||||
unsigned offset;
|
||||
} M68K_PROGRAM;
|
||||
|
||||
/* The memory blocks must be in native (Motorola) format */
|
||||
typedef struct
|
||||
{
|
||||
unsigned low_addr;
|
||||
unsigned high_addr;
|
||||
void *mem_handler;
|
||||
void *data;
|
||||
} M68K_DATA;
|
||||
|
||||
/* M68K CPU CONTEXT */
|
||||
typedef struct
|
||||
{
|
||||
M68K_PROGRAM *fetch;
|
||||
M68K_DATA *read_byte;
|
||||
M68K_DATA *read_word;
|
||||
M68K_DATA *write_byte;
|
||||
M68K_DATA *write_word;
|
||||
M68K_PROGRAM *sv_fetch;
|
||||
M68K_DATA *sv_read_byte;
|
||||
M68K_DATA *sv_read_word;
|
||||
M68K_DATA *sv_write_byte;
|
||||
M68K_DATA *sv_write_word;
|
||||
M68K_PROGRAM *user_fetch;
|
||||
M68K_DATA *user_read_byte;
|
||||
M68K_DATA *user_read_word;
|
||||
M68K_DATA *user_write_byte;
|
||||
M68K_DATA *user_write_word;
|
||||
void (*reset_handler)(void);
|
||||
void (*iack_handler)(unsigned level);
|
||||
unsigned * icust_handler;
|
||||
unsigned dreg[8];
|
||||
unsigned areg[8];
|
||||
unsigned asp;
|
||||
unsigned pc;
|
||||
unsigned cycles_counter;
|
||||
unsigned char interrupts[8];
|
||||
unsigned short sr;
|
||||
unsigned short execinfo;
|
||||
} M68K_CONTEXT;
|
||||
|
||||
|
||||
/************************/
|
||||
/* Function definition */
|
||||
/************************/
|
||||
|
||||
/* General purpose functions */
|
||||
void m68k_init(void);
|
||||
unsigned m68k_reset(void);
|
||||
void m68k_emulate(int n);
|
||||
unsigned m68k_get_pc(void);
|
||||
unsigned m68k_get_cpu_state(void);
|
||||
int m68k_fetch(unsigned address, unsigned memory_space);
|
||||
|
||||
/* Interrupt handling functions */
|
||||
int m68k_raise_irq(int level, int vector);
|
||||
int m68k_lower_irq(int level);
|
||||
int m68k_get_irq_vector(int level);
|
||||
int m68k_change_irq_vector(int level, int vector);
|
||||
|
||||
/* CPU context handling functions */
|
||||
int m68k_get_context_size(void);
|
||||
void m68k_get_context(void *context);
|
||||
void m68k_set_context(void *context);
|
||||
int m68k_get_register(m68k_register reg);
|
||||
int m68k_set_register(m68k_register reg, unsigned value);
|
||||
|
||||
/* Timing functions */
|
||||
unsigned m68k_get_cycles_counter(void);
|
||||
unsigned m68k_trip_cycles_counter(void);
|
||||
unsigned m68k_control_cycles_counter(int n);
|
||||
void m68k_release_timeslice(void);
|
||||
void m68k_stop_emulating(void);
|
||||
void m68k_add_cycles(int cycles);
|
||||
void m68k_release_cycles(int cycles);
|
||||
|
||||
#if defined(__cplusplus) && !defined(USE_FAME_CORE_C)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,322 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "dcastaway.h"
|
||||
#include "mem.h"
|
||||
#include "st.h"
|
||||
#include "config.h"
|
||||
|
||||
#include "m68k_intrf.h"
|
||||
|
||||
#ifdef DEBUG_FAME
|
||||
FILE *fame_debug_file=stdout;
|
||||
unsigned fame_debug_count=0;
|
||||
#ifdef DEBUG_FAME_START
|
||||
int fame_debug_output=0;
|
||||
#else
|
||||
int fame_debug_output=1;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_FAME
|
||||
#include "dis.h"
|
||||
#endif
|
||||
|
||||
void SetMemBB(unsigned long address, unsigned char value);
|
||||
void SetMemWW(unsigned long address, unsigned short value);
|
||||
|
||||
char GetMemB(unsigned long address);
|
||||
short GetMemW(unsigned long address);
|
||||
long GetMemL(unsigned long address);
|
||||
void SetMemB(unsigned long address, unsigned char value);
|
||||
void SetMemW(unsigned long address, unsigned short value);
|
||||
void SetMemL(unsigned long address, unsigned long value);
|
||||
|
||||
|
||||
#if defined(FAME_SINGLE_MEMORY) && defined(DEBUG_FAME)
|
||||
|
||||
static char MyGetMemB(unsigned long address)
|
||||
{
|
||||
char ret;
|
||||
|
||||
if (fame_debug_output)
|
||||
{ fprintf(fame_debug_file,"GetMemB(0x%.6X)",address); DEBUG_FAME_FFLUSH; }
|
||||
|
||||
ret=GetMemB(address);
|
||||
|
||||
if (fame_debug_output)
|
||||
{ fprintf(fame_debug_file," = 0x%.2X\n",ret); DEBUG_FAME_FFLUSH; }
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static short MyGetMemW(unsigned long address)
|
||||
{
|
||||
short ret;
|
||||
|
||||
if (fame_debug_output)
|
||||
{ fprintf(fame_debug_file,"GetMemW(0x%.6X)",address); DEBUG_FAME_FFLUSH; }
|
||||
|
||||
ret=GetMemW(address);
|
||||
|
||||
if (fame_debug_output)
|
||||
{ fprintf(fame_debug_file," = 0x%.4X\n",ret); DEBUG_FAME_FFLUSH; }
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void MySetMemB(unsigned long address, unsigned value)
|
||||
{
|
||||
value&=0xff;
|
||||
if (fame_debug_output)
|
||||
{ fprintf(fame_debug_file,"SetMemB(0x%.6X,0x%.2X)",address,value); DEBUG_FAME_FFLUSH; }
|
||||
|
||||
SetMemB(address,value);
|
||||
|
||||
if (fame_debug_output)
|
||||
{ fputs(fame_debug_file,"."); DEBUG_FAME_FFLUSH; }
|
||||
}
|
||||
|
||||
static void MySetMemW(unsigned long address, unsigned value)
|
||||
{
|
||||
value&=0xffff;
|
||||
if (fame_debug_output)
|
||||
{ fprintf(fame_debug_file,"SetMemW(0x%.6X,0x%.4X)",address,value); DEBUG_FAME_FFLUSH; }
|
||||
|
||||
SetMemW(address,value);
|
||||
|
||||
if (fame_debug_output)
|
||||
{ fputs(".",fame_debug_file); DEBUG_FAME_FFLUSH; }
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define MyGetMemW GetMemW
|
||||
#define MyGetMemB GetMemB
|
||||
#define MySetMemW SetMemW
|
||||
#define MySetMemB SetMemB
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef USE_FAME_CORE
|
||||
int recalc_int=1; //0;
|
||||
#endif
|
||||
int in_fame_core=0;
|
||||
int number_exg0_fame=0;
|
||||
static unsigned addr_exg0_fame=0;
|
||||
static unsigned pc_exg0_fame=0;
|
||||
static unsigned sr_exg0_fame=0;
|
||||
static int rw_exg0_fame=0;
|
||||
static unsigned long exaddress=0x12345678;
|
||||
|
||||
void HWReset(void)
|
||||
{
|
||||
m68k_reset();
|
||||
exaddress=0x12345678;
|
||||
}
|
||||
|
||||
static int inexec=0;
|
||||
|
||||
void ExceptionGroup0_execute(void)
|
||||
{
|
||||
short context = 0;
|
||||
|
||||
#ifdef DEBUG_FAME
|
||||
if (fame_debug_output)
|
||||
{ fputs("ExceptionGroup0_execute",fame_debug_file); DEBUG_FAME_FFLUSH; }
|
||||
#endif
|
||||
|
||||
M68KCONTEXT.execinfo&=0x7F;
|
||||
|
||||
if ((!((exaddress+1!=addr_exg0_fame)&&(exaddress+2!=addr_exg0_fame)&&(exaddress+3!=addr_exg0_fame))) || (!inexec))
|
||||
{
|
||||
if (!inexec)
|
||||
m68k_reset();
|
||||
return;
|
||||
}
|
||||
inexec=0;
|
||||
|
||||
context |= 0x8;
|
||||
if (rw_exg0_fame)
|
||||
context |= 0x10;
|
||||
if (GetS())
|
||||
context |= 0x4;
|
||||
if (rw_exg0_fame && addr_exg0_fame == pc_exg0_fame)
|
||||
context |= 0x2;
|
||||
else
|
||||
context |= 0x1;
|
||||
|
||||
M68KCONTEXT.sr |= (1<<13);
|
||||
M68KCONTEXT.sr &= ~(1<<15);
|
||||
|
||||
M68KCONTEXT.areg[7]-=14;
|
||||
SetMemW(M68KCONTEXT.areg[7], context);
|
||||
SetMemL(M68KCONTEXT.areg[7] + 2, addr_exg0_fame);
|
||||
SetMemW(M68KCONTEXT.areg[7] + 6, GetMemW(pc_exg0_fame));
|
||||
SetMemW(M68KCONTEXT.areg[7] + 8, sr_exg0_fame);
|
||||
SetMemL(M68KCONTEXT.areg[7] + 10, pc_exg0_fame);
|
||||
|
||||
M68KCONTEXT.pc=GetMemL((long)number_exg0_fame * 4);
|
||||
|
||||
exaddress=addr_exg0_fame;
|
||||
number_exg0_fame=0;
|
||||
}
|
||||
|
||||
void ExceptionGroup0(
|
||||
int number, /* trap number */
|
||||
unsigned long address, /* fault address */
|
||||
int rw) /* read = true, write = false */
|
||||
{
|
||||
#ifdef DEBUG_FAME
|
||||
if (fame_debug_output)
|
||||
{ fprintf(fame_debug_file,"ExceptionGroup0(%i,0x%X,%i)\n",number,address,rw); DEBUG_FAME_FFLUSH; }
|
||||
#endif
|
||||
if ((exaddress+1!=address)&&(exaddress+2!=address)&&(exaddress+3!=address)&&(!inexec)){
|
||||
inexec=1;
|
||||
number_exg0_fame=number;
|
||||
addr_exg0_fame=address;
|
||||
rw_exg0_fame=rw;
|
||||
pc_exg0_fame=M68KCONTEXT.pc;
|
||||
sr_exg0_fame=M68KCONTEXT.sr;
|
||||
if (!in_fame_core)
|
||||
ExceptionGroup0_execute();
|
||||
else
|
||||
IO_CYCLE=0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static M68K_CONTEXT context;
|
||||
|
||||
static M68K_PROGRAM program[]= {
|
||||
{0, MEMSIZE-1, (unsigned)membase},
|
||||
{MEMSIZE, (MEMSIZE*2)-1, ((unsigned)membase)-MEMSIZE},
|
||||
{MEMSIZE*2, (MEMSIZE*3)-1, ((unsigned)membase)-(MEMSIZE*2)},
|
||||
#if MEMSIZE*4 <= ROMBASE2
|
||||
{MEMSIZE*3, (MEMSIZE*4)-1, ((unsigned)membase)-(MEMSIZE*3)},
|
||||
#if MEMSIZE*5 <= ROMBASE2
|
||||
{MEMSIZE*4, (MEMSIZE*5)-1, ((unsigned)membase)-(MEMSIZE*4)},
|
||||
#if MEMSIZE*6 <= ROMBASE2
|
||||
{MEMSIZE*5, (MEMSIZE*6)-1, ((unsigned)membase)-(MEMSIZE*5)},
|
||||
#if MEMSIZE*7 <= ROMBASE2
|
||||
{MEMSIZE*6, (MEMSIZE*7)-1, ((unsigned)membase)-(MEMSIZE*6)},
|
||||
#if MEMSIZE*8 <= ROMBASE2
|
||||
{MEMSIZE*7, (MEMSIZE*8)-1, ((unsigned)membase)-(MEMSIZE*7)},
|
||||
#if MEMSIZE*9 <= ROMBASE2
|
||||
{MEMSIZE*8, (MEMSIZE*9)-1, ((unsigned)membase)-(MEMSIZE*8)},
|
||||
#if MEMSIZE*10 <= ROMBASE2
|
||||
{MEMSIZE*9, (MEMSIZE*10)-1, ((unsigned)membase)-(MEMSIZE*9)},
|
||||
#if MEMSIZE*11 <= ROMBASE2
|
||||
{MEMSIZE*10, (MEMSIZE*11)-1, ((unsigned)membase)-(MEMSIZE*10)},
|
||||
#if MEMSIZE*12 <= ROMBASE2
|
||||
{MEMSIZE*11, (MEMSIZE*12)-1, ((unsigned)membase)-(MEMSIZE*11)},
|
||||
#if MEMSIZE*13 <= ROMBASE2
|
||||
{MEMSIZE*12, (MEMSIZE*13)-1, ((unsigned)membase)-(MEMSIZE*12)},
|
||||
#if MEMSIZE*14 <= ROMBASE2
|
||||
{MEMSIZE*13, (MEMSIZE*14)-1, ((unsigned)membase)-(MEMSIZE*13)},
|
||||
#if MEMSIZE*15 <= ROMBASE2
|
||||
{MEMSIZE*14, (MEMSIZE*15)-1, ((unsigned)membase)-(MEMSIZE*14)},
|
||||
#if MEMSIZE*16 <= ROMBASE2
|
||||
{MEMSIZE*15, (MEMSIZE*16)-1, ((unsigned)membase)-(MEMSIZE*15)},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
{ROMBASE2, (IOBASE-1), (unsigned)rombase},
|
||||
{IOBASE, 0x00FFFFFF, (unsigned)rombase},
|
||||
{(unsigned)-1,(unsigned)-1,(unsigned)NULL}
|
||||
};
|
||||
|
||||
#ifndef FAME_SINGLE_MEMORY
|
||||
static M68K_DATA read8[] = {
|
||||
{0, MEMSIZE-1, NULL, (void *)membase},
|
||||
{MEMSIZE, (ROMBASE2)-1, (void *)GetMemB, NULL},
|
||||
{ROMBASE2, IOBASE-1, NULL, (void *)rombase},
|
||||
{IOBASE, 0x00FFFFFF, (void *)DoIORB, NULL},
|
||||
{(unsigned)-1,(unsigned)-1,NULL,NULL}
|
||||
};
|
||||
|
||||
static M68K_DATA read16[] = {
|
||||
{0, MEMSIZE-1, NULL, (void *)membase},
|
||||
{MEMSIZE, (ROMBASE2)-1, (void *)GetMemW, NULL},
|
||||
{ROMBASE2, IOBASE-1, NULL, (void *)rombase},
|
||||
{IOBASE, 0x00FFFFFF, (void *)DoIORW, NULL},
|
||||
{(unsigned)-1,(unsigned)-1,NULL,NULL}
|
||||
};
|
||||
|
||||
static M68K_DATA write8[] = {
|
||||
// {0, MEMSIZE-1, NULL, (void *)membase},
|
||||
{0, MEMSIZE-1, (void *)SetMemBB, NULL},
|
||||
{MEMSIZE, (IOBASE)-1, (void *)SetMemB, NULL},
|
||||
{IOBASE, 0x00FFFFFF, (void *)DoIOWB, NULL},
|
||||
{(unsigned)-1,(unsigned)-1,NULL,NULL}
|
||||
};
|
||||
|
||||
static M68K_DATA write16[] = {
|
||||
// {0, MEMSIZE-1, NULL, (void *)membase},
|
||||
{0, MEMSIZE-1, (void *)SetMemWW, NULL},
|
||||
{MEMSIZE, (IOBASE)-1, (void *)SetMemW, NULL},
|
||||
{IOBASE, 0x00FFFFFF, (void *)DoIOWW, NULL},
|
||||
{(unsigned)-1,(unsigned)-1,NULL,NULL}
|
||||
};
|
||||
|
||||
#else
|
||||
|
||||
static M68K_DATA read8[] = {
|
||||
{ 0, 0xFFFFFF, (void *)MyGetMemB, NULL },
|
||||
{(unsigned)-1,(unsigned)-1,NULL,NULL}
|
||||
};
|
||||
|
||||
static M68K_DATA read16[] = {
|
||||
{ 0, 0xFFFFFF, (void *)MyGetMemW, NULL },
|
||||
{(unsigned)-1,(unsigned)-1,NULL,NULL}
|
||||
};
|
||||
|
||||
static M68K_DATA write8[] = {
|
||||
{ 0, 0xFFFFFF, (void *)MySetMemB, NULL },
|
||||
{(unsigned)-1,(unsigned)-1,NULL,NULL}
|
||||
};
|
||||
|
||||
static M68K_DATA write16[] = {
|
||||
{ 0, 0xFFFFFF, (void *)MySetMemW, NULL },
|
||||
{(unsigned)-1,(unsigned)-1,NULL,NULL}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
void initialize_memmap(void)
|
||||
{
|
||||
int i;
|
||||
memset(&context,0,sizeof(M68K_CONTEXT));
|
||||
context.fetch=context.sv_fetch=context.user_fetch=(M68K_PROGRAM*)&program;
|
||||
context.read_byte=context.sv_read_byte=context.user_read_byte=(M68K_DATA*)&read8;
|
||||
context.read_word=context.sv_read_word=context.user_read_word=(M68K_DATA*)&read16;
|
||||
context.write_byte=context.sv_write_byte=context.user_write_byte=(M68K_DATA*)&write8;
|
||||
context.write_word=context.sv_write_word=context.user_write_word=(M68K_DATA*)&write16;
|
||||
for(i=0;program[i].low_addr != ((unsigned)-1);i++)
|
||||
{
|
||||
if (program[i].low_addr >= ROMBASE2)
|
||||
program[i].offset= (((unsigned)rombase)+ROMBASE2)-program[i].low_addr;
|
||||
else
|
||||
program[i].offset= ((unsigned)membase) - (i*MEMSIZE);
|
||||
}
|
||||
|
||||
#ifndef FAME_SINGLE_MEMORY
|
||||
read8[0].data=read16[0].data=write8[0].data=write16[0].data=(void *)((unsigned)membase);
|
||||
read8[2].data=read16[2].data=(void *)((unsigned)rombase);
|
||||
#endif
|
||||
|
||||
m68k_init();
|
||||
m68k_set_context(&context);
|
||||
m68k_reset();
|
||||
}
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "config.h"
|
||||
#include "dcastaway.h"
|
||||
|
||||
extern int waitstate;
|
||||
|
||||
#ifndef USE_FAME_CORE
|
||||
|
||||
#include "castaway/68000.h"
|
||||
#include "castaway/op68k.h"
|
||||
|
||||
extern unsigned IO_CYCLE;
|
||||
|
||||
static __inline__ unsigned long cpu_loop(unsigned slice) {
|
||||
|
||||
extern unsigned long (*jmp_table[8192])(operin);
|
||||
|
||||
#define initialize_memmap()
|
||||
//printf("%8x =>%8x\n",pc,myinst);
|
||||
|
||||
#define cpuinst \
|
||||
address = pc&MEMADDRMASK; \
|
||||
if (address<MEMSIZE) myinst=biginst=ReadSL(mymembase+address); \
|
||||
else if (address>=ROMBASE2) myinst=biginst=ReadSL(myrombase+address); \
|
||||
else { HWReset(); return slice-IO_CYCLE; } \
|
||||
pc+=2; \
|
||||
IO_CYCLE-=(*jmp_table[(myinst<<16)>>19])(reg);
|
||||
|
||||
register unsigned long *p_reg=(unsigned long *)®[0];
|
||||
register unsigned long address;
|
||||
register int8 *mymembase=membase;
|
||||
register int8 *myrombase=rombase;
|
||||
register uint32 myinst;
|
||||
IO_CYCLE=slice;
|
||||
//Execute 10 instructions
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
return slice-IO_CYCLE;
|
||||
#undef cpuinst
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
|
||||
#include "fame.h"
|
||||
|
||||
|
||||
#if defined(DREAMCAST) || defined(USE_FAME_CORE_C)
|
||||
#define M68KCONTEXT m68kcontext
|
||||
#define IO_CYCLE io_cycle_counter
|
||||
#else
|
||||
#define M68KCONTEXT _m68kcontext
|
||||
#define IO_CYCLE __io_cycle_counter
|
||||
#endif
|
||||
|
||||
extern unsigned IO_CYCLE;
|
||||
|
||||
//extern struct M68K_CONTEXT M68KCONTEXT;
|
||||
extern M68K_CONTEXT M68KCONTEXT;
|
||||
extern int recalc_int;
|
||||
extern void SetMemW(unsigned long address, unsigned short value);
|
||||
extern void HWReset(void);
|
||||
|
||||
#define GetS() ((M68KCONTEXT.sr >> 13) & 1)
|
||||
#define GetFC2() GetS()
|
||||
#define GetI() ((M68KCONTEXT.sr >> 8) & 7)
|
||||
#ifdef DEBUG_FAME
|
||||
#define Interrupt(NUM,LEV) \
|
||||
{ \
|
||||
extern int fame_debug_output; \
|
||||
extern FILE *fame_debug_file; \
|
||||
if (fame_debug_output) \
|
||||
{ fprintf(fame_debug_file,"Interrupt(%i,%i)\n",(NUM),(LEV)); DEBUG_FAME_FFLUSH; } \
|
||||
m68k_lower_irq((LEV)); \
|
||||
m68k_raise_irq((LEV),(NUM)); \
|
||||
}
|
||||
#else
|
||||
#define Interrupt(NUM,LEV) \
|
||||
{ \
|
||||
M68KCONTEXT.interrupts[0] |= (1 << (LEV)); \
|
||||
M68KCONTEXT.interrupts[(LEV)]=(NUM); \
|
||||
M68KCONTEXT.execinfo &= 0x7F; \
|
||||
}
|
||||
#endif
|
||||
|
||||
#define ClearInterrupt(LEV) M68KCONTEXT.interrupts[0] &= ~(1 << (LEV))
|
||||
|
||||
|
||||
#define MEMADDRMASK 0x00ffffffl
|
||||
#define MEMADDRMASKS 0x00fffffel
|
||||
#define MEMIDXSHIFT 11
|
||||
#define MEMADDRSIZE (MEMADDRMASK + 1)
|
||||
#define AUTOINT2 26
|
||||
#define AUTOINT4 28
|
||||
#define BUSERR 2
|
||||
#define ADDRESSERR 3
|
||||
|
||||
char GetMemB(unsigned long address);
|
||||
short GetMemW(unsigned long address);
|
||||
void initialize_memmap(void);
|
||||
void ExceptionGroup0( int, unsigned long, int);
|
||||
void ExceptionGroup0_execute(void);
|
||||
|
||||
|
||||
#ifdef DEBUG_FAME
|
||||
static char dis_msg[96];
|
||||
static unsigned short dis_buf[10];
|
||||
void disassemble68k(char *buf, unsigned short *inst_stream);
|
||||
static __inline__ unsigned long cpu_loop(unsigned slice)
|
||||
{
|
||||
unsigned i;
|
||||
extern int number_exg0_fame;
|
||||
extern int in_fame_core;
|
||||
extern unsigned fame_debug_count;
|
||||
extern int fame_debug_output;
|
||||
extern FILE *fame_debug_file;
|
||||
|
||||
#ifdef DEBUG_FAME_START
|
||||
if (fame_debug_count>=((unsigned)(DEBUG_FAME_START)))
|
||||
fame_debug_output=1;
|
||||
else {
|
||||
unsigned long cycles_actual=M68KCONTEXT.cycles_counter;
|
||||
short lastint=M68KCONTEXT.sr&0x700;
|
||||
|
||||
in_fame_core=1;
|
||||
m68k_emulate(slice);
|
||||
in_fame_core=0;
|
||||
|
||||
fprintf(fame_debug_file,"SLICE(%u) %u (%u) ret=%u (%x %x)\n",slice,fame_debug_count,slice,M68KCONTEXT.cycles_counter-cycles_actual,M68KCONTEXT.execinfo&0x80,M68KCONTEXT.interrupts[0]);
|
||||
fame_debug_count++;
|
||||
|
||||
if (number_exg0_fame)
|
||||
ExceptionGroup0_execute();
|
||||
|
||||
if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700)))
|
||||
M68KCONTEXT.execinfo&=0x7f;
|
||||
|
||||
return (M68KCONTEXT.cycles_counter-cycles_actual);
|
||||
}
|
||||
|
||||
if (fame_debug_output)
|
||||
fprintf(fame_debug_file,"SLICE(%u) %u (%u)\n",slice,fame_debug_count,slice);
|
||||
#endif
|
||||
|
||||
in_fame_core=1;
|
||||
unsigned long cycles_actual=M68KCONTEXT.cycles_counter;
|
||||
short lastint=M68KCONTEXT.sr&0x700;
|
||||
while(M68KCONTEXT.cycles_counter-cycles_actual<slice)
|
||||
{
|
||||
if (fame_debug_output)
|
||||
{
|
||||
dis_msg[0]= 0;
|
||||
dis_buf[0]= m68k_fetch(m68k_get_pc(),0);
|
||||
dis_buf[1]= m68k_fetch(m68k_get_pc()+2,0);
|
||||
dis_buf[2]= m68k_fetch(m68k_get_pc()+4,0);
|
||||
dis_buf[3]= m68k_fetch(m68k_get_pc()+6,0);
|
||||
dis_buf[4]= m68k_fetch(m68k_get_pc()+8,0);
|
||||
dis_buf[5]= m68k_fetch(m68k_get_pc()+10,0);
|
||||
dis_buf[6]= m68k_fetch(m68k_get_pc()+12,0);
|
||||
dis_buf[7]= m68k_fetch(m68k_get_pc()+14,0);
|
||||
disassemble68k(dis_msg,dis_buf);
|
||||
fprintf(fame_debug_file,"- PC=%.8X (%s) SR=%.2X - INT=%.2X STAT=%.4X E0=%i\n",m68k_get_pc(), dis_msg, M68KCONTEXT.sr,M68KCONTEXT.interrupts[0],M68KCONTEXT.execinfo,number_exg0_fame);
|
||||
fprintf(fame_debug_file,"\tD0=%.8X D1=%.8X D2=%.8X D3=%.8X\n",M68KCONTEXT.dreg[0],M68KCONTEXT.dreg[1],M68KCONTEXT.dreg[2],M68KCONTEXT.dreg[3]);
|
||||
fprintf(fame_debug_file,"\tD4=%.8X D5=%.8X D6=%.8X D7=%.8X\n",M68KCONTEXT.dreg[4],M68KCONTEXT.dreg[5],M68KCONTEXT.dreg[6],M68KCONTEXT.dreg[7]);
|
||||
fprintf(fame_debug_file,"\tA0=%.8X A1=%.8X A2=%.8X A3=%.8X\n",M68KCONTEXT.areg[0],M68KCONTEXT.areg[1],M68KCONTEXT.areg[2],M68KCONTEXT.areg[3]);
|
||||
fprintf(fame_debug_file,"\tA4=%.8X A5=%.8X A6=%.8X A7=%.8X\n",M68KCONTEXT.areg[4],M68KCONTEXT.areg[5],M68KCONTEXT.areg[6],M68KCONTEXT.areg[7]);DEBUG_FAME_FFLUSH;
|
||||
}
|
||||
m68k_emulate(1);
|
||||
if (fame_debug_output)
|
||||
{ fputs(".",fame_debug_file); DEBUG_FAME_FFLUSH; }
|
||||
if (M68KCONTEXT.execinfo&0x80)
|
||||
break;
|
||||
}
|
||||
in_fame_core=0;
|
||||
|
||||
fame_debug_count++;
|
||||
|
||||
#ifdef DEBUG_FAME_STOP
|
||||
if (fame_debug_count>((unsigned)(DEBUG_FAME_STOP)))
|
||||
{
|
||||
#ifdef DEBUG_FAME_FILE
|
||||
extern FILE *fame_debug_file;
|
||||
if (fame_debug_file)
|
||||
fclose(fame_debug_file);
|
||||
fame_debug_file=NULL;
|
||||
#endif
|
||||
free(malloc(24*1024*1024)); exit(0); }
|
||||
#endif
|
||||
if (number_exg0_fame)
|
||||
{
|
||||
ExceptionGroup0_execute();
|
||||
number_exg0_fame=0;
|
||||
}
|
||||
if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700)))
|
||||
M68KCONTEXT.execinfo&=0x7f;
|
||||
return (M68KCONTEXT.cycles_counter-cycles_actual);
|
||||
}
|
||||
|
||||
#else
|
||||
static __inline__ unsigned long cpu_loop(unsigned slice)
|
||||
{
|
||||
extern int in_fame_core;
|
||||
extern int number_exg0_fame;
|
||||
|
||||
unsigned long cycles_actual=M68KCONTEXT.cycles_counter;
|
||||
short lastint=M68KCONTEXT.sr&0x700;
|
||||
|
||||
in_fame_core=1;
|
||||
m68k_emulate(slice);
|
||||
in_fame_core=0;
|
||||
|
||||
if (number_exg0_fame)
|
||||
ExceptionGroup0_execute();
|
||||
|
||||
if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700)))
|
||||
M68KCONTEXT.execinfo&=0x7f;
|
||||
|
||||
return (M68KCONTEXT.cycles_counter-cycles_actual);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
/*
|
||||
* Castaway
|
||||
* (C) 1994 - 2002 Martin Doering, Joachim Hoenig
|
||||
*
|
||||
* 68000.c - 68000 emulator jump table and misc subroutines
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*
|
||||
* revision history
|
||||
* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring
|
||||
* 09.06.2002 JH Use of mmap for memory access discontinued
|
||||
* 12.06.2002 JH Correct bus error/address error exception stack frame
|
||||
* 13.06.2002 JH Merged in Martin's BCD implementation (untested),
|
||||
* completed jump table. STOP is now the only
|
||||
* unimplemented instruction.
|
||||
* 14.06.2002 JH Implemented STOP, shutdown CPU after multiple bus errors.
|
||||
* Removed inst parameter from CPU opcode functions.
|
||||
* 19.06.2002 JH CPURun() returns # of executed instructions.
|
||||
* 20.06.2002 JH added yet another SR implementation variant.
|
||||
* 02.07.2002 JH Support different CPU types. Removed MOVE CCR,<EA> from
|
||||
* 68000 jump table.
|
||||
* 20.08.2002 JH Fixed CPU shutdown.
|
||||
* 27.08.2002 JH Bugfix: S and T flag incorrectly reported for group 0 exceptions
|
||||
* Implemented additional 68010 registers and instructions.
|
||||
* 31.08.2002 JH Implemented M68010 exception stack frames.
|
||||
* 08.10.2002 JH Implemented Trace exception
|
||||
*/
|
||||
static char sccsid[] = "$Id: 68000.c,v 1.18 2002/10/10 19:52:11 jhoenig Exp $";
|
||||
#include "config.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <assert.h>
|
||||
#include <setjmp.h>
|
||||
#include "68000.h"
|
||||
#include "mem.h"
|
||||
#include "st.h"
|
||||
#include "op68k.h"
|
||||
#include "proto.h"
|
||||
#include "operin.h"
|
||||
|
||||
|
||||
#if (CPU_TYPE == 68000 || CPU_TYPE == 68008)
|
||||
#include "op68000.h"
|
||||
#elif (CPU_TYPE == 68010) // broken
|
||||
#include "op68010.h"
|
||||
#endif
|
||||
extern int disass;
|
||||
unsigned long reg[23];
|
||||
unsigned long dfc, sfc, vbr;
|
||||
#define biginst reg[18]
|
||||
#define pc reg[19]
|
||||
#define usp reg[20]
|
||||
#define ssp reg[21]
|
||||
#define recalc_int reg[22]
|
||||
|
||||
|
||||
extern void StartDisass();
|
||||
unsigned short SaveWordTrc;
|
||||
unsigned char GetTrc;
|
||||
unsigned short int0=0;
|
||||
unsigned long exaddress=0x12345678;
|
||||
int intmask, intpri;
|
||||
char cpu_state;
|
||||
unsigned cpu_type;
|
||||
volatile unsigned cpu_count;
|
||||
|
||||
jmp_buf trap_buf;
|
||||
|
||||
|
||||
unsigned short GetSRB(void)
|
||||
{
|
||||
uint32 cvnz=reg[16]; //-------c-------v-------n-------z
|
||||
uint32 stx=reg[17]; //---------------s-------t-------x
|
||||
uint32 sr=(cvnz>>24)+(cvnz>>15)+(cvnz<<2)+(cvnz>>5)+(stx<<4);
|
||||
return sr&(unsigned short)0xff;
|
||||
}
|
||||
|
||||
unsigned short GetSRW(void)
|
||||
{
|
||||
uint32 cvnz=reg[16]; //-------c-------v-------n-------z
|
||||
uint32 stx=reg[17]; //---------------s-------t-------x
|
||||
uint32 sr=(cvnz>>24)+(cvnz>>15)+(cvnz<<2)+(cvnz>>5)+(stx<<4);
|
||||
uint32 sr2=(stx<<7)+(stx>>3)+(intmask<<8);
|
||||
return (sr&(unsigned short)0xff)+(sr2&(unsigned short)0xff00);
|
||||
}
|
||||
|
||||
|
||||
void SetSRB(unsigned long sr)
|
||||
{
|
||||
uint32 cvnz=((sr&1)<<24)+((sr&2)<<15)+((sr&4)>>2)+((sr&8)<<5);
|
||||
reg[16]=cvnz;
|
||||
SetX(sr&0x10);
|
||||
}
|
||||
|
||||
void SetSRW(unsigned long sr)
|
||||
{
|
||||
uint32 cvnz=((sr&1)<<24)+((sr&2)<<15)+((sr&4)>>2)+((sr&8)<<5);
|
||||
reg[16]=cvnz;
|
||||
SetX (sr&0x10);
|
||||
SetI ((sr&0x700)>>8);
|
||||
SetS (sr&0x2000);
|
||||
SetT (sr&0x8000);
|
||||
}
|
||||
|
||||
void ExceptionGroup0(
|
||||
int number,
|
||||
unsigned long address,
|
||||
int ReadWrite)
|
||||
{
|
||||
short sr = GetSRW(), context = 0;
|
||||
#ifdef DEBUG
|
||||
ON_TRAP(number);
|
||||
assert(cpu_state != -3);
|
||||
#endif
|
||||
if ((exaddress+1!=address)&&(exaddress+2!=address)&&(exaddress+3!=address)){
|
||||
if (cpu_state == 0) {
|
||||
cpu_state = -3;
|
||||
longjmp(trap_buf, 1);
|
||||
}
|
||||
#if CPU_TYPE == 68000
|
||||
else if (cpu_state > 0) {
|
||||
context |= 0x8;
|
||||
}
|
||||
if (ReadWrite) context |= 0x10;
|
||||
#else
|
||||
if (ReadWrite) context |= 0x100;
|
||||
#endif
|
||||
if (GetS()) context |= 0x4;
|
||||
if (ReadWrite && address == pc) context |= 0x2;
|
||||
else context |= 0x1;
|
||||
cpu_state = 0; /* begin group 0 exception processing */
|
||||
SetS (1);
|
||||
SetT (0);
|
||||
#if CPU_TYPE == 68010
|
||||
reg[15] -= 44; /* Rerun info */
|
||||
reg[15] -= 4; SetMemL(reg[15], address); /* fault address */
|
||||
reg[15] -= 2; SetMemW(reg[15], context);
|
||||
reg[15] -= 2; SetMemW(reg[15], 0x8000 | (number * 4));
|
||||
reg[15] -= 4; SetMemL(reg[15], GetPC());
|
||||
reg[15] -= 2; SetMemW(reg[15], sr);
|
||||
#else
|
||||
reg[15] = reg[15] - 14;
|
||||
SetMemW(reg[15], context);
|
||||
SetMemL(reg[15] + 2, address);
|
||||
SetMemW(reg[15] + 6, (uint16)biginst);
|
||||
SetMemW(reg[15] + 8, sr);
|
||||
SetMemL(reg[15] + 10, GetPC());
|
||||
#endif
|
||||
|
||||
SetPC (GetMemL ((long) number * 4) + vbr);
|
||||
/* end exception processing */
|
||||
cpu_state = -1;
|
||||
exaddress=address;
|
||||
|
||||
}
|
||||
int0=1;
|
||||
}
|
||||
|
||||
void ExceptionGroup1(int number)
|
||||
{
|
||||
|
||||
uint32 sp, newpc=pc;
|
||||
short sr = GetSRW();
|
||||
|
||||
if (number!=TRAPV) newpc-=2;
|
||||
SetS(1);
|
||||
SetT(0);
|
||||
sp=reg[15];
|
||||
sp-=4; SetMemL(sp, newpc);
|
||||
sp-=2; SetMemW(sp, sr);
|
||||
reg[15]=sp;
|
||||
SetPC (GetMemL(number*4+vbr));
|
||||
int0=1;
|
||||
}
|
||||
|
||||
void Interrupt(int number, int level)
|
||||
{
|
||||
uint32 sp;
|
||||
short sr = GetSRW();
|
||||
SetI(level); SetS(1); SetT(0);
|
||||
sp=reg[15];
|
||||
sp-=4; SetMemL(sp, GetPC());
|
||||
sp-=2; SetMemW(sp, sr);
|
||||
reg[15]=sp;
|
||||
SetPC (GetMemL(number*4+vbr));
|
||||
}
|
||||
|
||||
void ExceptionGroup2(int number)
|
||||
{
|
||||
uint32 sp;
|
||||
short sr = GetSRW();
|
||||
SetS(1); SetT(0);
|
||||
sp=reg[15];
|
||||
sp-=4; SetMemL(sp, GetPC());
|
||||
sp-=2; SetMemW(sp, sr);
|
||||
reg[15]=sp;
|
||||
SetPC (GetMemL(number*4+vbr));
|
||||
}
|
||||
|
||||
unsigned long Trace()
|
||||
{
|
||||
uint32 sp;
|
||||
short sr;
|
||||
register unsigned long cycleco=0;
|
||||
register unsigned long address,timeinst;
|
||||
register int8 *mymembase=membase;
|
||||
register int8 *myrombase=rombase;
|
||||
register uint32 myinst;
|
||||
address = pc&MEMADDRMASK;
|
||||
// disass=1;
|
||||
int0=0;
|
||||
if (address<MEMSIZE) myinst=biginst=ReadSL(mymembase+address);
|
||||
else if (address>=ROMBASE) myinst=biginst=ReadSL(myrombase+address);
|
||||
else { ExceptionGroup1(ADDRESSERR); return cycleco; }
|
||||
#ifdef DISASS
|
||||
if (disass==1) StoreTrace();
|
||||
#endif
|
||||
pc+=2;
|
||||
cycleco+=(*jmp_table[(myinst<<16)>>19])(reg);
|
||||
|
||||
if (!int0){
|
||||
sr = GetSRW();
|
||||
SetS(1); SetT(0);
|
||||
sp=reg[15];
|
||||
sp-=4; SetMemL(sp, GetPC());
|
||||
sp-=2; SetMemW(sp, sr);
|
||||
reg[15]=sp;
|
||||
SetPC (GetMemL(TRACE*4+vbr));
|
||||
return cycleco;
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
unsigned long IllIns(operin)
|
||||
{
|
||||
ExceptionGroup1(ILLINSTR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long Line_A(operin)
|
||||
{
|
||||
ExceptionGroup1(LINE_A);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long Line_F(operin)
|
||||
{
|
||||
ExceptionGroup1(LINE_F);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long Stop(void)
|
||||
{
|
||||
if (!GetS())
|
||||
ExceptionGroup1(PRIV);
|
||||
SetSRW(GetMPCW());
|
||||
pc += 2;
|
||||
cpu_state = -2; /* stopped */
|
||||
//longjmp(trap_buf, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void HWReset(void)
|
||||
{
|
||||
reg[15] = GetMemL (0l);
|
||||
SetPC(GetMemL (4l));
|
||||
SetI(7);
|
||||
SetT(0);
|
||||
SetS(1);
|
||||
cpu_state = -1; /* running */
|
||||
cpu_type = CPU_TYPE;
|
||||
}
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
/*
|
||||
* Castaway
|
||||
* (C) 1994 - 2002 Martin Doering, Joachim Hoenig
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*/
|
||||
#ifndef _68000H
|
||||
#define _68000H
|
||||
|
||||
#include "config.h" // wg. define
|
||||
#include "operin.h"
|
||||
|
||||
/*
|
||||
* Supported CPU types
|
||||
* CPU CPU_TYPE
|
||||
* MC68000 68000
|
||||
* MC68008 68000
|
||||
* MC68EC000 not supported (yet)
|
||||
* MC68010 68010
|
||||
* MC68020 68020
|
||||
* MC68EC020 not supported (yet)
|
||||
* MC68030 not supported (yet)
|
||||
* MC68EC030 not supported (yet)
|
||||
* MC68040 not supported (yet)
|
||||
* MC68EC040 not supported (yet)
|
||||
* CPU32 not supported (yet)
|
||||
*/
|
||||
#define CPU_TYPE 68000
|
||||
|
||||
/*
|
||||
* Exception vector numbers (trap numbers).
|
||||
*/
|
||||
#define RESET 0
|
||||
#define BUSERR 2
|
||||
#define ADDRESSERR 3
|
||||
#define ILLINSTR 4
|
||||
#define DIVZ 5
|
||||
#define TRAPCHK 6
|
||||
#define TRAPV 7
|
||||
#define PRIV 8
|
||||
#define TRACE 9
|
||||
#define LINE_A 10
|
||||
#define LINE_F 11
|
||||
#if CPU_TYPE != 68000
|
||||
#define FORMATERR 14
|
||||
#endif
|
||||
#define AUTOINT1 25
|
||||
#define AUTOINT2 26
|
||||
#define AUTOINT3 27
|
||||
#define AUTOINT4 28
|
||||
#define AUTOINT5 29
|
||||
#define AUTOINT6 30
|
||||
#define AUTOINT7 31
|
||||
#define TRAP0 32 + 0
|
||||
#define TRAP1 32 + 1
|
||||
#define TRAP2 32 + 2
|
||||
#define TRAP3 32 + 3
|
||||
#define TRAP4 32 + 4
|
||||
#define TRAP5 32 + 5
|
||||
#define TRAP6 32 + 6
|
||||
#define TRAP7 32 + 7
|
||||
#define TRAP8 32 + 8
|
||||
#define TRAP9 32 + 9
|
||||
#define TRAP10 32 + 10
|
||||
#define TRAP11 32 + 11
|
||||
#define TRAP12 32 + 12
|
||||
#define TRAP13 32 + 13
|
||||
#define TRAP14 32 + 14
|
||||
#define TRAP15 32 + 15
|
||||
|
||||
/* Group 0 exceptions (address error / bus error) */
|
||||
extern void ExceptionGroup0(
|
||||
int number, /* trap number */
|
||||
unsigned long address, /* fault address */
|
||||
int ReadWrite); /* read = true, write = false */
|
||||
/* Group 1 exceptions: illegal instruction, privilege violation, interrupts */
|
||||
extern void ExceptionGroup1(int number);
|
||||
extern void Interrupt(int number, int level);
|
||||
/* Group 2 exceptions: traps, divide by zero */
|
||||
extern void ExceptionGroup2(int number);
|
||||
|
||||
extern void HWReset(void); /* Reset */
|
||||
extern unsigned long IllIns(operin); /* Illegal instruction */
|
||||
extern unsigned long Line_A(operin); /* Axxx instruction opcode */
|
||||
extern unsigned long Line_F(operin); /* Fxxx instruction opcode */
|
||||
extern unsigned long Stop(void); /* Stop instruction */
|
||||
|
||||
extern unsigned char tracemode; //For Trace Switching
|
||||
extern unsigned short SaveWordTrc;
|
||||
extern unsigned char GetTrc;
|
||||
|
||||
/*
|
||||
* CPU Registers
|
||||
*
|
||||
* WARNING:
|
||||
* Never access registers directly from outside the emulator.
|
||||
* The internal representation of registers may change.
|
||||
*/
|
||||
/* Data and address registers are stored in native byte order.
|
||||
* register numbering: 0=d0, 1=d1, ..., 8=a0, 9=a1, ... 15=a7 */
|
||||
extern unsigned long reg[23];
|
||||
#define biginst reg[18]
|
||||
#define pc reg[19]
|
||||
#define usp reg[20]
|
||||
#define ssp reg[21]
|
||||
#define recalc_int reg[22]
|
||||
|
||||
|
||||
#define ins7 (biginst & 7)
|
||||
#define ins15 (biginst & 15)
|
||||
|
||||
/* 68010 registers */
|
||||
extern unsigned long dfc, sfc, vbr;
|
||||
/* 68020 registers */
|
||||
extern unsigned long caar, cacr, isp, msp;
|
||||
|
||||
extern int intmask;
|
||||
extern char cpu_state; /* 0, 1, 2 while processing exceptions,
|
||||
* -1 executing, -2 stopped, -3 shutdown */
|
||||
extern unsigned cpu_type; /* 68000, 68010 */
|
||||
|
||||
/*
|
||||
* Interrupts
|
||||
*
|
||||
* The state of interrupt lines IPL0-IPL2 is stored in the variable
|
||||
* intpri. The emulator acknowledges interrupts by calling QueryIRQ().
|
||||
* It expects the interrupt vector number to be returned.
|
||||
* WARNING:
|
||||
* Never update intpri asynchronously. Use the CPUEvent() function
|
||||
* to force CPURun() to return before updating intpri.
|
||||
*/
|
||||
extern int intpri;
|
||||
extern int QueryIRQ(int level); /* get interrupt vector number */
|
||||
|
||||
#define GetS() *(((int8*)reg)+70)
|
||||
#define GetFC2() GetS()
|
||||
#define GetFC1() address == pc
|
||||
#define GetFC0() address != pc
|
||||
#define GetFC() (((GetFC2() << 1) | GetFC1()) << 1) | GetFC0()
|
||||
|
||||
/*
|
||||
* memory access jump tables
|
||||
*/
|
||||
#define MEMADDRMASK 0x00ffffffl
|
||||
#define MEMADDRMASKS 0x00fffffel
|
||||
#define MEMIDXSHIFT 11
|
||||
#define MEMADDRSIZE (MEMADDRMASK + 1)
|
||||
#define MEMTABLESIZE (MEMADDRSIZE >> MEMIDXSHIFT)
|
||||
#define MEMBANKSIZE (MEMADDRSIZE / MEMTABLESIZE)
|
||||
#define MEMBANKMASK (MEMBANKSIZE - 1)
|
||||
|
||||
/* Fetch byte from address */
|
||||
char GetMemB(unsigned long address);
|
||||
short GetMemW(unsigned long address);
|
||||
long GetMemL(unsigned long address);
|
||||
void SetMemB (unsigned long address, unsigned char value);
|
||||
void SetMemW(unsigned long address, unsigned short value);
|
||||
void SetMemL(unsigned long address, unsigned long value);
|
||||
#ifdef DEBUG
|
||||
extern int stop_on;
|
||||
extern int verb_on;
|
||||
/* go to sleep (gives debugger a chance to attach) */
|
||||
void DebugStop(void);
|
||||
#ifdef TRACEBACK
|
||||
/*
|
||||
* execution trace
|
||||
*/
|
||||
struct state {
|
||||
uint32 reg[16];
|
||||
uint32 stack[8];
|
||||
uint32 pc, usp, ssp;
|
||||
uint16 inst[5];
|
||||
uint16 sr;
|
||||
|
||||
};
|
||||
extern int hide_supervisor;
|
||||
extern unsigned long instcnt;
|
||||
extern int tbi;
|
||||
extern struct state traceback[TRACEBACK];
|
||||
extern int trace_on;
|
||||
/* print execution trace of last TRACEBACK instructions and sleep */
|
||||
void TraceStop(void);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#
|
||||
# Component Makefile
|
||||
#
|
||||
# This Makefile can be left empty. By default, it will take the sources in the
|
||||
# src/ directory, compile them and link them into lib(subdirectory_name).a
|
||||
# in the build directory. This behaviour is entirely configurable,
|
||||
# please read the ESP-IDF documents if you need to do this.
|
||||
#
|
||||
|
||||
COMPONENT_ADD_INCLUDEDIRS := . ..
|
||||
COMPONENT_SRCDIRS := .
|
||||
|
||||
CPPFLAGS += -DNO_SOUND #-DEMULATED_JOYSTICK -DUSE_SHORT_SLICE -DUSE_DOUBLE_BUFFER
|
||||
CPPFLAGS += -fpermissive -O3 -ffast-math
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "config.h"
|
||||
#include "dcastaway.h"
|
||||
|
||||
extern int waitstate;
|
||||
|
||||
#ifndef USE_FAME_CORE
|
||||
|
||||
#include "68000.h"
|
||||
#include "op68k.h"
|
||||
|
||||
extern unsigned IO_CYCLE;
|
||||
|
||||
static __inline__ unsigned long cpu_loop(unsigned slice) {
|
||||
|
||||
extern const unsigned long (*jmp_table[8192])(operin);
|
||||
|
||||
#define initialize_memmap()
|
||||
|
||||
#define cpuinst \
|
||||
address = pc&MEMADDRMASK; \
|
||||
if (address<MEMSIZE) myinst=biginst=ReadSL(mymembase+address); \
|
||||
else if (address>=ROMBASE2) myinst=biginst=ReadSL(myrombase+address); \
|
||||
else { HWReset(); return slice-IO_CYCLE; } \
|
||||
pc+=2; \
|
||||
IO_CYCLE-=(*jmp_table[(myinst<<16)>>19])(reg);
|
||||
|
||||
register unsigned long *p_reg=(unsigned long *)®[0];
|
||||
register unsigned long address;
|
||||
register int8 *mymembase=membase;
|
||||
register int8 *myrombase=rombase;
|
||||
register uint32 myinst;
|
||||
IO_CYCLE=slice;
|
||||
//Execute 10 instructions
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
cpuinst
|
||||
return slice-IO_CYCLE;
|
||||
#undef cpuinst
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
|
||||
#include "fame.h"
|
||||
|
||||
|
||||
#if defined(DREAMCAST) || defined(USE_FAME_CORE_C)
|
||||
#define M68KCONTEXT m68kcontext
|
||||
#define IO_CYCLE io_cycle_counter
|
||||
#else
|
||||
#define M68KCONTEXT _m68kcontext
|
||||
#define IO_CYCLE __io_cycle_counter
|
||||
#endif
|
||||
|
||||
extern unsigned IO_CYCLE;
|
||||
|
||||
//extern struct M68K_CONTEXT M68KCONTEXT;
|
||||
extern M68K_CONTEXT M68KCONTEXT;
|
||||
extern int recalc_int;
|
||||
extern void SetMemW(unsigned long address, unsigned short value);
|
||||
extern void HWReset(void);
|
||||
|
||||
#define GetS() ((M68KCONTEXT.sr >> 13) & 1)
|
||||
#define GetFC2() GetS()
|
||||
#define GetI() ((M68KCONTEXT.sr >> 8) & 7)
|
||||
#ifdef DEBUG_FAME
|
||||
#define Interrupt(NUM,LEV) \
|
||||
{ \
|
||||
extern int fame_debug_output; \
|
||||
extern FILE *fame_debug_file; \
|
||||
if (fame_debug_output) \
|
||||
{ fprintf(fame_debug_file,"Interrupt(%i,%i)\n",(NUM),(LEV)); DEBUG_FAME_FFLUSH; } \
|
||||
m68k_lower_irq((LEV)); \
|
||||
m68k_raise_irq((LEV),(NUM)); \
|
||||
}
|
||||
#else
|
||||
#define Interrupt(NUM,LEV) \
|
||||
{ \
|
||||
M68KCONTEXT.interrupts[0] |= (1 << (LEV)); \
|
||||
M68KCONTEXT.interrupts[(LEV)]=(NUM); \
|
||||
M68KCONTEXT.execinfo &= 0x7F; \
|
||||
}
|
||||
#endif
|
||||
|
||||
#define ClearInterrupt(LEV) M68KCONTEXT.interrupts[0] &= ~(1 << (LEV))
|
||||
|
||||
|
||||
#define MEMADDRMASK 0x00ffffffl
|
||||
#define MEMADDRMASKS 0x00fffffel
|
||||
#define MEMIDXSHIFT 11
|
||||
#define MEMADDRSIZE (MEMADDRMASK + 1)
|
||||
#define AUTOINT2 26
|
||||
#define AUTOINT4 28
|
||||
#define BUSERR 2
|
||||
#define ADDRESSERR 3
|
||||
|
||||
char GetMemB(unsigned long address);
|
||||
short GetMemW(unsigned long address);
|
||||
void initialize_memmap(void);
|
||||
void ExceptionGroup0( int, unsigned long, int);
|
||||
void ExceptionGroup0_execute(void);
|
||||
|
||||
|
||||
#ifdef DEBUG_FAME
|
||||
static char dis_msg[96];
|
||||
static unsigned short dis_buf[10];
|
||||
void disassemble68k(char *buf, unsigned short *inst_stream);
|
||||
static __inline__ unsigned long cpu_loop(unsigned slice)
|
||||
{
|
||||
unsigned i;
|
||||
extern int number_exg0_fame;
|
||||
extern int in_fame_core;
|
||||
extern unsigned fame_debug_count;
|
||||
extern int fame_debug_output;
|
||||
extern FILE *fame_debug_file;
|
||||
|
||||
#ifdef DEBUG_FAME_START
|
||||
if (fame_debug_count>=((unsigned)(DEBUG_FAME_START)))
|
||||
fame_debug_output=1;
|
||||
else {
|
||||
unsigned long cycles_actual=M68KCONTEXT.cycles_counter;
|
||||
short lastint=M68KCONTEXT.sr&0x700;
|
||||
|
||||
in_fame_core=1;
|
||||
m68k_emulate(slice);
|
||||
in_fame_core=0;
|
||||
|
||||
fprintf(fame_debug_file,"SLICE(%u) %u (%u) ret=%u (%x %x)\n",slice,fame_debug_count,slice,M68KCONTEXT.cycles_counter-cycles_actual,M68KCONTEXT.execinfo&0x80,M68KCONTEXT.interrupts[0]);
|
||||
fame_debug_count++;
|
||||
|
||||
if (number_exg0_fame)
|
||||
ExceptionGroup0_execute();
|
||||
|
||||
if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700)))
|
||||
M68KCONTEXT.execinfo&=0x7f;
|
||||
|
||||
return (M68KCONTEXT.cycles_counter-cycles_actual);
|
||||
}
|
||||
|
||||
if (fame_debug_output)
|
||||
fprintf(fame_debug_file,"SLICE(%u) %u (%u)\n",slice,fame_debug_count,slice);
|
||||
#endif
|
||||
|
||||
in_fame_core=1;
|
||||
unsigned long cycles_actual=M68KCONTEXT.cycles_counter;
|
||||
short lastint=M68KCONTEXT.sr&0x700;
|
||||
while(M68KCONTEXT.cycles_counter-cycles_actual<slice)
|
||||
{
|
||||
if (fame_debug_output)
|
||||
{
|
||||
dis_msg[0]= 0;
|
||||
dis_buf[0]= m68k_fetch(m68k_get_pc(),0);
|
||||
dis_buf[1]= m68k_fetch(m68k_get_pc()+2,0);
|
||||
dis_buf[2]= m68k_fetch(m68k_get_pc()+4,0);
|
||||
dis_buf[3]= m68k_fetch(m68k_get_pc()+6,0);
|
||||
dis_buf[4]= m68k_fetch(m68k_get_pc()+8,0);
|
||||
dis_buf[5]= m68k_fetch(m68k_get_pc()+10,0);
|
||||
dis_buf[6]= m68k_fetch(m68k_get_pc()+12,0);
|
||||
dis_buf[7]= m68k_fetch(m68k_get_pc()+14,0);
|
||||
disassemble68k(dis_msg,dis_buf);
|
||||
fprintf(fame_debug_file,"- PC=%.8X (%s) SR=%.2X - INT=%.2X STAT=%.4X E0=%i\n",m68k_get_pc(), dis_msg, M68KCONTEXT.sr,M68KCONTEXT.interrupts[0],M68KCONTEXT.execinfo,number_exg0_fame);
|
||||
fprintf(fame_debug_file,"\tD0=%.8X D1=%.8X D2=%.8X D3=%.8X\n",M68KCONTEXT.dreg[0],M68KCONTEXT.dreg[1],M68KCONTEXT.dreg[2],M68KCONTEXT.dreg[3]);
|
||||
fprintf(fame_debug_file,"\tD4=%.8X D5=%.8X D6=%.8X D7=%.8X\n",M68KCONTEXT.dreg[4],M68KCONTEXT.dreg[5],M68KCONTEXT.dreg[6],M68KCONTEXT.dreg[7]);
|
||||
fprintf(fame_debug_file,"\tA0=%.8X A1=%.8X A2=%.8X A3=%.8X\n",M68KCONTEXT.areg[0],M68KCONTEXT.areg[1],M68KCONTEXT.areg[2],M68KCONTEXT.areg[3]);
|
||||
fprintf(fame_debug_file,"\tA4=%.8X A5=%.8X A6=%.8X A7=%.8X\n",M68KCONTEXT.areg[4],M68KCONTEXT.areg[5],M68KCONTEXT.areg[6],M68KCONTEXT.areg[7]);DEBUG_FAME_FFLUSH;
|
||||
}
|
||||
m68k_emulate(1);
|
||||
if (fame_debug_output)
|
||||
{ fputs(".",fame_debug_file); DEBUG_FAME_FFLUSH; }
|
||||
if (M68KCONTEXT.execinfo&0x80)
|
||||
break;
|
||||
}
|
||||
in_fame_core=0;
|
||||
|
||||
fame_debug_count++;
|
||||
|
||||
#ifdef DEBUG_FAME_STOP
|
||||
if (fame_debug_count>((unsigned)(DEBUG_FAME_STOP)))
|
||||
{
|
||||
#ifdef DEBUG_FAME_FILE
|
||||
extern FILE *fame_debug_file;
|
||||
if (fame_debug_file)
|
||||
fclose(fame_debug_file);
|
||||
fame_debug_file=NULL;
|
||||
#endif
|
||||
free(malloc(24*1024*1024)); exit(0); }
|
||||
#endif
|
||||
if (number_exg0_fame)
|
||||
{
|
||||
ExceptionGroup0_execute();
|
||||
number_exg0_fame=0;
|
||||
}
|
||||
if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700)))
|
||||
M68KCONTEXT.execinfo&=0x7f;
|
||||
return (M68KCONTEXT.cycles_counter-cycles_actual);
|
||||
}
|
||||
|
||||
#else
|
||||
static __inline__ unsigned long cpu_loop(unsigned slice)
|
||||
{
|
||||
extern int in_fame_core;
|
||||
extern int number_exg0_fame;
|
||||
|
||||
unsigned long cycles_actual=M68KCONTEXT.cycles_counter;
|
||||
short lastint=M68KCONTEXT.sr&0x700;
|
||||
|
||||
in_fame_core=1;
|
||||
m68k_emulate(slice);
|
||||
in_fame_core=0;
|
||||
|
||||
if (number_exg0_fame)
|
||||
ExceptionGroup0_execute();
|
||||
|
||||
if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700)))
|
||||
M68KCONTEXT.execinfo&=0x7f;
|
||||
|
||||
return (M68KCONTEXT.cycles_counter-cycles_actual);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,577 @@
|
|||
/*
|
||||
* Castaway
|
||||
* (C) 1994 - 2002 Martin Doering, Joachim Hoenig
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*/
|
||||
#ifndef OP68KH
|
||||
#define OP68KH
|
||||
|
||||
#include "config.h"
|
||||
#include "operin.h"
|
||||
|
||||
extern short GetMemWpc(unsigned long address);
|
||||
extern long GetMemLpc(unsigned long address);
|
||||
extern void SetMemPL(unsigned long address, unsigned long value);
|
||||
extern void SetMemPW(unsigned long address, unsigned long value);
|
||||
|
||||
|
||||
/*
|
||||
* Status Register Access
|
||||
*/
|
||||
//AG: Changed to yet another SR implementation which is faster
|
||||
//Note this code is little endian dependant and will need changing for big endian machines
|
||||
|
||||
//reg[16]=ZNVC
|
||||
//reg[17]=XTS-
|
||||
//reg[18]=inst
|
||||
|
||||
#define Zflag 0x1
|
||||
#define Nflag 0x100
|
||||
#define Vflag 0x10000
|
||||
#define Cflag 0x1000000
|
||||
|
||||
#define SetC(flag) if (flag) *(((int8*)reg)+67)=1; else *(((int8*)reg)+67)=0;
|
||||
#define SetV(flag) if (flag) *(((int8*)reg)+66)=1; else *(((int8*)reg)+66)=0;
|
||||
#define SetX(flag) if (flag) *(((int8*)reg)+68)=1; else *(((int8*)reg)+68)=0;
|
||||
#define SetT(flag) if (flag) *(((int8*)reg)+69)=1; else *(((int8*)reg)+69)=0;
|
||||
#define SetZ(flag) if (flag) *(((int8*)reg)+64)=1; else *(((int8*)reg)+64)=0;
|
||||
#define SetZI(flag) if (flag) *(((int8*)reg)+64)=0; else *(((int8*)reg)+64)=1;
|
||||
#define SetN(flag) if (flag) *(((int8*)reg)+65)=1; else *(((int8*)reg)+65)=0;
|
||||
#define SetXC(flag) if (flag) *(((int8*)reg)+68)=*(((int8*)reg)+67)=1; else *(((int8*)reg)+68)=*(((int8*)reg)+67)=0;
|
||||
|
||||
#define ForceX(flag) *(((int8*)reg)+68)=flag;
|
||||
#define ForceC(flag) *(((int8*)reg)+67)=flag;
|
||||
#define ForceV(flag) *(((int8*)reg)+66)=flag;
|
||||
#define ForceZ(flag) *(((int8*)reg)+64)=flag;
|
||||
#define ForceCVNZ(operand) reg[16]=operand;
|
||||
|
||||
#define ZeroZ(flag) if (flag) *(((int8*)reg)+64)=0;
|
||||
|
||||
#define SetNZ(operand) \
|
||||
if (operand==0) *(((int16*)reg)+32)=0x1; \
|
||||
else if (operand<0) *(((int16*)reg)+32)=0x100; \
|
||||
else *(((int16*)reg)+32)=0;
|
||||
|
||||
#define SetI(imask) intmask=(imask); recalc_int=1;
|
||||
|
||||
#define SetS(flag) \
|
||||
if (*(((int8*)reg)+70)) ssp=reg[15]; else usp=reg[15]; \
|
||||
if (flag) {*(((int8*)reg)+70)=1; reg[15]=ssp;} else {*(((int8*)reg)+70)=0; reg[15]=usp;}
|
||||
|
||||
#define ClrCVSetNZ(operand) \
|
||||
if (operand==0) reg[16]=0x1; \
|
||||
else if (operand<0) reg[16]=0x100; \
|
||||
else reg[16]=0;
|
||||
|
||||
#define GetC() *(((int8*)reg)+67)
|
||||
#define GetV() *(((int8*)reg)+66)
|
||||
#define GetZ() *(((int8*)reg)+64)
|
||||
#define GetN() *(((int8*)reg)+65)
|
||||
#define GetX() *(((int8*)reg)+68)
|
||||
#define GetI() intmask
|
||||
#define GetS() *(((int8*)reg)+70)
|
||||
#define GetT() *(((int8*)reg)+69)
|
||||
|
||||
//-------------------------------
|
||||
|
||||
extern uint16 GetSRB(void);
|
||||
extern uint16 GetSRW(void);
|
||||
extern void SetSRB(unsigned long);
|
||||
extern void SetSRW(unsigned long);
|
||||
|
||||
|
||||
/*
|
||||
* Other Register Access
|
||||
*/
|
||||
#define GetPC() pc
|
||||
#define SetPC(addr) pc = addr
|
||||
|
||||
#define FastMPCB() (char)(biginst>>16)
|
||||
#define FastMPCW() (((int32)biginst)>>16)
|
||||
#define FastMPCW32() (biginst>>16)
|
||||
|
||||
#define GetMPCB() GetMemBpc (pc + 1)
|
||||
#define GetMPCW() GetMemWpc (pc)
|
||||
#define GetMPCL() GetMemLpc (pc)
|
||||
|
||||
#define IncMPCB(var) {register uint32 regpc=pc; pc=regpc+2; var=GetMemBpc (regpc+1);}
|
||||
#define IncMPCW(var) {register uint32 regpc=pc; pc=regpc+2; var=GetMemWpc (regpc);}
|
||||
#define IncMPCL(var) {register uint32 regpc=pc; pc=regpc+4; var=GetMemLpc (regpc);}
|
||||
|
||||
#define GetRegB(regno) (int8) reg[regno]
|
||||
#define GetRegW(regno) (int16) reg[regno]
|
||||
#define GetRegL(regno) (int32) reg[regno]
|
||||
|
||||
#define GetARegW(regno) (int16) reg[regno+8]
|
||||
#define GetARegL(regno) (int32) reg[regno+8]
|
||||
|
||||
#ifndef USE_LITTLE_ENDIAN /* USE_BIG_ENDIAN */
|
||||
#define SetRegB(regno, value) *(((int8 *) ®[regno]) + 3) = value
|
||||
#define SetRegW(regno, value) *(((int16 *) ®[regno]) + 1) = value
|
||||
#define SetARegW(regno, value) *(((int16 *) ®[regno+8]) + 1) = value
|
||||
#else /* USE_LITTLE_ENDIAN */
|
||||
#define SetRegB(regno, value) *((int8 *) ®[regno]) = value
|
||||
#define SetRegW(regno, value) *((int16 *) ®[regno]) = value
|
||||
#define SetARegW(regno, value) *((int16 *) ®[regno+8]) = value
|
||||
#endif
|
||||
#define SetRegL(regno, value) reg[regno] = value
|
||||
#define SetARegL(regno, value) reg[regno+8] = value
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Addressing modes (target)
|
||||
*/
|
||||
/* d, a, ain, aip, mai, dai, aix, imm, (eaw,ear,eac) */
|
||||
#define CN(address,spec)
|
||||
#define Cs(address,spec) address=spec;
|
||||
#define Cd(address,spec) address=spec;
|
||||
#define Ca(address,spec) address=8+spec;
|
||||
#define Cain(address,spec) address=reg[spec+8];
|
||||
#define CaipW(address,spec) address=reg[spec+8]; reg[spec+8]=address+2;
|
||||
#define CaipL(address,spec) address=reg[spec+8]; reg[spec+8]=address+4;
|
||||
#define CmaiW(address,spec) address=reg[spec+8]; address-=2; reg[spec+8]=address;
|
||||
#define CmaiL(address,spec) address=reg[spec+8]; address-=4; reg[spec+8]=address;
|
||||
#define Cdai(address,spec) IncMPCW(address); address+=reg[spec+8];
|
||||
#define Caix(address,spec) { register uint16 mod = GetMPCW(); pc += 2; address = reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)); }
|
||||
#define CaipB(address,spec) address=reg[spec+8]; if (spec==7) reg[spec+8]=address+2; else reg[spec+8]=address+1;
|
||||
#define CaipB15(address,spec) address=reg[spec+8]; reg[spec+8]=address+2;
|
||||
|
||||
#define CmaiB(address,spec) address=reg[spec+8]; if (spec==7) address-=2; else address--; reg[spec+8]=address;
|
||||
#define CmaiB15(address,spec) address=reg[spec+8]; address-=2; reg[spec+8]=address;
|
||||
|
||||
#define Ceaw(address, spec) \
|
||||
switch (spec) {\
|
||||
case 0x0:\
|
||||
IncMPCW(address);\
|
||||
break;\
|
||||
case 0x1:\
|
||||
IncMPCL(address);\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
default:\
|
||||
ExceptionGroup1(ILLINSTR);\
|
||||
address = 0;\
|
||||
break;\
|
||||
}
|
||||
#define Cear(address,spec) \
|
||||
{ register uint16 mod;\
|
||||
register uint32 regpc=pc;\
|
||||
switch (spec) {\
|
||||
case 0x0:\
|
||||
pc=regpc+2;\
|
||||
address = GetMemWpc(regpc);\
|
||||
break;\
|
||||
case 0x1:\
|
||||
pc=regpc+4;\
|
||||
address = GetMemLpc(regpc);\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
case 0x2:\
|
||||
pc=regpc+2;\
|
||||
address = regpc + GetMemWpc(regpc);\
|
||||
break;\
|
||||
case 0x3:\
|
||||
pc=regpc+2;\
|
||||
mod = GetMemWpc(regpc);\
|
||||
address = regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12));\
|
||||
cycles += 2;\
|
||||
break;\
|
||||
default:\
|
||||
ExceptionGroup1(ILLINSTR);\
|
||||
address = 0;\
|
||||
break;\
|
||||
}}
|
||||
|
||||
//Faster version of effective address macros
|
||||
//Only use these when the pc hasn't been advanced by an earlier macro
|
||||
#define Fdai(address,spec) address=FastMPCW()+reg[spec+8]; pc+=2;
|
||||
#define Faix(address,spec) {register uint32 mod=FastMPCW32(); pc += 2; address = reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)); }
|
||||
#define Feaw(address, spec) \
|
||||
switch (spec) {\
|
||||
case 0x0:\
|
||||
address=FastMPCW(); pc+=2;\
|
||||
break;\
|
||||
case 0x1:\
|
||||
IncMPCL(address);\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
default:\
|
||||
ExceptionGroup1(ILLINSTR);\
|
||||
address = 0;\
|
||||
break;\
|
||||
}
|
||||
#define Fear(address,spec) \
|
||||
{ register uint32 mod;\
|
||||
register uint32 regpc=pc;\
|
||||
switch (spec) {\
|
||||
case 0x0:\
|
||||
pc=regpc+2;\
|
||||
address = FastMPCW();\
|
||||
break;\
|
||||
case 0x1:\
|
||||
pc=regpc+4;\
|
||||
address = GetMemLpc(regpc);\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
case 0x2:\
|
||||
pc=regpc+2;\
|
||||
address = regpc + FastMPCW();\
|
||||
break;\
|
||||
case 0x3:\
|
||||
pc=regpc+2;\
|
||||
mod = FastMPCW32();\
|
||||
address = regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12));\
|
||||
cycles += 2;\
|
||||
break;\
|
||||
default:\
|
||||
ExceptionGroup1(ILLINSTR);\
|
||||
address = 0;\
|
||||
break;\
|
||||
}}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Operand types: B byte, W word, L long, R regno, A address
|
||||
*/
|
||||
#define DN(name)
|
||||
#define DB(name) register int8 name;
|
||||
#define DW(name) register int16 name;
|
||||
#define DL(name) register int32 name;
|
||||
#define DR(name) register uint16 name;
|
||||
#define DA(name) register int32 name;
|
||||
|
||||
|
||||
/*
|
||||
* target macros
|
||||
*/
|
||||
#define GRB(regno, name) name = GetRegB (regno);
|
||||
#define GRW(regno, name) name = GetRegW (regno);
|
||||
#define GRL(regno, name) name = GetRegL (regno);
|
||||
#define SRB(regno, name) SetRegB (regno, name);
|
||||
#define SRW(regno, name) SetRegW (regno, name);
|
||||
#define SRL(regno, name) SetRegL (regno, name);
|
||||
#define GMB(address, name) name = GetMemB (address);
|
||||
#define GMW(address, name) name = GetMemW (address);
|
||||
#define GML(address, name) name = GetMemL (address);
|
||||
#define GN(address, name)
|
||||
#define SMB(address, name) SetMemB (address, name);
|
||||
#define SMW(address, name) SetMemW (address, name);
|
||||
#define SML(address, name) SetMemL (address, name);
|
||||
#define SN(address, name)
|
||||
#define GCB(dummy, name) name = GetSRB ();
|
||||
#define GCW(dummy, name) name = GetSRW ();
|
||||
#define SCB(dummy, name) SetSRB (name);
|
||||
#define SCW(dummy, name) SetSRW (name);
|
||||
#define GPW(address, name) \
|
||||
name = GetMemB(address);\
|
||||
name <<= 8;\
|
||||
name |= (uint8) GetMemB(address + 2);
|
||||
#define GPL(address, name) \
|
||||
name = GetMemB(address);\
|
||||
name <<= 8;\
|
||||
name |= (uint8) GetMemB(address + 2);\
|
||||
name <<= 8;\
|
||||
name |= (uint8) GetMemB(address + 4);\
|
||||
name <<= 8;\
|
||||
name |= (uint8) GetMemB(address + 6);
|
||||
#define SPW(address, name) \
|
||||
SetMemPW(address, name);
|
||||
#define SPL(address, name) \
|
||||
SetMemPL(address, name);
|
||||
|
||||
|
||||
/*
|
||||
* source macros
|
||||
*/
|
||||
#define SdaiPW(var,spec) {uint32 a; Cdai(a,spec); var = GPW(a,var);}
|
||||
#define SdaiPL(var,spec) {uint32 a; Cdai(a,spec); var = GPL(a,var);}
|
||||
#define SNN(var,spec)
|
||||
#define SNQ(var, dummy) var = (int8) biginst;
|
||||
#define ScB(var,spec) var = GetSRB();
|
||||
#define ScW(var,spec) var = GetSRW();
|
||||
#define Ss(var,spec) var = spec;
|
||||
#define SimmB(var,spec) var=FastMPCB(); pc+=2;
|
||||
#define SimmW(var,spec) var=FastMPCW(); pc+=2;
|
||||
#define SimmL(var,spec) IncMPCL(var);
|
||||
#define SdB(var,spec) var = GetRegB (spec);
|
||||
#define SdW(var,spec) var = GetRegW (spec);
|
||||
#define SdL(var,spec) var = GetRegL (spec);
|
||||
#define SaW(var,spec) var = GetARegW (spec);
|
||||
#define SaL(var,spec) var = GetARegL (spec);
|
||||
#define SainB(var,spec) var = GetMemB (reg[spec+8]);
|
||||
#define SainW(var,spec) var = GetMemW (reg[spec+8]);
|
||||
#define SainL(var,spec) var = GetMemL (reg[spec+8]);
|
||||
#define SainA(var,spec) var = (reg[spec+8]);
|
||||
#define SaipW(var,spec) {register uint32 myadr=reg[spec+8]; reg[spec+8]=myadr+2; var=GetMemW(myadr);}
|
||||
#define SaipL(var,spec) {register uint32 myadr=reg[spec+8]; reg[spec+8]=myadr+4; var=GetMemL(myadr);}
|
||||
#define SmaiW(var,spec) {register uint32 myadr=reg[spec+8]; myadr-=2; reg[spec+8]=myadr; var=GetMemW(myadr);}
|
||||
#define SmaiL(var,spec) {register uint32 myadr=reg[spec+8]; myadr-=4; reg[spec+8]=myadr; var=GetMemL(myadr);}
|
||||
#define SdaiB(var,spec) var = GetMemB(reg[spec+8]+FastMPCW()); pc+=2;
|
||||
#define SdaiW(var,spec) var = GetMemW(reg[spec+8]+FastMPCW()); pc+=2;
|
||||
#define SdaiL(var,spec) var = GetMemL(reg[spec+8]+FastMPCW()); pc+=2;
|
||||
#define SdaiA(var,spec) var = reg[spec+8]+FastMPCW(); pc+=2;
|
||||
#define SaixB(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = GetMemB(reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));};
|
||||
#define SaixW(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = GetMemW(reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));};
|
||||
#define SaixL(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = GetMemL(reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));};
|
||||
#define SaixA(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = (reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));};
|
||||
#define SaipB(var,spec) {register uint32 myadr=reg[spec+8]; if (spec==7) reg[spec+8]=myadr+2; else reg[spec+8]=myadr+1; var=GetMemB(myadr);}
|
||||
#define SmaiB(var,spec) {register uint32 myadr=reg[spec+8]; if (spec==7) myadr-=2; else myadr--; reg[spec+8]=myadr; var=GetMemB(myadr);}
|
||||
|
||||
#define SearB(var,spec) \
|
||||
{ register uint32 mod;\
|
||||
register uint32 regpc=pc;\
|
||||
switch (spec) {\
|
||||
case 0x0:\
|
||||
pc=regpc+2;\
|
||||
var = GetMemB (FastMPCW());\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
case 0x1:\
|
||||
pc=regpc+4;\
|
||||
var = GetMemB (GetMemLpc(regpc));\
|
||||
cycles += 8;\
|
||||
break;\
|
||||
case 0x2:\
|
||||
pc=regpc+2;\
|
||||
var = GetMemB (regpc+FastMPCW());\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
case 0x3:\
|
||||
pc=regpc+2;\
|
||||
mod = FastMPCW32();\
|
||||
var = GetMemB (regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));\
|
||||
cycles += 6;\
|
||||
break;\
|
||||
case 0x4:\
|
||||
pc=regpc+2;\
|
||||
var = FastMPCB();\
|
||||
break;\
|
||||
default:\
|
||||
ExceptionGroup1(ILLINSTR);\
|
||||
var = 0;\
|
||||
break;\
|
||||
}}
|
||||
#define SearW(var,spec) \
|
||||
{ register uint32 mod;\
|
||||
register uint32 regpc=pc;\
|
||||
switch (spec) {\
|
||||
case 0x0:\
|
||||
pc=regpc+2;\
|
||||
var = GetMemW (FastMPCW());\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
case 0x1:\
|
||||
pc=regpc+4;\
|
||||
var = GetMemW (GetMemLpc(regpc));\
|
||||
cycles += 8;\
|
||||
break;\
|
||||
case 0x2:\
|
||||
pc=regpc+2;\
|
||||
var = GetMemW (regpc+FastMPCW());\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
case 0x3:\
|
||||
pc=regpc+2;\
|
||||
mod = FastMPCW32();\
|
||||
var = GetMemW (regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));\
|
||||
cycles += 6;\
|
||||
break;\
|
||||
case 0x4:\
|
||||
pc=regpc+2;\
|
||||
var = FastMPCW();\
|
||||
break;\
|
||||
default:\
|
||||
ExceptionGroup1(ILLINSTR);\
|
||||
var = 0;\
|
||||
break;\
|
||||
}}
|
||||
#define SearL(var,spec) \
|
||||
{ register uint32 mod;\
|
||||
register uint32 regpc=pc;\
|
||||
switch (spec) {\
|
||||
case 0x0:\
|
||||
pc=regpc+2;\
|
||||
var = GetMemL (FastMPCW());\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
case 0x1:\
|
||||
pc=regpc+4;\
|
||||
var = GetMemL (GetMemLpc(regpc));\
|
||||
cycles += 8;\
|
||||
break;\
|
||||
case 0x2:\
|
||||
pc=regpc+2;\
|
||||
var = GetMemL (regpc+FastMPCW());\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
case 0x3:\
|
||||
pc=regpc+2;\
|
||||
mod = FastMPCW32();\
|
||||
var = GetMemL (regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));\
|
||||
cycles += 6;\
|
||||
break;\
|
||||
case 0x4:\
|
||||
pc=regpc+4;\
|
||||
var = GetMemLpc(regpc);\
|
||||
break;\
|
||||
default:\
|
||||
ExceptionGroup1(ILLINSTR);\
|
||||
var = 0;\
|
||||
break;\
|
||||
}}
|
||||
#define SearA(var,spec) \
|
||||
{ register uint32 mod;\
|
||||
register uint32 regpc=pc;\
|
||||
switch (spec) {\
|
||||
case 0x0:\
|
||||
pc=regpc+2;\
|
||||
var = FastMPCW();\
|
||||
break;\
|
||||
case 0x1:\
|
||||
pc=regpc+4;\
|
||||
var = GetMemLpc(regpc);\
|
||||
cycles += 4;\
|
||||
break;\
|
||||
case 0x2:\
|
||||
pc=regpc+2;\
|
||||
var = regpc+FastMPCW();\
|
||||
break;\
|
||||
case 0x3:\
|
||||
pc=regpc+2;\
|
||||
mod = FastMPCW32();\
|
||||
var = regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12));\
|
||||
cycles += 2;\
|
||||
break;\
|
||||
default:\
|
||||
ExceptionGroup1(ILLINSTR);\
|
||||
var = 0;\
|
||||
break;\
|
||||
}}
|
||||
|
||||
/*
|
||||
* Condition-Code queries
|
||||
*/
|
||||
#define CCt 0xff
|
||||
#define CCf 0x00
|
||||
#define CChi (!GetC() && !GetZ())
|
||||
#define CCls (GetC() || GetZ())
|
||||
#define CCcc !GetC()
|
||||
#define CCcs GetC()
|
||||
#define CCne !GetZ()
|
||||
#define CCeq GetZ()
|
||||
#define CCvc !GetV()
|
||||
#define CCvs GetV()
|
||||
#define CCpl !GetN()
|
||||
#define CCmi GetN()
|
||||
#define CCge !(GetN() ^ GetV())
|
||||
#define CClt (GetN() ^ GetV())
|
||||
#define CCgt (!(GetN() ^ GetV()) && !GetZ())
|
||||
#define CCle ((GetN() ^ GetV()) || GetZ())
|
||||
|
||||
/*
|
||||
* Oper arguments:
|
||||
* Code Opcode
|
||||
* Op(target,source) Macro used to execute operation
|
||||
* DeclS(name) Macro to declare source (such as DB, DW or DL, or
|
||||
DN=no source, DA=address, DR=register number)
|
||||
* GetS(var,spec) Macro to fetch source, with addressing mode evaluation.
|
||||
SNN = no fetch
|
||||
SNQ = used in MOVEQ
|
||||
ScB = condition code register
|
||||
ScW = status register word (s-flag not checked)
|
||||
Ss = source equals source specifier (spec1)
|
||||
SaW, SaL = get #<spec1> data register value
|
||||
SdB, SdW, SdL = get data register value
|
||||
SainB, SainW, SainL = (A<spec>)
|
||||
SainA = (LEA only)
|
||||
SaixB, SaixW, SaixL = (d8,A<spec>,X<>)
|
||||
SaixA = (LEA only)
|
||||
SdaiB, SdaiW, SdaiL = d16(A<spec>)
|
||||
SdaiA = (LEA only)
|
||||
SaipB, SaipW, SaipL = (A<spec>)+
|
||||
SmaiB, SmaiW, SmaiL = -(A<spec>)
|
||||
SimmB, SimmW, SimmL = immediate
|
||||
SdaiPW, SdaiPL = used in MOVEP
|
||||
SearB, SearW, SearL = other addressing modes
|
||||
SearA = (LEA only)
|
||||
* spec1 source specifier, usually the data or address register number.
|
||||
* DeclT(name) Macro to declare target (such as DB, DW or DL, or
|
||||
DN=no target, DA=address, DR=register number)
|
||||
* DeclEA2(name) Macro to declare target address (typically DA, DR, or DN)
|
||||
* CalcEA2(address,spec) Macro to calculate address, with addressing mode evaluation.
|
||||
CN = no address
|
||||
Cs = equals target specifier (spec2)
|
||||
Cd = equals target specifier (spec2) (data register number)
|
||||
Ca = equals target specifier (spec2) + 8 (address register number)
|
||||
Cain = (A<spec>)
|
||||
Caix = (d8,A<spec>,X<>)
|
||||
Cdai = d16(A<spec>)
|
||||
CaipB, CaipW, CaipL = (A<spec>)+,
|
||||
CaipB15 = stack pointer only
|
||||
CmaiB, CmaiW, CmaiL = -(A<spec>)
|
||||
CmaiB15 = stack pointer only
|
||||
Ceaw = other addressing modes (if target is modified)
|
||||
Cear = other addressing modes (if target is not modified)
|
||||
* spec2 target specifier, usually the data or address register number.
|
||||
* GetEA2(address,name) Macro to get target value
|
||||
GCB = get condition code
|
||||
GCW = get status (s-flag not checked)
|
||||
GN = no read
|
||||
GMB, GMW, GML = read from memory
|
||||
GPW, GPL = (MOVEP)
|
||||
GRB, GRW, GRL = read from register
|
||||
* SetEA2(address,name) Macro to set target value
|
||||
SCB = set condition code
|
||||
SCW = set status (s-flag not checked)
|
||||
SN = no write
|
||||
SMB, SMW, SML = write to memory
|
||||
SPW, SPL = (MOVEP)
|
||||
SRB, SRW, SRL = write to register
|
||||
*/
|
||||
|
||||
#if (!defined(DEBUG) || !defined(INTERNALTRACE))
|
||||
#define Oper(Code, Op, DeclS, GetS, spec1, DeclT, DeclEA2, CalcEA2, spec2, GetEA2, SetEA2, rval)\
|
||||
unsigned long Code(operin)\
|
||||
{\
|
||||
register unsigned long cycles=0;\
|
||||
DeclS (source)\
|
||||
DeclT (target)\
|
||||
DeclEA2 (address2)\
|
||||
GetS (source, spec1)\
|
||||
CalcEA2 (address2, spec2)\
|
||||
GetEA2 (address2, target)\
|
||||
Op (target, source)\
|
||||
SetEA2 (address2, target)\
|
||||
return rval; \
|
||||
}
|
||||
#else
|
||||
/* quick'n dirty debug hack */
|
||||
#undef DN
|
||||
#define DN(name) int name;
|
||||
#define Oper(Code, Op, DeclS, GetS, spec1, DeclT, DeclEA2, CalcEA2, spec2, GetEA2, SetEA2, rval)\
|
||||
unsigned long Code(operin)\
|
||||
{\
|
||||
register unsigned long cycles=0;\
|
||||
DeclS (source)\
|
||||
DeclT (target)\
|
||||
DeclEA2 (address2)\
|
||||
source = 0; \
|
||||
target = 0; \
|
||||
address2 = 0; \
|
||||
GetS (source, spec1)\
|
||||
CalcEA2 (address2, spec2)\
|
||||
GetEA2 (address2, target)\
|
||||
traceback[tbi].address = address2; \
|
||||
traceback[tbi].source = source; \
|
||||
traceback[tbi].target = target; \
|
||||
Op (target, source)\
|
||||
traceback[tbi].result = target; \
|
||||
SetEA2 (address2, target)\
|
||||
return rval; \
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,809 @@
|
|||
/*
|
||||
* Castaway
|
||||
* (C) 1994 - 2002 Martin Doering, Joachim Hoenig
|
||||
*
|
||||
* $File$ - 68k add instructions
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*
|
||||
* revision history
|
||||
* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring
|
||||
* 10.07.2002 JH Fixed Z-Flag for ADDX
|
||||
* 08.10.2002 JH Fixed Z-Flag for ADD.B 0x80+0x80 and Add.W 0x8000+0x8000.
|
||||
*/
|
||||
#ifndef PROTOH
|
||||
static char sccsid[] = "$Id: op68kadd.c,v 1.3 2002/10/08 00:18:02 jhoenig Exp $";
|
||||
#include "68000.h"
|
||||
#include "op68k.h"
|
||||
|
||||
/*
|
||||
* Opfuncs.
|
||||
*/
|
||||
|
||||
#define DoAddB(target,source) \
|
||||
{register int32 tgt,cvnz=0;\
|
||||
tgt = target + source;\
|
||||
if ((uint32) source > (uint32) ~target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\
|
||||
target = tgt;\
|
||||
if (tgt!=target) cvnz+=Vflag;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
};
|
||||
|
||||
#define DoAddW(target,source) \
|
||||
{register int32 tgt,cvnz=0;\
|
||||
tgt = target + source;\
|
||||
if ((uint32) source > (uint32) ~target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\
|
||||
target = tgt;\
|
||||
if (tgt!=target) cvnz+=Vflag;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
};
|
||||
|
||||
#define DoAddL(target,source) \
|
||||
/* Overflow precondition: source has same sign */\
|
||||
{register int32 precon=(target>>31)-(source>>31),cvnz=0;\
|
||||
if ((uint32) source > (uint32) ~target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\
|
||||
target += source;\
|
||||
/* target and source now have different sign: overflow! */\
|
||||
if (precon==0 && (target>>31)!=(source>>31)) cvnz+=Vflag;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
};
|
||||
|
||||
#define DoAdda(target,source) target += source;
|
||||
|
||||
#define DoAddx(target,source) \
|
||||
/* Overflow precondition: source has same sign */\
|
||||
{register int32 precon=(target>>31)-(source>>31);\
|
||||
if (GetX ()) {\
|
||||
SetXC ((uint32) source >= (uint32) ~target);\
|
||||
target += source + 1;\
|
||||
} else {\
|
||||
SetXC ((uint32) source > (uint32) ~target);\
|
||||
target += source;\
|
||||
}\
|
||||
/* target and source now have different sign: overflow! */\
|
||||
SetV(precon==0 && (target>>31)!=(source>>31));\
|
||||
ZeroZ(target!=0);\
|
||||
SetN(target < 0);};
|
||||
|
||||
#endif
|
||||
|
||||
Oper (Opd000, DoAddB, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4)
|
||||
Oper (Opd010, DoAddB, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8)
|
||||
Oper (Opd018, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8)
|
||||
Oper (Opd020, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12)
|
||||
Oper (Opd028, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12)
|
||||
Oper (Opd030, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16)
|
||||
Oper (Opd038, DoAddB, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opd040, DoAddW, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4)
|
||||
Oper (Opd048, DoAddW, DW, SaW, ins7, DW, DR, Cd, 0, GRW, SRW, 4)
|
||||
Oper (Opd050, DoAddW, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8)
|
||||
Oper (Opd058, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8)
|
||||
Oper (Opd060, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12)
|
||||
Oper (Opd068, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12)
|
||||
Oper (Opd070, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16)
|
||||
Oper (Opd078, DoAddW, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opd080, DoAddL, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8)
|
||||
Oper (Opd088, DoAddL, DL, SaL, ins7, DL, DR, Cd, 0, GRL, SRL, 8)
|
||||
Oper (Opd090, DoAddL, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Opd098, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Opd0a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Opd0a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20)
|
||||
Oper (Opd0b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20)
|
||||
Oper (Opd0b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd0c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 0, GRL, SRL, 8)
|
||||
Oper (Opd0c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 0, GRL, SRL, 8)
|
||||
Oper (Opd0d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 0, GRL, SRL, 12)
|
||||
Oper (Opd0d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 0, GRL, SRL, 12)
|
||||
Oper (Opd0e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16)
|
||||
Oper (Opd0e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16)
|
||||
Oper (Opd0f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 0, GRL, SRL, 20)
|
||||
Oper (Opd0f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Opd100, DoAddx, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4)
|
||||
Oper (Opd108, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20)
|
||||
Oper (Opd110, DoAddB, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opd118, DoAddB, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opd120, DoAddB, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opd128, DoAddB, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opd130, DoAddB, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Opd138, DoAddB, DB, SdB, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd140, DoAddx, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4)
|
||||
Oper (Opd148, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 0, GMW, SMW, 20)
|
||||
Oper (Opd150, DoAddW, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opd158, DoAddW, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opd160, DoAddW, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opd168, DoAddW, DW, SdW, 0, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opd170, DoAddW, DW, SdW, 0, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Opd178, DoAddW, DW, SdW, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd180, DoAddx, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8)
|
||||
Oper (Opd188, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 0, GML, SML, 32)
|
||||
Oper (Opd190, DoAddL, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opd198, DoAddL, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opd1a0, DoAddL, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opd1a8, DoAddL, DL, SdL, 0, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Opd1b0, DoAddL, DL, SdL, 0, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Opd1b8, DoAddL, DL, SdL, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Opd1c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 0, GRL, SRL, 8)
|
||||
Oper (Opd1c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 0, GRL, SRL, 8)
|
||||
Oper (Opd1d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 0, GRL, SRL, 16)
|
||||
Oper (Opd1d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 0, GRL, SRL, 16)
|
||||
Oper (Opd1e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 16)
|
||||
Oper (Opd1e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 20)
|
||||
Oper (Opd1f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 0, GRL, SRL, 20)
|
||||
Oper (Opd1f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opd200, DoAddB, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4)
|
||||
Oper (Opd210, DoAddB, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8)
|
||||
Oper (Opd218, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8)
|
||||
Oper (Opd220, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12)
|
||||
Oper (Opd228, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12)
|
||||
Oper (Opd230, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16)
|
||||
Oper (Opd238, DoAddB, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opd240, DoAddW, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4)
|
||||
Oper (Opd248, DoAddW, DW, SaW, ins7, DW, DR, Cd, 1, GRW, SRW, 4)
|
||||
Oper (Opd250, DoAddW, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8)
|
||||
Oper (Opd258, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8)
|
||||
Oper (Opd260, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12)
|
||||
Oper (Opd268, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12)
|
||||
Oper (Opd270, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16)
|
||||
Oper (Opd278, DoAddW, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opd280, DoAddL, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8)
|
||||
Oper (Opd288, DoAddL, DL, SaL, ins7, DL, DR, Cd, 1, GRL, SRL, 8)
|
||||
Oper (Opd290, DoAddL, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Opd298, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Opd2a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Opd2a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20)
|
||||
Oper (Opd2b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20)
|
||||
Oper (Opd2b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd2c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 1, GRL, SRL, 8)
|
||||
Oper (Opd2c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 1, GRL, SRL, 8)
|
||||
Oper (Opd2d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 1, GRL, SRL, 12)
|
||||
Oper (Opd2d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 1, GRL, SRL, 12)
|
||||
Oper (Opd2e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16)
|
||||
Oper (Opd2e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16)
|
||||
Oper (Opd2f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 1, GRL, SRL, 20)
|
||||
Oper (Opd2f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Opd300, DoAddx, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4)
|
||||
Oper (Opd308, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20)
|
||||
Oper (Opd310, DoAddB, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opd318, DoAddB, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opd320, DoAddB, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opd328, DoAddB, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opd330, DoAddB, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Opd338, DoAddB, DB, SdB, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd340, DoAddx, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4)
|
||||
Oper (Opd348, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 1, GMW, SMW, 20)
|
||||
Oper (Opd350, DoAddW, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opd358, DoAddW, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opd360, DoAddW, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opd368, DoAddW, DW, SdW, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opd370, DoAddW, DW, SdW, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Opd378, DoAddW, DW, SdW, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd380, DoAddx, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8)
|
||||
Oper (Opd388, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 1, GML, SML, 32)
|
||||
Oper (Opd390, DoAddL, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opd398, DoAddL, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opd3a0, DoAddL, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opd3a8, DoAddL, DL, SdL, 1, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Opd3b0, DoAddL, DL, SdL, 1, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Opd3b8, DoAddL, DL, SdL, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Opd3c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 1, GRL, SRL, 8)
|
||||
Oper (Opd3c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 1, GRL, SRL, 8)
|
||||
Oper (Opd3d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 1, GRL, SRL, 16)
|
||||
Oper (Opd3d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 1, GRL, SRL, 16)
|
||||
Oper (Opd3e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 16)
|
||||
Oper (Opd3e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 20)
|
||||
Oper (Opd3f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 1, GRL, SRL, 20)
|
||||
Oper (Opd3f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opd400, DoAddB, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4)
|
||||
Oper (Opd410, DoAddB, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8)
|
||||
Oper (Opd418, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8)
|
||||
Oper (Opd420, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12)
|
||||
Oper (Opd428, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12)
|
||||
Oper (Opd430, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16)
|
||||
Oper (Opd438, DoAddB, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opd440, DoAddW, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4)
|
||||
Oper (Opd448, DoAddW, DW, SaW, ins7, DW, DR, Cd, 2, GRW, SRW, 4)
|
||||
Oper (Opd450, DoAddW, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8)
|
||||
Oper (Opd458, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8)
|
||||
Oper (Opd460, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12)
|
||||
Oper (Opd468, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12)
|
||||
Oper (Opd470, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16)
|
||||
Oper (Opd478, DoAddW, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opd480, DoAddL, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8)
|
||||
Oper (Opd488, DoAddL, DL, SaL, ins7, DL, DR, Cd, 2, GRL, SRL, 8)
|
||||
Oper (Opd490, DoAddL, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Opd498, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Opd4a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Opd4a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20)
|
||||
Oper (Opd4b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20)
|
||||
Oper (Opd4b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd4c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 2, GRL, SRL, 8)
|
||||
Oper (Opd4c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 2, GRL, SRL, 8)
|
||||
Oper (Opd4d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 2, GRL, SRL, 12)
|
||||
Oper (Opd4d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 2, GRL, SRL, 12)
|
||||
Oper (Opd4e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16)
|
||||
Oper (Opd4e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16)
|
||||
Oper (Opd4f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 2, GRL, SRL, 20)
|
||||
Oper (Opd4f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Opd500, DoAddx, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4)
|
||||
Oper (Opd508, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20)
|
||||
Oper (Opd510, DoAddB, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opd518, DoAddB, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opd520, DoAddB, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opd528, DoAddB, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opd530, DoAddB, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Opd538, DoAddB, DB, SdB, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd540, DoAddx, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4)
|
||||
Oper (Opd548, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 2, GMW, SMW, 20)
|
||||
Oper (Opd550, DoAddW, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opd558, DoAddW, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opd560, DoAddW, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opd568, DoAddW, DW, SdW, 2, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opd570, DoAddW, DW, SdW, 2, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Opd578, DoAddW, DW, SdW, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd580, DoAddx, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8)
|
||||
Oper (Opd588, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 2, GML, SML, 32)
|
||||
Oper (Opd590, DoAddL, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opd598, DoAddL, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opd5a0, DoAddL, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opd5a8, DoAddL, DL, SdL, 2, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Opd5b0, DoAddL, DL, SdL, 2, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Opd5b8, DoAddL, DL, SdL, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Opd5c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 2, GRL, SRL, 8)
|
||||
Oper (Opd5c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 2, GRL, SRL, 8)
|
||||
Oper (Opd5d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 2, GRL, SRL, 16)
|
||||
Oper (Opd5d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 2, GRL, SRL, 16)
|
||||
Oper (Opd5e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 16)
|
||||
Oper (Opd5e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 20)
|
||||
Oper (Opd5f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 2, GRL, SRL, 20)
|
||||
Oper (Opd5f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opd600, DoAddB, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4)
|
||||
Oper (Opd610, DoAddB, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8)
|
||||
Oper (Opd618, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8)
|
||||
Oper (Opd620, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12)
|
||||
Oper (Opd628, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12)
|
||||
Oper (Opd630, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16)
|
||||
Oper (Opd638, DoAddB, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opd640, DoAddW, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4)
|
||||
Oper (Opd648, DoAddW, DW, SaW, ins7, DW, DR, Cd, 3, GRW, SRW, 4)
|
||||
Oper (Opd650, DoAddW, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8)
|
||||
Oper (Opd658, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8)
|
||||
Oper (Opd660, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12)
|
||||
Oper (Opd668, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12)
|
||||
Oper (Opd670, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16)
|
||||
Oper (Opd678, DoAddW, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opd680, DoAddL, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8)
|
||||
Oper (Opd688, DoAddL, DL, SaL, ins7, DL, DR, Cd, 3, GRL, SRL, 8)
|
||||
Oper (Opd690, DoAddL, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Opd698, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Opd6a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Opd6a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20)
|
||||
Oper (Opd6b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20)
|
||||
Oper (Opd6b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd6c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 3, GRL, SRL, 8)
|
||||
Oper (Opd6c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 3, GRL, SRL, 8)
|
||||
Oper (Opd6d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 3, GRL, SRL, 12)
|
||||
Oper (Opd6d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 3, GRL, SRL, 12)
|
||||
Oper (Opd6e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16)
|
||||
Oper (Opd6e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16)
|
||||
Oper (Opd6f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 3, GRL, SRL, 20)
|
||||
Oper (Opd6f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Opd700, DoAddx, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4)
|
||||
Oper (Opd708, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20)
|
||||
Oper (Opd710, DoAddB, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opd718, DoAddB, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opd720, DoAddB, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opd728, DoAddB, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opd730, DoAddB, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Opd738, DoAddB, DB, SdB, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd740, DoAddx, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4)
|
||||
Oper (Opd748, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 3, GMW, SMW, 20)
|
||||
Oper (Opd750, DoAddW, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opd758, DoAddW, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opd760, DoAddW, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opd768, DoAddW, DW, SdW, 3, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opd770, DoAddW, DW, SdW, 3, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Opd778, DoAddW, DW, SdW, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd780, DoAddx, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8)
|
||||
Oper (Opd788, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 3, GML, SML, 32)
|
||||
Oper (Opd790, DoAddL, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opd798, DoAddL, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opd7a0, DoAddL, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opd7a8, DoAddL, DL, SdL, 3, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Opd7b0, DoAddL, DL, SdL, 3, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Opd7b8, DoAddL, DL, SdL, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Opd7c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 3, GRL, SRL, 8)
|
||||
Oper (Opd7c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 3, GRL, SRL, 8)
|
||||
Oper (Opd7d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 3, GRL, SRL, 16)
|
||||
Oper (Opd7d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 3, GRL, SRL, 16)
|
||||
Oper (Opd7e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 16)
|
||||
Oper (Opd7e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 20)
|
||||
Oper (Opd7f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 3, GRL, SRL, 20)
|
||||
Oper (Opd7f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opd800, DoAddB, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4)
|
||||
Oper (Opd810, DoAddB, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8)
|
||||
Oper (Opd818, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8)
|
||||
Oper (Opd820, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12)
|
||||
Oper (Opd828, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12)
|
||||
Oper (Opd830, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16)
|
||||
Oper (Opd838, DoAddB, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opd840, DoAddW, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4)
|
||||
Oper (Opd848, DoAddW, DW, SaW, ins7, DW, DR, Cd, 4, GRW, SRW, 4)
|
||||
Oper (Opd850, DoAddW, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8)
|
||||
Oper (Opd858, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8)
|
||||
Oper (Opd860, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12)
|
||||
Oper (Opd868, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12)
|
||||
Oper (Opd870, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16)
|
||||
Oper (Opd878, DoAddW, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opd880, DoAddL, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8)
|
||||
Oper (Opd888, DoAddL, DL, SaL, ins7, DL, DR, Cd, 4, GRL, SRL, 8)
|
||||
Oper (Opd890, DoAddL, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Opd898, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Opd8a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Opd8a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20)
|
||||
Oper (Opd8b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20)
|
||||
Oper (Opd8b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd8c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 4, GRL, SRL, 8)
|
||||
Oper (Opd8c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 4, GRL, SRL, 8)
|
||||
Oper (Opd8d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 4, GRL, SRL, 12)
|
||||
Oper (Opd8d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 4, GRL, SRL, 12)
|
||||
Oper (Opd8e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16)
|
||||
Oper (Opd8e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16)
|
||||
Oper (Opd8f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 4, GRL, SRL, 20)
|
||||
Oper (Opd8f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Opd900, DoAddx, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4)
|
||||
Oper (Opd908, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20)
|
||||
Oper (Opd910, DoAddB, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opd918, DoAddB, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opd920, DoAddB, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opd928, DoAddB, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opd930, DoAddB, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Opd938, DoAddB, DB, SdB, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd940, DoAddx, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4)
|
||||
Oper (Opd948, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 4, GMW, SMW, 20)
|
||||
Oper (Opd950, DoAddW, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opd958, DoAddW, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opd960, DoAddW, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opd968, DoAddW, DW, SdW, 4, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opd970, DoAddW, DW, SdW, 4, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Opd978, DoAddW, DW, SdW, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opd980, DoAddx, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8)
|
||||
Oper (Opd988, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 4, GML, SML, 32)
|
||||
Oper (Opd990, DoAddL, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opd998, DoAddL, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opd9a0, DoAddL, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opd9a8, DoAddL, DL, SdL, 4, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Opd9b0, DoAddL, DL, SdL, 4, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Opd9b8, DoAddL, DL, SdL, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Opd9c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 4, GRL, SRL, 8)
|
||||
Oper (Opd9c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 4, GRL, SRL, 8)
|
||||
Oper (Opd9d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 4, GRL, SRL, 16)
|
||||
Oper (Opd9d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 4, GRL, SRL, 16)
|
||||
Oper (Opd9e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 16)
|
||||
Oper (Opd9e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 20)
|
||||
Oper (Opd9f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 4, GRL, SRL, 20)
|
||||
Oper (Opd9f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opda00, DoAddB, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4)
|
||||
Oper (Opda10, DoAddB, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8)
|
||||
Oper (Opda18, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8)
|
||||
Oper (Opda20, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12)
|
||||
Oper (Opda28, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12)
|
||||
Oper (Opda30, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16)
|
||||
Oper (Opda38, DoAddB, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opda40, DoAddW, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4)
|
||||
Oper (Opda48, DoAddW, DW, SaW, ins7, DW, DR, Cd, 5, GRW, SRW, 4)
|
||||
Oper (Opda50, DoAddW, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8)
|
||||
Oper (Opda58, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8)
|
||||
Oper (Opda60, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12)
|
||||
Oper (Opda68, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12)
|
||||
Oper (Opda70, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16)
|
||||
Oper (Opda78, DoAddW, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opda80, DoAddL, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8)
|
||||
Oper (Opda88, DoAddL, DL, SaL, ins7, DL, DR, Cd, 5, GRL, SRL, 8)
|
||||
Oper (Opda90, DoAddL, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Opda98, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Opdaa0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Opdaa8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20)
|
||||
Oper (Opdab0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20)
|
||||
Oper (Opdab8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Opdac0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 5, GRL, SRL, 8)
|
||||
Oper (Opdac8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 5, GRL, SRL, 8)
|
||||
Oper (Opdad0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 5, GRL, SRL, 12)
|
||||
Oper (Opdad8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 5, GRL, SRL, 12)
|
||||
Oper (Opdae0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16)
|
||||
Oper (Opdae8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16)
|
||||
Oper (Opdaf0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 5, GRL, SRL, 20)
|
||||
Oper (Opdaf8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Opdb00, DoAddx, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4)
|
||||
Oper (Opdb08, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20)
|
||||
Oper (Opdb10, DoAddB, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opdb18, DoAddB, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opdb20, DoAddB, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opdb28, DoAddB, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opdb30, DoAddB, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Opdb38, DoAddB, DB, SdB, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opdb40, DoAddx, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4)
|
||||
Oper (Opdb48, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 5, GMW, SMW, 20)
|
||||
Oper (Opdb50, DoAddW, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opdb58, DoAddW, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opdb60, DoAddW, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opdb68, DoAddW, DW, SdW, 5, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opdb70, DoAddW, DW, SdW, 5, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Opdb78, DoAddW, DW, SdW, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opdb80, DoAddx, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8)
|
||||
Oper (Opdb88, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 5, GML, SML, 32)
|
||||
Oper (Opdb90, DoAddL, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opdb98, DoAddL, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opdba0, DoAddL, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opdba8, DoAddL, DL, SdL, 5, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Opdbb0, DoAddL, DL, SdL, 5, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Opdbb8, DoAddL, DL, SdL, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Opdbc0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 5, GRL, SRL, 8)
|
||||
Oper (Opdbc8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 5, GRL, SRL, 8)
|
||||
Oper (Opdbd0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 5, GRL, SRL, 16)
|
||||
Oper (Opdbd8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 5, GRL, SRL, 16)
|
||||
Oper (Opdbe0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 16)
|
||||
Oper (Opdbe8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 20)
|
||||
Oper (Opdbf0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 5, GRL, SRL, 20)
|
||||
Oper (Opdbf8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opdc00, DoAddB, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4)
|
||||
Oper (Opdc10, DoAddB, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8)
|
||||
Oper (Opdc18, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8)
|
||||
Oper (Opdc20, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12)
|
||||
Oper (Opdc28, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12)
|
||||
Oper (Opdc30, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16)
|
||||
Oper (Opdc38, DoAddB, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opdc40, DoAddW, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4)
|
||||
Oper (Opdc48, DoAddW, DW, SaW, ins7, DW, DR, Cd, 6, GRW, SRW, 4)
|
||||
Oper (Opdc50, DoAddW, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8)
|
||||
Oper (Opdc58, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8)
|
||||
Oper (Opdc60, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12)
|
||||
Oper (Opdc68, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12)
|
||||
Oper (Opdc70, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16)
|
||||
Oper (Opdc78, DoAddW, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opdc80, DoAddL, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8)
|
||||
Oper (Opdc88, DoAddL, DL, SaL, ins7, DL, DR, Cd, 6, GRL, SRL, 8)
|
||||
Oper (Opdc90, DoAddL, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Opdc98, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Opdca0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Opdca8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20)
|
||||
Oper (Opdcb0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20)
|
||||
Oper (Opdcb8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Opdcc0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 6, GRL, SRL, 8)
|
||||
Oper (Opdcc8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 6, GRL, SRL, 8)
|
||||
Oper (Opdcd0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 6, GRL, SRL, 12)
|
||||
Oper (Opdcd8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 6, GRL, SRL, 12)
|
||||
Oper (Opdce0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16)
|
||||
Oper (Opdce8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16)
|
||||
Oper (Opdcf0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 6, GRL, SRL, 20)
|
||||
Oper (Opdcf8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Opdd00, DoAddx, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4)
|
||||
Oper (Opdd08, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20)
|
||||
Oper (Opdd10, DoAddB, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opdd18, DoAddB, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opdd20, DoAddB, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opdd28, DoAddB, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opdd30, DoAddB, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Opdd38, DoAddB, DB, SdB, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opdd40, DoAddx, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4)
|
||||
Oper (Opdd48, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 6, GMW, SMW, 20)
|
||||
Oper (Opdd50, DoAddW, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opdd58, DoAddW, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opdd60, DoAddW, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opdd68, DoAddW, DW, SdW, 6, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opdd70, DoAddW, DW, SdW, 6, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Opdd78, DoAddW, DW, SdW, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opdd80, DoAddx, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8)
|
||||
Oper (Opdd88, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 6, GML, SML, 32)
|
||||
Oper (Opdd90, DoAddL, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opdd98, DoAddL, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opdda0, DoAddL, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opdda8, DoAddL, DL, SdL, 6, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Opddb0, DoAddL, DL, SdL, 6, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Opddb8, DoAddL, DL, SdL, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Opddc0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 6, GRL, SRL, 8)
|
||||
Oper (Opddc8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 6, GRL, SRL, 8)
|
||||
Oper (Opddd0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 6, GRL, SRL, 16)
|
||||
Oper (Opddd8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 6, GRL, SRL, 16)
|
||||
Oper (Opdde0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 16)
|
||||
Oper (Opdde8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 20)
|
||||
Oper (Opddf0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 6, GRL, SRL, 20)
|
||||
Oper (Opddf8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opde00, DoAddB, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4)
|
||||
Oper (Opde10, DoAddB, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8)
|
||||
Oper (Opde18, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8)
|
||||
Oper (Opde20, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12)
|
||||
Oper (Opde28, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12)
|
||||
Oper (Opde30, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16)
|
||||
Oper (Opde38, DoAddB, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opde40, DoAddW, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4)
|
||||
Oper (Opde48, DoAddW, DW, SaW, ins7, DW, DR, Cd, 7, GRW, SRW, 4)
|
||||
Oper (Opde50, DoAddW, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8)
|
||||
Oper (Opde58, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8)
|
||||
Oper (Opde60, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12)
|
||||
Oper (Opde68, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12)
|
||||
Oper (Opde70, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16)
|
||||
Oper (Opde78, DoAddW, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opde80, DoAddL, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8)
|
||||
Oper (Opde88, DoAddL, DL, SaL, ins7, DL, DR, Cd, 7, GRL, SRL, 8)
|
||||
Oper (Opde90, DoAddL, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Opde98, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Opdea0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Opdea8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20)
|
||||
Oper (Opdeb0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20)
|
||||
Oper (Opdeb8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Opdec0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 7, GRL, SRL, 8)
|
||||
Oper (Opdec8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 7, GRL, SRL, 8)
|
||||
Oper (Opded0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 7, GRL, SRL, 12)
|
||||
Oper (Opded8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 7, GRL, SRL, 12)
|
||||
Oper (Opdee0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16)
|
||||
Oper (Opdee8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16)
|
||||
Oper (Opdef0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 7, GRL, SRL, 20)
|
||||
Oper (Opdef8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Opdf00, DoAddx, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4)
|
||||
Oper (Opdf08, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB15, 7, GMB, SMB, 20)
|
||||
Oper (Opdf10, DoAddB, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opdf18, DoAddB, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opdf20, DoAddB, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opdf28, DoAddB, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opdf30, DoAddB, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Opdf38, DoAddB, DB, SdB, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opdf40, DoAddx, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4)
|
||||
Oper (Opdf48, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 7, GMW, SMW, 20)
|
||||
Oper (Opdf50, DoAddW, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opdf58, DoAddW, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opdf60, DoAddW, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opdf68, DoAddW, DW, SdW, 7, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opdf70, DoAddW, DW, SdW, 7, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Opdf78, DoAddW, DW, SdW, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opdf80, DoAddx, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8)
|
||||
Oper (Opdf88, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 7, GML, SML, 32)
|
||||
Oper (Opdf90, DoAddL, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opdf98, DoAddL, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opdfa0, DoAddL, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opdfa8, DoAddL, DL, SdL, 7, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Opdfb0, DoAddL, DL, SdL, 7, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Opdfb8, DoAddL, DL, SdL, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Opdfc0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 7, GRL, SRL, 8)
|
||||
Oper (Opdfc8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 7, GRL, SRL, 8)
|
||||
Oper (Opdfd0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 7, GRL, SRL, 16)
|
||||
Oper (Opdfd8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 7, GRL, SRL, 16)
|
||||
Oper (Opdfe0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 16)
|
||||
Oper (Opdfe8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 20)
|
||||
Oper (Opdff0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 7, GRL, SRL, 20)
|
||||
Oper (Opdff8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op0600, DoAddB, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8)
|
||||
Oper (Op0610, DoAddB, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16)
|
||||
Oper (Op0618, DoAddB, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16)
|
||||
Oper (Op0620, DoAddB, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20)
|
||||
Oper (Op0628, DoAddB, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20)
|
||||
Oper (Op0630, DoAddB, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24)
|
||||
Oper (Op0638, DoAddB, DB, SimmB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+23)&0xfffffffc)
|
||||
Oper (Op0640, DoAddW, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8)
|
||||
Oper (Op0650, DoAddW, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16)
|
||||
Oper (Op0658, DoAddW, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16)
|
||||
Oper (Op0660, DoAddW, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20)
|
||||
Oper (Op0668, DoAddW, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20)
|
||||
Oper (Op0670, DoAddW, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24)
|
||||
Oper (Op0678, DoAddW, DW, SimmW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+23)&0xfffffffc)
|
||||
Oper (Op0680, DoAddL, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16)
|
||||
Oper (Op0690, DoAddL, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28)
|
||||
Oper (Op0698, DoAddL, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28)
|
||||
Oper (Op06a0, DoAddL, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32)
|
||||
Oper (Op06a8, DoAddL, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32)
|
||||
Oper (Op06b0, DoAddL, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36)
|
||||
Oper (Op06b8, DoAddL, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc)
|
||||
|
||||
Oper (Op5000, DoAddB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5010, DoAddB, DB, Ss, 8, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5018, DoAddB, DB, Ss, 8, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5020, DoAddB, DB, Ss, 8, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5028, DoAddB, DB, Ss, 8, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5030, DoAddB, DB, Ss, 8, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5038, DoAddB, DB, Ss, 8, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5040, DoAddW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5048, DoAdda, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5050, DoAddW, DW, Ss, 8, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5058, DoAddW, DW, Ss, 8, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5060, DoAddW, DW, Ss, 8, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5068, DoAddW, DW, Ss, 8, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5070, DoAddW, DW, Ss, 8, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5078, DoAddW, DW, Ss, 8, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5080, DoAddL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5088, DoAdda, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5090, DoAddL, DL, Ss, 8, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5098, DoAddL, DL, Ss, 8, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op50a0, DoAddL, DL, Ss, 8, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op50a8, DoAddL, DL, Ss, 8, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op50b0, DoAddL, DL, Ss, 8, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op50b8, DoAddL, DL, Ss, 8, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5200, DoAddB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5210, DoAddB, DB, Ss, 1, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5218, DoAddB, DB, Ss, 1, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5220, DoAddB, DB, Ss, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5228, DoAddB, DB, Ss, 1, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5230, DoAddB, DB, Ss, 1, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5238, DoAddB, DB, Ss, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5240, DoAddW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5248, DoAdda, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5250, DoAddW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5258, DoAddW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5260, DoAddW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5268, DoAddW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5270, DoAddW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5278, DoAddW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5280, DoAddL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5288, DoAdda, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5290, DoAddL, DL, Ss, 1, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5298, DoAddL, DL, Ss, 1, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op52a0, DoAddL, DL, Ss, 1, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op52a8, DoAddL, DL, Ss, 1, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op52b0, DoAddL, DL, Ss, 1, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op52b8, DoAddL, DL, Ss, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5400, DoAddB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5410, DoAddB, DB, Ss, 2, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5418, DoAddB, DB, Ss, 2, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5420, DoAddB, DB, Ss, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5428, DoAddB, DB, Ss, 2, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5430, DoAddB, DB, Ss, 2, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5438, DoAddB, DB, Ss, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5440, DoAddW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5448, DoAdda, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5450, DoAddW, DW, Ss, 2, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5458, DoAddW, DW, Ss, 2, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5460, DoAddW, DW, Ss, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5468, DoAddW, DW, Ss, 2, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5470, DoAddW, DW, Ss, 2, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5478, DoAddW, DW, Ss, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5480, DoAddL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5488, DoAdda, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5490, DoAddL, DL, Ss, 2, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5498, DoAddL, DL, Ss, 2, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op54a0, DoAddL, DL, Ss, 2, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op54a8, DoAddL, DL, Ss, 2, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op54b0, DoAddL, DL, Ss, 2, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op54b8, DoAddL, DL, Ss, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5600, DoAddB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5610, DoAddB, DB, Ss, 3, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5618, DoAddB, DB, Ss, 3, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5620, DoAddB, DB, Ss, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5628, DoAddB, DB, Ss, 3, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5630, DoAddB, DB, Ss, 3, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5638, DoAddB, DB, Ss, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5640, DoAddW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5648, DoAdda, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5650, DoAddW, DW, Ss, 3, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5658, DoAddW, DW, Ss, 3, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5660, DoAddW, DW, Ss, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5668, DoAddW, DW, Ss, 3, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5670, DoAddW, DW, Ss, 3, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5678, DoAddW, DW, Ss, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5680, DoAddL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5688, DoAdda, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5690, DoAddL, DL, Ss, 3, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5698, DoAddL, DL, Ss, 3, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op56a0, DoAddL, DL, Ss, 3, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op56a8, DoAddL, DL, Ss, 3, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op56b0, DoAddL, DL, Ss, 3, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op56b8, DoAddL, DL, Ss, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5800, DoAddB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5810, DoAddB, DB, Ss, 4, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5818, DoAddB, DB, Ss, 4, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5820, DoAddB, DB, Ss, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5828, DoAddB, DB, Ss, 4, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5830, DoAddB, DB, Ss, 4, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5838, DoAddB, DB, Ss, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5840, DoAddW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5848, DoAdda, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5850, DoAddW, DW, Ss, 4, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5858, DoAddW, DW, Ss, 4, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5860, DoAddW, DW, Ss, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5868, DoAddW, DW, Ss, 4, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5870, DoAddW, DW, Ss, 4, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5878, DoAddW, DW, Ss, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5880, DoAddL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5888, DoAdda, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5890, DoAddL, DL, Ss, 4, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5898, DoAddL, DL, Ss, 4, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op58a0, DoAddL, DL, Ss, 4, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op58a8, DoAddL, DL, Ss, 4, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op58b0, DoAddL, DL, Ss, 4, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op58b8, DoAddL, DL, Ss, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5a00, DoAddB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5a10, DoAddB, DB, Ss, 5, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5a18, DoAddB, DB, Ss, 5, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5a20, DoAddB, DB, Ss, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5a28, DoAddB, DB, Ss, 5, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5a30, DoAddB, DB, Ss, 5, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5a38, DoAddB, DB, Ss, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5a40, DoAddW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5a48, DoAdda, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5a50, DoAddW, DW, Ss, 5, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5a58, DoAddW, DW, Ss, 5, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5a60, DoAddW, DW, Ss, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5a68, DoAddW, DW, Ss, 5, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5a70, DoAddW, DW, Ss, 5, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5a78, DoAddW, DW, Ss, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5a80, DoAddL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5a88, DoAdda, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5a90, DoAddL, DL, Ss, 5, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5a98, DoAddL, DL, Ss, 5, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op5aa0, DoAddL, DL, Ss, 5, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op5aa8, DoAddL, DL, Ss, 5, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op5ab0, DoAddL, DL, Ss, 5, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op5ab8, DoAddL, DL, Ss, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5c00, DoAddB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5c10, DoAddB, DB, Ss, 6, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5c18, DoAddB, DB, Ss, 6, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5c20, DoAddB, DB, Ss, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5c28, DoAddB, DB, Ss, 6, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5c30, DoAddB, DB, Ss, 6, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5c38, DoAddB, DB, Ss, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5c40, DoAddW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5c48, DoAdda, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5c50, DoAddW, DW, Ss, 6, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5c58, DoAddW, DW, Ss, 6, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5c60, DoAddW, DW, Ss, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5c68, DoAddW, DW, Ss, 6, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5c70, DoAddW, DW, Ss, 6, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5c78, DoAddW, DW, Ss, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5c80, DoAddL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5c88, DoAdda, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5c90, DoAddL, DL, Ss, 6, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5c98, DoAddL, DL, Ss, 6, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op5ca0, DoAddL, DL, Ss, 6, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op5ca8, DoAddL, DL, Ss, 6, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op5cb0, DoAddL, DL, Ss, 6, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op5cb8, DoAddL, DL, Ss, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5e00, DoAddB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5e10, DoAddB, DB, Ss, 7, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5e18, DoAddB, DB, Ss, 7, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5e20, DoAddB, DB, Ss, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5e28, DoAddB, DB, Ss, 7, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5e30, DoAddB, DB, Ss, 7, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5e38, DoAddB, DB, Ss, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5e40, DoAddW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5e48, DoAdda, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5e50, DoAddW, DW, Ss, 7, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5e58, DoAddW, DW, Ss, 7, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5e60, DoAddW, DW, Ss, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5e68, DoAddW, DW, Ss, 7, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5e70, DoAddW, DW, Ss, 7, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5e78, DoAddW, DW, Ss, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5e80, DoAddL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5e88, DoAdda, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5e90, DoAddL, DL, Ss, 7, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5e98, DoAddL, DL, Ss, 7, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op5ea0, DoAddL, DL, Ss, 7, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op5ea8, DoAddL, DL, Ss, 7, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op5eb0, DoAddL, DL, Ss, 7, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op5eb8, DoAddL, DL, Ss, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
|
@ -0,0 +1,844 @@
|
|||
/*
|
||||
* Castaway
|
||||
* (C) 1994 - 2002 Martin Doering, Joachim Hoenig
|
||||
*
|
||||
* $File$ - 68k arithmetic instructions
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*
|
||||
* revision history
|
||||
* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring
|
||||
* 12.06.2002 JH Correct bus error/address error exception stack frame
|
||||
* 13.06.2002 JH Merged in Martin's BCD implementation (untested),
|
||||
* completed jump table. STOP is now the only
|
||||
* unimplemented instruction.
|
||||
* 08.10.2002 JH Fixed Z-Flag for ADD.B 0x80+0x80 and Add.W 0x8000+0x8000.
|
||||
*/
|
||||
#ifndef PROTOH
|
||||
static char sccsid[] = "$Id: op68karith.c,v 1.5 2002/10/08 00:18:02 jhoenig Exp $";
|
||||
#include "68000.h"
|
||||
#include "op68k.h"
|
||||
|
||||
#include<stdio.h>
|
||||
|
||||
/*
|
||||
* Opfuncs.
|
||||
*/
|
||||
|
||||
#define DoCmpB(target,source) \
|
||||
{register int32 tgt,cvnz=0; register int8 tgt8;\
|
||||
tgt = target - source;\
|
||||
if ((uint32) source > (uint32) target) cvnz+=Cflag;\
|
||||
tgt8=tgt;\
|
||||
if (tgt!=tgt8) cvnz+=Vflag;\
|
||||
if (tgt8==0) cvnz+=Zflag;\
|
||||
else if (tgt8<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
};
|
||||
|
||||
#define DoCmpW(target,source) \
|
||||
{register int32 tgt,cvnz=0; register int16 tgt16;\
|
||||
tgt = target - source;\
|
||||
if ((uint32) source > (uint32) target) cvnz+=Cflag;\
|
||||
tgt16=tgt;\
|
||||
if (tgt!=tgt16) cvnz+=Vflag;\
|
||||
if (tgt16==0) cvnz+=Zflag;\
|
||||
else if (tgt16<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
};
|
||||
|
||||
#define DoCmpL(target,source) \
|
||||
/* Overflow precondition: source has different sign */\
|
||||
{register int32 precon=(target>>31)-(source>>31),cvnz=0;\
|
||||
if ((uint32) source > (uint32) target) cvnz+=Cflag;\
|
||||
target -= source;\
|
||||
/* target and source now have same sign: overflow! */\
|
||||
if (precon && (target>>31)==(source>>31)) cvnz+=Vflag;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
};
|
||||
|
||||
#define DoCmpa(target,source) DoCmpL(target,source)
|
||||
#define DoCmpm(target,source) DoCmpL(target,source)
|
||||
|
||||
|
||||
#define DoDivs(target,source) \
|
||||
if (source == 0) {\
|
||||
ExceptionGroup2(DIVZ);\
|
||||
} else {\
|
||||
int16 quot, rest;\
|
||||
if ((target / source) > 32767 || (target / source) < -32768) {\
|
||||
ForceV (1);\
|
||||
ForceC (0);\
|
||||
} else {\
|
||||
rest = target % source;\
|
||||
quot = target / source;\
|
||||
target = (rest << 16) | (uint16) quot;\
|
||||
ClrCVSetNZ ((int16) target);\
|
||||
}\
|
||||
}
|
||||
|
||||
#define DoDivu(target,source) \
|
||||
if (source == 0) {\
|
||||
ExceptionGroup2(DIVZ);\
|
||||
} else {\
|
||||
uint16 quot, rest;\
|
||||
if (((uint32) target / (uint16) source) & 0xffff0000) {\
|
||||
ForceV (1);\
|
||||
ForceC (0);\
|
||||
} else {\
|
||||
rest = (uint32) target % (uint16) source;\
|
||||
quot = (uint32) target / (uint16) source;\
|
||||
target = (rest << 16) | quot;\
|
||||
ClrCVSetNZ ((int16) target);\
|
||||
}\
|
||||
}
|
||||
|
||||
#define DoMuls(target,source) \
|
||||
target = ((int16) target * source);\
|
||||
ClrCVSetNZ (target);
|
||||
|
||||
#define DoMulu(target,source) \
|
||||
target = ((uint16) target * (uint16) source);\
|
||||
ClrCVSetNZ (target);
|
||||
|
||||
//#define DoSuba(target,source) target -= source;
|
||||
|
||||
/*
|
||||
#define DoSubx(target,source) \
|
||||
// Overflow precondition: source has different sign \
|
||||
SetV ((target < 0) != (source < 0));\
|
||||
if (GetX ()) {\
|
||||
SetXC ((uint32) source >= (uint32) target);\
|
||||
target -= source;\
|
||||
target -= 1;\
|
||||
} else {\
|
||||
SetXC ((uint32) source > (uint32) target);\
|
||||
target -= source;\
|
||||
}\
|
||||
//target and source now have same sign: overflow!
|
||||
SetV (GetV() && (target<0) == (source<0));\
|
||||
SetNZ (target);
|
||||
*/
|
||||
|
||||
/* BCD all totally untested (MAD) */
|
||||
|
||||
#define DoNBCD(target, source) \
|
||||
{ register uint32 lo = (target & 0xF) + GetX();\
|
||||
register uint32 hi = (target & 0xF0);\
|
||||
if (lo>10) {lo=20-lo; hi+=0x20;}\
|
||||
else if (lo>0) {lo=10-lo; hi+=0x10;}\
|
||||
if (hi>0xa0) {hi=0x140-hi; ForceX(1); ForceC(1);}\
|
||||
else if (hi>0) {hi=0xa0-hi; ForceX(1); ForceC(1);}\
|
||||
else {ForceC(0); ForceX(0);}\
|
||||
target=hi+lo;\
|
||||
if (target!=0) ForceZ(0);\
|
||||
};
|
||||
|
||||
#define DoABCD(target, source) \
|
||||
{ register int32 tgt; \
|
||||
tgt = (source & 0xF) + (target & 0xF) + GetX(); \
|
||||
if(tgt >= 0xA) \
|
||||
tgt += 0x6; \
|
||||
tgt += (source & 0xF0) + (target & 0xF0); \
|
||||
if(tgt >= 0xA0) \
|
||||
tgt += 0x60; \
|
||||
SetXC (tgt & 0xFF00); \
|
||||
tgt &= 0xFF; \
|
||||
SetZ(tgt == 0); \
|
||||
target = tgt; \
|
||||
};
|
||||
|
||||
#define DoSBCD(target, source) \
|
||||
{ register int32 tgt, hi; \
|
||||
tgt = (target & 0xF) - (source & 0xF) - GetX(); \
|
||||
hi = (target & 0xF0) - (source & 0xF0); \
|
||||
if(tgt < 0) { \
|
||||
tgt += 10; \
|
||||
hi -= 0x10; \
|
||||
} \
|
||||
if(hi < 0) { \
|
||||
hi -= 0x60; \
|
||||
} \
|
||||
tgt += hi; \
|
||||
SetXC (tgt & 0xFF00); \
|
||||
tgt &= 0xFF; \
|
||||
SetZ(tgt == 0); \
|
||||
target = tgt; \
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
Oper (Opc0c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 72)
|
||||
Oper (Opc0d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 76)
|
||||
Oper (Opc0d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 76)
|
||||
Oper (Opc0e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 76)
|
||||
Oper (Opc0e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 80)
|
||||
Oper (Opc0f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 80)
|
||||
Oper (Opc0f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opc1c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 72)
|
||||
Oper (Opc1d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 76)
|
||||
Oper (Opc1d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 76)
|
||||
Oper (Opc1e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 76)
|
||||
Oper (Opc1e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 80)
|
||||
Oper (Opc1f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 80)
|
||||
Oper (Opc1f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opc2c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 72)
|
||||
Oper (Opc2d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 76)
|
||||
Oper (Opc2d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 76)
|
||||
Oper (Opc2e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 76)
|
||||
Oper (Opc2e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 80)
|
||||
Oper (Opc2f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 80)
|
||||
Oper (Opc2f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opc3c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 72)
|
||||
Oper (Opc3d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 76)
|
||||
Oper (Opc3d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 76)
|
||||
Oper (Opc3e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 76)
|
||||
Oper (Opc3e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 80)
|
||||
Oper (Opc3f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 80)
|
||||
Oper (Opc3f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opc4c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 72)
|
||||
Oper (Opc4d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 76)
|
||||
Oper (Opc4d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 76)
|
||||
Oper (Opc4e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 76)
|
||||
Oper (Opc4e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 80)
|
||||
Oper (Opc4f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 80)
|
||||
Oper (Opc4f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opc5c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 72)
|
||||
Oper (Opc5d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 76)
|
||||
Oper (Opc5d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 76)
|
||||
Oper (Opc5e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 76)
|
||||
Oper (Opc5e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 80)
|
||||
Oper (Opc5f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 80)
|
||||
Oper (Opc5f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opc6c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 72)
|
||||
Oper (Opc6d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 76)
|
||||
Oper (Opc6d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 76)
|
||||
Oper (Opc6e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 76)
|
||||
Oper (Opc6e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 80)
|
||||
Oper (Opc6f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 80)
|
||||
Oper (Opc6f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opc7c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 72)
|
||||
Oper (Opc7d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 76)
|
||||
Oper (Opc7d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 76)
|
||||
Oper (Opc7e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 76)
|
||||
Oper (Opc7e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 80)
|
||||
Oper (Opc7f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 80)
|
||||
Oper (Opc7f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opc8c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 72)
|
||||
Oper (Opc8d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 76)
|
||||
Oper (Opc8d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 76)
|
||||
Oper (Opc8e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 76)
|
||||
Oper (Opc8e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 80)
|
||||
Oper (Opc8f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 80)
|
||||
Oper (Opc8f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opc9c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 72)
|
||||
Oper (Opc9d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 76)
|
||||
Oper (Opc9d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 76)
|
||||
Oper (Opc9e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 76)
|
||||
Oper (Opc9e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 80)
|
||||
Oper (Opc9f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 80)
|
||||
Oper (Opc9f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opcac0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 72)
|
||||
Oper (Opcad0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 76)
|
||||
Oper (Opcad8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 76)
|
||||
Oper (Opcae0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 76)
|
||||
Oper (Opcae8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 80)
|
||||
Oper (Opcaf0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 80)
|
||||
Oper (Opcaf8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opcbc0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 72)
|
||||
Oper (Opcbd0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 76)
|
||||
Oper (Opcbd8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 76)
|
||||
Oper (Opcbe0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 76)
|
||||
Oper (Opcbe8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 80)
|
||||
Oper (Opcbf0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 80)
|
||||
Oper (Opcbf8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opccc0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 72)
|
||||
Oper (Opccd0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 76)
|
||||
Oper (Opccd8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 76)
|
||||
Oper (Opcce0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 76)
|
||||
Oper (Opcce8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 80)
|
||||
Oper (Opccf0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 80)
|
||||
Oper (Opccf8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opcdc0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 72)
|
||||
Oper (Opcdd0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 76)
|
||||
Oper (Opcdd8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 76)
|
||||
Oper (Opcde0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 76)
|
||||
Oper (Opcde8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 80)
|
||||
Oper (Opcdf0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 80)
|
||||
Oper (Opcdf8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opcec0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 72)
|
||||
Oper (Opced0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 76)
|
||||
Oper (Opced8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 76)
|
||||
Oper (Opcee0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 76)
|
||||
Oper (Opcee8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 80)
|
||||
Oper (Opcef0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 80)
|
||||
Oper (Opcef8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opcfc0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 72)
|
||||
Oper (Opcfd0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 76)
|
||||
Oper (Opcfd8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 76)
|
||||
Oper (Opcfe0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 76)
|
||||
Oper (Opcfe8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 80)
|
||||
Oper (Opcff0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 80)
|
||||
Oper (Opcff8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+77)&0xfffffffc)
|
||||
|
||||
Oper (Opb000, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SN, 4)
|
||||
Oper (Opb010, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SN, 8)
|
||||
Oper (Opb018, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SN, 8)
|
||||
Oper (Opb020, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SN, 12)
|
||||
Oper (Opb028, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SN, 12)
|
||||
Oper (Opb030, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SN, 16)
|
||||
Oper (Opb038, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opb040, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SN, 4)
|
||||
Oper (Opb048, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 0, GRW, SN, 4)
|
||||
Oper (Opb050, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SN, 8)
|
||||
Oper (Opb058, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SN, 8)
|
||||
Oper (Opb060, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SN, 12)
|
||||
Oper (Opb068, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SN, 12)
|
||||
Oper (Opb070, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SN, 16)
|
||||
Oper (Opb078, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opb080, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SN, 8)
|
||||
Oper (Opb088, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 0, GRL, SN, 8)
|
||||
Oper (Opb090, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SN, 16)
|
||||
Oper (Opb098, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SN, 16)
|
||||
Oper (Opb0a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SN, 16)
|
||||
Oper (Opb0a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SN, 20)
|
||||
Oper (Opb0b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SN, 20)
|
||||
Oper (Opb0b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
Oper (Opb0c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 0, GRL, SN, 8)
|
||||
Oper (Opb0c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 0, GRL, SN, 8)
|
||||
Oper (Opb0d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 0, GRL, SN, 12)
|
||||
Oper (Opb0d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 0, GRL, SN, 12)
|
||||
Oper (Opb0e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 0, GRL, SN, 12)
|
||||
Oper (Opb0e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 0, GRL, SN, 16)
|
||||
Oper (Opb0f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 0, GRL, SN, 16)
|
||||
Oper (Opb0f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 0, GRL, SN, (cycles+13)&0xfffffffc)
|
||||
|
||||
Oper (Opb108, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 0, GMB, SN, 12)
|
||||
Oper (Opb148, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 0, GMW, SN, 12)
|
||||
Oper (Opb188, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 0, GML, SN, 20)
|
||||
Oper (Opb1c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 0, GRL, SN, 8)
|
||||
Oper (Opb1c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 0, GRL, SN, 8)
|
||||
Oper (Opb1d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 0, GRL, SN, 16)
|
||||
Oper (Opb1d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 0, GRL, SN, 16)
|
||||
Oper (Opb1e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 0, GRL, SN, 16)
|
||||
Oper (Opb1e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 0, GRL, SN, 20)
|
||||
Oper (Opb1f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 0, GRL, SN, 20)
|
||||
Oper (Opb1f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 0, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
|
||||
Oper (Opb200, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SN, 4)
|
||||
Oper (Opb210, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SN, 8)
|
||||
Oper (Opb218, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SN, 8)
|
||||
Oper (Opb220, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SN, 12)
|
||||
Oper (Opb228, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SN, 12)
|
||||
Oper (Opb230, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SN, 16)
|
||||
Oper (Opb238, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opb240, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SN, 4)
|
||||
Oper (Opb248, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 1, GRW, SN, 4)
|
||||
Oper (Opb250, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SN, 8)
|
||||
Oper (Opb258, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SN, 8)
|
||||
Oper (Opb260, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SN, 12)
|
||||
Oper (Opb268, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SN, 12)
|
||||
Oper (Opb270, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SN, 16)
|
||||
Oper (Opb278, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opb280, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SN, 8)
|
||||
Oper (Opb288, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 1, GRL, SN, 8)
|
||||
Oper (Opb290, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SN, 16)
|
||||
Oper (Opb298, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SN, 16)
|
||||
Oper (Opb2a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SN, 16)
|
||||
Oper (Opb2a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SN, 20)
|
||||
Oper (Opb2b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SN, 20)
|
||||
Oper (Opb2b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
Oper (Opb2c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 1, GRL, SN, 8)
|
||||
Oper (Opb2c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 1, GRL, SN, 8)
|
||||
Oper (Opb2d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 1, GRL, SN, 12)
|
||||
Oper (Opb2d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 1, GRL, SN, 12)
|
||||
Oper (Opb2e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 1, GRL, SN, 12)
|
||||
Oper (Opb2e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 1, GRL, SN, 16)
|
||||
Oper (Opb2f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 1, GRL, SN, 16)
|
||||
Oper (Opb2f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 1, GRL, SN, (cycles+13)&0xfffffffc)
|
||||
|
||||
Oper (Opb308, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 1, GMB, SN, 12)
|
||||
Oper (Opb348, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 1, GMW, SN, 12)
|
||||
Oper (Opb388, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 1, GML, SN, 20)
|
||||
Oper (Opb3c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 1, GRL, SN, 8)
|
||||
Oper (Opb3c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 1, GRL, SN, 8)
|
||||
Oper (Opb3d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 1, GRL, SN, 16)
|
||||
Oper (Opb3d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 1, GRL, SN, 16)
|
||||
Oper (Opb3e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 1, GRL, SN, 16)
|
||||
Oper (Opb3e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 1, GRL, SN, 20)
|
||||
Oper (Opb3f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 1, GRL, SN, 20)
|
||||
Oper (Opb3f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 1, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
|
||||
Oper (Opb400, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SN, 4)
|
||||
Oper (Opb410, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SN, 8)
|
||||
Oper (Opb418, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SN, 8)
|
||||
Oper (Opb420, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SN, 12)
|
||||
Oper (Opb428, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SN, 12)
|
||||
Oper (Opb430, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SN, 16)
|
||||
Oper (Opb438, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opb440, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SN, 4)
|
||||
Oper (Opb448, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 2, GRW, SN, 4)
|
||||
Oper (Opb450, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SN, 8)
|
||||
Oper (Opb458, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SN, 8)
|
||||
Oper (Opb460, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SN, 12)
|
||||
Oper (Opb468, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SN, 12)
|
||||
Oper (Opb470, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SN, 16)
|
||||
Oper (Opb478, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opb480, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SN, 8)
|
||||
Oper (Opb488, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 2, GRL, SN, 8)
|
||||
Oper (Opb490, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SN, 16)
|
||||
Oper (Opb498, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SN, 16)
|
||||
Oper (Opb4a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SN, 16)
|
||||
Oper (Opb4a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SN, 20)
|
||||
Oper (Opb4b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SN, 20)
|
||||
Oper (Opb4b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
Oper (Opb4c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 2, GRL, SN, 8)
|
||||
Oper (Opb4c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 2, GRL, SN, 8)
|
||||
Oper (Opb4d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 2, GRL, SN, 12)
|
||||
Oper (Opb4d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 2, GRL, SN, 12)
|
||||
Oper (Opb4e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 2, GRL, SN, 12)
|
||||
Oper (Opb4e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 2, GRL, SN, 16)
|
||||
Oper (Opb4f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 2, GRL, SN, 16)
|
||||
Oper (Opb4f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 2, GRL, SN, (cycles+13)&0xfffffffc)
|
||||
|
||||
Oper (Opb508, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 2, GMB, SN, 12)
|
||||
Oper (Opb548, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 2, GMW, SN, 12)
|
||||
Oper (Opb588, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 2, GML, SN, 20)
|
||||
Oper (Opb5c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 2, GRL, SN, 8)
|
||||
Oper (Opb5c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 2, GRL, SN, 8)
|
||||
Oper (Opb5d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 2, GRL, SN, 16)
|
||||
Oper (Opb5d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 2, GRL, SN, 16)
|
||||
Oper (Opb5e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 2, GRL, SN, 16)
|
||||
Oper (Opb5e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 2, GRL, SN, 20)
|
||||
Oper (Opb5f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 2, GRL, SN, 20)
|
||||
Oper (Opb5f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 2, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
|
||||
Oper (Opb600, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SN, 4)
|
||||
Oper (Opb610, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SN, 8)
|
||||
Oper (Opb618, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SN, 8)
|
||||
Oper (Opb620, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SN, 12)
|
||||
Oper (Opb628, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SN, 12)
|
||||
Oper (Opb630, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SN, 16)
|
||||
Oper (Opb638, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opb640, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SN, 4)
|
||||
Oper (Opb648, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 3, GRW, SN, 4)
|
||||
Oper (Opb650, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SN, 8)
|
||||
Oper (Opb658, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SN, 8)
|
||||
Oper (Opb660, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SN, 12)
|
||||
Oper (Opb668, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SN, 12)
|
||||
Oper (Opb670, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SN, 16)
|
||||
Oper (Opb678, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opb680, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SN, 8)
|
||||
Oper (Opb688, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 3, GRL, SN, 8)
|
||||
Oper (Opb690, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SN, 16)
|
||||
Oper (Opb698, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SN, 16)
|
||||
Oper (Opb6a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SN, 16)
|
||||
Oper (Opb6a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SN, 20)
|
||||
Oper (Opb6b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SN, 20)
|
||||
Oper (Opb6b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
Oper (Opb6c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 3, GRL, SN, 8)
|
||||
Oper (Opb6c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 3, GRL, SN, 8)
|
||||
Oper (Opb6d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 3, GRL, SN, 12)
|
||||
Oper (Opb6d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 3, GRL, SN, 12)
|
||||
Oper (Opb6e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 3, GRL, SN, 12)
|
||||
Oper (Opb6e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 3, GRL, SN, 16)
|
||||
Oper (Opb6f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 3, GRL, SN, 16)
|
||||
Oper (Opb6f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 3, GRL, SN, (cycles+13)&0xfffffffc)
|
||||
|
||||
Oper (Opb708, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 3, GMB, SN, 12)
|
||||
Oper (Opb748, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 3, GMW, SN, 12)
|
||||
Oper (Opb788, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 3, GML, SN, 20)
|
||||
Oper (Opb7c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 3, GRL, SN, 8)
|
||||
Oper (Opb7c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 3, GRL, SN, 8)
|
||||
Oper (Opb7d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 3, GRL, SN, 16)
|
||||
Oper (Opb7d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 3, GRL, SN, 16)
|
||||
Oper (Opb7e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 3, GRL, SN, 16)
|
||||
Oper (Opb7e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 3, GRL, SN, 20)
|
||||
Oper (Opb7f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 3, GRL, SN, 20)
|
||||
Oper (Opb7f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 3, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
|
||||
Oper (Opb800, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SN, 4)
|
||||
Oper (Opb810, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SN, 8)
|
||||
Oper (Opb818, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SN, 8)
|
||||
Oper (Opb820, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SN, 12)
|
||||
Oper (Opb828, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SN, 12)
|
||||
Oper (Opb830, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SN, 16)
|
||||
Oper (Opb838, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opb840, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SN, 4)
|
||||
Oper (Opb848, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 4, GRW, SN, 4)
|
||||
Oper (Opb850, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SN, 8)
|
||||
Oper (Opb858, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SN, 8)
|
||||
Oper (Opb860, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SN, 12)
|
||||
Oper (Opb868, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SN, 12)
|
||||
Oper (Opb870, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SN, 16)
|
||||
Oper (Opb878, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opb880, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SN, 8)
|
||||
Oper (Opb888, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 4, GRL, SN, 8)
|
||||
Oper (Opb890, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SN, 16)
|
||||
Oper (Opb898, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SN, 16)
|
||||
Oper (Opb8a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SN, 16)
|
||||
Oper (Opb8a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SN, 20)
|
||||
Oper (Opb8b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SN, 20)
|
||||
Oper (Opb8b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
Oper (Opb8c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 4, GRL, SN, 8)
|
||||
Oper (Opb8c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 4, GRL, SN, 8)
|
||||
Oper (Opb8d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 4, GRL, SN, 12)
|
||||
Oper (Opb8d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 4, GRL, SN, 12)
|
||||
Oper (Opb8e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 4, GRL, SN, 12)
|
||||
Oper (Opb8e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 4, GRL, SN, 16)
|
||||
Oper (Opb8f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 4, GRL, SN, 16)
|
||||
Oper (Opb8f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 4, GRL, SN, (cycles+13)&0xfffffffc)
|
||||
|
||||
Oper (Opb908, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 4, GMB, SN, 12)
|
||||
Oper (Opb948, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 4, GMW, SN, 12)
|
||||
Oper (Opb988, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 4, GML, SN, 20)
|
||||
Oper (Opb9c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 4, GRL, SN, 8)
|
||||
Oper (Opb9c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 4, GRL, SN, 8)
|
||||
Oper (Opb9d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 4, GRL, SN, 16)
|
||||
Oper (Opb9d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 4, GRL, SN, 16)
|
||||
Oper (Opb9e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 4, GRL, SN, 16)
|
||||
Oper (Opb9e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 4, GRL, SN, 20)
|
||||
Oper (Opb9f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 4, GRL, SN, 20)
|
||||
Oper (Opb9f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 4, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
|
||||
Oper (Opba00, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SN, 4)
|
||||
Oper (Opba10, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SN, 8)
|
||||
Oper (Opba18, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SN, 8)
|
||||
Oper (Opba20, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SN, 12)
|
||||
Oper (Opba28, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SN, 12)
|
||||
Oper (Opba30, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SN, 16)
|
||||
Oper (Opba38, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opba40, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SN, 4)
|
||||
Oper (Opba48, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 5, GRW, SN, 4)
|
||||
Oper (Opba50, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SN, 8)
|
||||
Oper (Opba58, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SN, 8)
|
||||
Oper (Opba60, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SN, 12)
|
||||
Oper (Opba68, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SN, 12)
|
||||
Oper (Opba70, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SN, 16)
|
||||
Oper (Opba78, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opba80, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SN, 8)
|
||||
Oper (Opba88, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 5, GRL, SN, 8)
|
||||
Oper (Opba90, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SN, 16)
|
||||
Oper (Opba98, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SN, 16)
|
||||
Oper (Opbaa0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SN, 16)
|
||||
Oper (Opbaa8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SN, 20)
|
||||
Oper (Opbab0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SN, 20)
|
||||
Oper (Opbab8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
Oper (Opbac0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 5, GRL, SN, 8)
|
||||
Oper (Opbac8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 5, GRL, SN, 8)
|
||||
Oper (Opbad0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 5, GRL, SN, 12)
|
||||
Oper (Opbad8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 5, GRL, SN, 12)
|
||||
Oper (Opbae0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 5, GRL, SN, 12)
|
||||
Oper (Opbae8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 5, GRL, SN, 16)
|
||||
Oper (Opbaf0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 5, GRL, SN, 16)
|
||||
Oper (Opbaf8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 5, GRL, SN, (cycles+13)&0xfffffffc)
|
||||
|
||||
Oper (Opbb08, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 5, GMB, SN, 12)
|
||||
Oper (Opbb48, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 5, GMW, SN, 12)
|
||||
Oper (Opbb88, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 5, GML, SN, 20)
|
||||
Oper (Opbbc0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 5, GRL, SN, 8)
|
||||
Oper (Opbbc8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 5, GRL, SN, 8)
|
||||
Oper (Opbbd0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 5, GRL, SN, 16)
|
||||
Oper (Opbbd8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 5, GRL, SN, 16)
|
||||
Oper (Opbbe0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 5, GRL, SN, 16)
|
||||
Oper (Opbbe8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 5, GRL, SN, 20)
|
||||
Oper (Opbbf0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 5, GRL, SN, 20)
|
||||
Oper (Opbbf8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 5, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
|
||||
Oper (Opbc00, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SN, 4)
|
||||
Oper (Opbc10, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SN, 8)
|
||||
Oper (Opbc18, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SN, 8)
|
||||
Oper (Opbc20, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SN, 12)
|
||||
Oper (Opbc28, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SN, 12)
|
||||
Oper (Opbc30, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SN, 16)
|
||||
Oper (Opbc38, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opbc40, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SN, 4)
|
||||
Oper (Opbc48, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 6, GRW, SN, 4)
|
||||
Oper (Opbc50, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SN, 8)
|
||||
Oper (Opbc58, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SN, 8)
|
||||
Oper (Opbc60, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SN, 12)
|
||||
Oper (Opbc68, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SN, 12)
|
||||
Oper (Opbc70, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SN, 16)
|
||||
Oper (Opbc78, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opbc80, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SN, 8)
|
||||
Oper (Opbc88, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 6, GRL, SN, 8)
|
||||
Oper (Opbc90, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SN, 16)
|
||||
Oper (Opbc98, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SN, 16)
|
||||
Oper (Opbca0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SN, 16)
|
||||
Oper (Opbca8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SN, 20)
|
||||
Oper (Opbcb0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SN, 20)
|
||||
Oper (Opbcb8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
Oper (Opbcc0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 6, GRL, SN, 8)
|
||||
Oper (Opbcc8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 6, GRL, SN, 8)
|
||||
Oper (Opbcd0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 6, GRL, SN, 12)
|
||||
Oper (Opbcd8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 6, GRL, SN, 12)
|
||||
Oper (Opbce0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 6, GRL, SN, 12)
|
||||
Oper (Opbce8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 6, GRL, SN, 16)
|
||||
Oper (Opbcf0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 6, GRL, SN, 16)
|
||||
Oper (Opbcf8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 6, GRL, SN, (cycles+13)&0xfffffffc)
|
||||
|
||||
Oper (Opbd08, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 6, GMB, SN, 12)
|
||||
Oper (Opbd48, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 6, GMW, SN, 12)
|
||||
Oper (Opbd88, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 6, GML, SN, 20)
|
||||
Oper (Opbdc0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 6, GRL, SN, 8)
|
||||
Oper (Opbdc8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 6, GRL, SN, 8)
|
||||
Oper (Opbdd0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 6, GRL, SN, 16)
|
||||
Oper (Opbdd8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 6, GRL, SN, 16)
|
||||
Oper (Opbde0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 6, GRL, SN, 16)
|
||||
Oper (Opbde8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 6, GRL, SN, 20)
|
||||
Oper (Opbdf0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 6, GRL, SN, 20)
|
||||
Oper (Opbdf8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 6, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
|
||||
Oper (Opbe00, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SN, 4)
|
||||
Oper (Opbe10, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SN, 8)
|
||||
Oper (Opbe18, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SN, 8)
|
||||
Oper (Opbe20, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SN, 12)
|
||||
Oper (Opbe28, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SN, 12)
|
||||
Oper (Opbe30, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SN, 16)
|
||||
Oper (Opbe38, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opbe40, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SN, 4)
|
||||
Oper (Opbe48, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 7, GRW, SN, 4)
|
||||
Oper (Opbe50, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SN, 8)
|
||||
Oper (Opbe58, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SN, 8)
|
||||
Oper (Opbe60, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SN, 12)
|
||||
Oper (Opbe68, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SN, 12)
|
||||
Oper (Opbe70, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SN, 16)
|
||||
Oper (Opbe78, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SN, (cycles+11)&0xfffffffc)
|
||||
Oper (Opbe80, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SN, 8)
|
||||
Oper (Opbe88, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 7, GRL, SN, 8)
|
||||
Oper (Opbe90, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SN, 16)
|
||||
Oper (Opbe98, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SN, 16)
|
||||
Oper (Opbea0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SN, 16)
|
||||
Oper (Opbea8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SN, 20)
|
||||
Oper (Opbeb0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SN, 20)
|
||||
Oper (Opbeb8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
Oper (Opbec0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 7, GRL, SN, 8)
|
||||
Oper (Opbec8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 7, GRL, SN, 8)
|
||||
Oper (Opbed0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 7, GRL, SN, 12)
|
||||
Oper (Opbed8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 7, GRL, SN, 12)
|
||||
Oper (Opbee0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 7, GRL, SN, 12)
|
||||
Oper (Opbee8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 7, GRL, SN, 16)
|
||||
Oper (Opbef0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 7, GRL, SN, 16)
|
||||
Oper (Opbef8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 7, GRL, SN, (cycles+13)&0xfffffffc)
|
||||
|
||||
Oper (Opbf08, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB15, 7, GMB, SN, 12)
|
||||
Oper (Opbf48, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 7, GMW, SN, 12)
|
||||
Oper (Opbf88, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 7, GML, SN, 20)
|
||||
Oper (Opbfc0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 7, GRL, SN, 8)
|
||||
Oper (Opbfc8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 7, GRL, SN, 8)
|
||||
Oper (Opbfd0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 7, GRL, SN, 16)
|
||||
Oper (Opbfd8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 7, GRL, SN, 16)
|
||||
Oper (Opbfe0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 7, GRL, SN, 16)
|
||||
Oper (Opbfe8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 7, GRL, SN, 20)
|
||||
Oper (Opbff0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 7, GRL, SN, 20)
|
||||
Oper (Opbff8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 7, GRL, SN, (cycles+17)&0xfffffffc)
|
||||
|
||||
Oper (Op80c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 140)
|
||||
Oper (Op80d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 144)
|
||||
Oper (Op80d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 144)
|
||||
Oper (Op80e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 148)
|
||||
Oper (Op80e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 148)
|
||||
Oper (Op80f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 152)
|
||||
Oper (Op80f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+147)&0xfffffffc)
|
||||
|
||||
Oper (Op81c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 160)
|
||||
Oper (Op81d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 164)
|
||||
Oper (Op81d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 164)
|
||||
Oper (Op81e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 164)
|
||||
Oper (Op81e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 168)
|
||||
Oper (Op81f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 168)
|
||||
Oper (Op81f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+165)&0xfffffffc)
|
||||
|
||||
Oper (Op82c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 140)
|
||||
Oper (Op82d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 144)
|
||||
Oper (Op82d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 144)
|
||||
Oper (Op82e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 148)
|
||||
Oper (Op82e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 148)
|
||||
Oper (Op82f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 152)
|
||||
Oper (Op82f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+147)&0xfffffffc)
|
||||
|
||||
Oper (Op83c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 160)
|
||||
Oper (Op83d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 164)
|
||||
Oper (Op83d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 164)
|
||||
Oper (Op83e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 164)
|
||||
Oper (Op83e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 168)
|
||||
Oper (Op83f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 168)
|
||||
Oper (Op83f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+165)&0xfffffffc)
|
||||
|
||||
Oper (Op84c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 140)
|
||||
Oper (Op84d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 144)
|
||||
Oper (Op84d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 144)
|
||||
Oper (Op84e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 148)
|
||||
Oper (Op84e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 148)
|
||||
Oper (Op84f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 152)
|
||||
Oper (Op84f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+147)&0xfffffffc)
|
||||
|
||||
Oper (Op85c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 160)
|
||||
Oper (Op85d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 164)
|
||||
Oper (Op85d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 164)
|
||||
Oper (Op85e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 164)
|
||||
Oper (Op85e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 168)
|
||||
Oper (Op85f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 168)
|
||||
Oper (Op85f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+165)&0xfffffffc)
|
||||
|
||||
Oper (Op86c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 140)
|
||||
Oper (Op86d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 144)
|
||||
Oper (Op86d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 144)
|
||||
Oper (Op86e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 148)
|
||||
Oper (Op86e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 148)
|
||||
Oper (Op86f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 152)
|
||||
Oper (Op86f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+147)&0xfffffffc)
|
||||
|
||||
Oper (Op87c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 160)
|
||||
Oper (Op87d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 164)
|
||||
Oper (Op87d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 164)
|
||||
Oper (Op87e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 164)
|
||||
Oper (Op87e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 168)
|
||||
Oper (Op87f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 168)
|
||||
Oper (Op87f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+165)&0xfffffffc)
|
||||
|
||||
Oper (Op88c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 140)
|
||||
Oper (Op88d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 144)
|
||||
Oper (Op88d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 144)
|
||||
Oper (Op88e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 148)
|
||||
Oper (Op88e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 148)
|
||||
Oper (Op88f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 152)
|
||||
Oper (Op88f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+147)&0xfffffffc)
|
||||
|
||||
Oper (Op89c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 160)
|
||||
Oper (Op89d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 164)
|
||||
Oper (Op89d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 164)
|
||||
Oper (Op89e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 164)
|
||||
Oper (Op89e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 168)
|
||||
Oper (Op89f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 168)
|
||||
Oper (Op89f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+165)&0xfffffffc)
|
||||
|
||||
Oper (Op8ac0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 140)
|
||||
Oper (Op8ad0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 144)
|
||||
Oper (Op8ad8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 144)
|
||||
Oper (Op8ae0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 148)
|
||||
Oper (Op8ae8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 148)
|
||||
Oper (Op8af0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 152)
|
||||
Oper (Op8af8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+147)&0xfffffffc)
|
||||
|
||||
Oper (Op8bc0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 160)
|
||||
Oper (Op8bd0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 164)
|
||||
Oper (Op8bd8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 164)
|
||||
Oper (Op8be0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 164)
|
||||
Oper (Op8be8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 168)
|
||||
Oper (Op8bf0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 168)
|
||||
Oper (Op8bf8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+165)&0xfffffffc)
|
||||
|
||||
Oper (Op8cc0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 140)
|
||||
Oper (Op8cd0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 144)
|
||||
Oper (Op8cd8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 144)
|
||||
Oper (Op8ce0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 148)
|
||||
Oper (Op8ce8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 148)
|
||||
Oper (Op8cf0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 152)
|
||||
Oper (Op8cf8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+147)&0xfffffffc)
|
||||
|
||||
Oper (Op8dc0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 160)
|
||||
Oper (Op8dd0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 164)
|
||||
Oper (Op8dd8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 164)
|
||||
Oper (Op8de0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 164)
|
||||
Oper (Op8de8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 168)
|
||||
Oper (Op8df0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 168)
|
||||
Oper (Op8df8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+165)&0xfffffffc)
|
||||
|
||||
Oper (Op8ec0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 140)
|
||||
Oper (Op8ed0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 144)
|
||||
Oper (Op8ed8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 144)
|
||||
Oper (Op8ee0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 148)
|
||||
Oper (Op8ee8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 148)
|
||||
Oper (Op8ef0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 152)
|
||||
Oper (Op8ef8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+147)&0xfffffffc)
|
||||
|
||||
Oper (Op8fc0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 160)
|
||||
Oper (Op8fd0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 164)
|
||||
Oper (Op8fd8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 164)
|
||||
Oper (Op8fe0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 164)
|
||||
Oper (Op8fe8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 168)
|
||||
Oper (Op8ff0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 168)
|
||||
Oper (Op8ff8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+165)&0xfffffffc)
|
||||
|
||||
Oper (Op0c00, DoCmpB, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SN, 8)
|
||||
Oper (Op0c10, DoCmpB, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SN, 12)
|
||||
Oper (Op0c18, DoCmpB, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SN, 12)
|
||||
Oper (Op0c20, DoCmpB, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SN, 16)
|
||||
Oper (Op0c28, DoCmpB, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SN, 16)
|
||||
Oper (Op0c30, DoCmpB, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SN, 20)
|
||||
Oper (Op0c38, DoCmpB, DB, SimmB, 0, DB, DA, Ceaw, ins7, GMB, SN, (cycles+19)&0xfffffffc)
|
||||
Oper (Op0c40, DoCmpW, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SN, 8)
|
||||
Oper (Op0c50, DoCmpW, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SN, 12)
|
||||
Oper (Op0c58, DoCmpW, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SN, 12)
|
||||
Oper (Op0c60, DoCmpW, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SN, 16)
|
||||
Oper (Op0c68, DoCmpW, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SN, 16)
|
||||
Oper (Op0c70, DoCmpW, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SN, 20)
|
||||
Oper (Op0c78, DoCmpW, DW, SimmW, 0, DW, DA, Ceaw, ins7, GMW, SN, (cycles+19)&0xfffffffc)
|
||||
Oper (Op0c80, DoCmpL, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SN, 16)
|
||||
Oper (Op0c90, DoCmpL, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SN, 20)
|
||||
Oper (Op0c98, DoCmpL, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SN, 20)
|
||||
Oper (Op0ca0, DoCmpL, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SN, 24)
|
||||
Oper (Op0ca8, DoCmpL, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SN, 24)
|
||||
Oper (Op0cb0, DoCmpL, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SN, 28)
|
||||
Oper (Op0cb8, DoCmpL, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SN, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opc100, DoABCD, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 8)
|
||||
Oper (Opc108, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20)
|
||||
Oper (Opc300, DoABCD, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 8)
|
||||
Oper (Opc308, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20)
|
||||
Oper (Opc500, DoABCD, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 8)
|
||||
Oper (Opc508, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20)
|
||||
Oper (Opc700, DoABCD, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 8)
|
||||
Oper (Opc708, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20)
|
||||
Oper (Opc900, DoABCD, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 8)
|
||||
Oper (Opc908, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20)
|
||||
Oper (Opcb00, DoABCD, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 8)
|
||||
Oper (Opcb08, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20)
|
||||
Oper (Opcd00, DoABCD, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 8)
|
||||
Oper (Opcd08, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20)
|
||||
Oper (Opcf00, DoABCD, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 8)
|
||||
Oper (Opcf08, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 7, GMB, SMB, 20)
|
||||
|
||||
Oper (Op8100, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 8)
|
||||
Oper (Op8108, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20)
|
||||
Oper (Op8300, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 8)
|
||||
Oper (Op8308, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20)
|
||||
Oper (Op8500, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 8)
|
||||
Oper (Op8508, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20)
|
||||
Oper (Op8700, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 8)
|
||||
Oper (Op8708, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20)
|
||||
Oper (Op8900, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 8)
|
||||
Oper (Op8908, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20)
|
||||
Oper (Op8b00, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 8)
|
||||
Oper (Op8b08, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20)
|
||||
Oper (Op8d00, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 8)
|
||||
Oper (Op8d08, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20)
|
||||
Oper (Op8f00, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 8)
|
||||
Oper (Op8f08, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 7, GMB, SMB, 20)
|
||||
|
||||
Oper (Op4800, DoNBCD, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 8)
|
||||
Oper (Op4810, DoNBCD, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op4818, DoNBCD, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op4820, DoNBCD, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op4828, DoNBCD, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op4830, DoNBCD, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op4838, DoNBCD, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
|
|
@ -0,0 +1,974 @@
|
|||
/*
|
||||
* Castaway
|
||||
* (C) 1994 - 2002 Martin Doering, Joachim Hoenig
|
||||
*
|
||||
* $File$ - 68k logical instructions
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*
|
||||
* revision history
|
||||
* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring
|
||||
* 10.07.2002 JH Minor clarification when CCR/SR is target (without effect)
|
||||
* 27.08.2002 JH ... with effect! Fixed bug. Restructured & clarified.
|
||||
*/
|
||||
#ifndef PROTOH
|
||||
static char sccsid[] = "$Id: op68klogop.c,v 1.3 2002/08/27 01:21:11 jhoenig Exp $";
|
||||
#include "68000.h"
|
||||
#include "op68k.h"
|
||||
#include "operin.h"
|
||||
|
||||
/*
|
||||
* Opfuncs.
|
||||
*/
|
||||
#define OlogSR(Code, Op, OpSR, Priv, DeclS, Get1, DeclT, Get2, Set2, GetSR, SetSR, retval)\
|
||||
unsigned long Code(operin)\
|
||||
{\
|
||||
register unsigned long cycles=0;\
|
||||
DeclS(source)\
|
||||
DeclT(target)\
|
||||
long address;\
|
||||
switch ins7 {\
|
||||
case 0x0:\
|
||||
Get1(source, 0)\
|
||||
address = GetMPCW();\
|
||||
pc += 2;\
|
||||
Get2(address, target)\
|
||||
Op(target, source)\
|
||||
Set2(address, target)\
|
||||
break;\
|
||||
case 0x1:\
|
||||
Get1(source, 0)\
|
||||
address = GetMPCL();\
|
||||
pc += 4;\
|
||||
Get2(address, target)\
|
||||
Op(target, source)\
|
||||
Set2(address, target)\
|
||||
break;\
|
||||
case 0x4:\
|
||||
if (Priv && !GetS()) { ExceptionGroup1(PRIV); };\
|
||||
Get1(source, 0)\
|
||||
GetSR(address2, target)\
|
||||
OpSR(target, source)\
|
||||
SetSR(address2, target)\
|
||||
break;\
|
||||
default:\
|
||||
ExceptionGroup1(ILLINSTR);\
|
||||
break;\
|
||||
}\
|
||||
return retval;\
|
||||
}
|
||||
|
||||
#define DoAnd(target,source) target &= source; ClrCVSetNZ(target);
|
||||
#define DoAndSR(target,source) target &= source;
|
||||
|
||||
#define DoEor(target,source) target ^= source; ClrCVSetNZ(target);
|
||||
#define DoEorSR(target,source) target ^= source;
|
||||
|
||||
#define DoOr(target,source) target |= source; ClrCVSetNZ(target);
|
||||
#define DoOrSR(target,source) target |= source;
|
||||
|
||||
#else
|
||||
|
||||
#define OlogSR(a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12) \
|
||||
extern unsigned long a1(operin);
|
||||
|
||||
#endif
|
||||
|
||||
Oper (Opc000, DoAnd, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4)
|
||||
Oper (Opc010, DoAnd, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8)
|
||||
Oper (Opc018, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8)
|
||||
Oper (Opc020, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12)
|
||||
Oper (Opc028, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12)
|
||||
Oper (Opc030, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16)
|
||||
Oper (Opc038, DoAnd, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opc040, DoAnd, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4)
|
||||
Oper (Opc050, DoAnd, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8)
|
||||
Oper (Opc058, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8)
|
||||
Oper (Opc060, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12)
|
||||
Oper (Opc068, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12)
|
||||
Oper (Opc070, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16)
|
||||
Oper (Opc078, DoAnd, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opc080, DoAnd, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8)
|
||||
Oper (Opc090, DoAnd, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Opc098, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Opc0a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Opc0a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20)
|
||||
Oper (Opc0b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20)
|
||||
Oper (Opc0b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opc110, DoAnd, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opc118, DoAnd, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opc120, DoAnd, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opc128, DoAnd, DB, SdB, 0, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opc130, DoAnd, DB, SdB, 0, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opc138, DoAnd, DB, SdB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opc150, DoAnd, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opc158, DoAnd, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opc160, DoAnd, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opc168, DoAnd, DW, SdW, 0, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opc170, DoAnd, DW, SdW, 0, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opc178, DoAnd, DW, SdW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opc190, DoAnd, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opc198, DoAnd, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opc1a0, DoAnd, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opc1a8, DoAnd, DL, SdL, 0, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opc1b0, DoAnd, DL, SdL, 0, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opc1b8, DoAnd, DL, SdL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opc200, DoAnd, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4)
|
||||
Oper (Opc210, DoAnd, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8)
|
||||
Oper (Opc218, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8)
|
||||
Oper (Opc220, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12)
|
||||
Oper (Opc228, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12)
|
||||
Oper (Opc230, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16)
|
||||
Oper (Opc238, DoAnd, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opc240, DoAnd, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4)
|
||||
Oper (Opc250, DoAnd, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8)
|
||||
Oper (Opc258, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8)
|
||||
Oper (Opc260, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12)
|
||||
Oper (Opc268, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12)
|
||||
Oper (Opc270, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16)
|
||||
Oper (Opc278, DoAnd, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opc280, DoAnd, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8)
|
||||
Oper (Opc290, DoAnd, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Opc298, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Opc2a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Opc2a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20)
|
||||
Oper (Opc2b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20)
|
||||
Oper (Opc2b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opc310, DoAnd, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opc318, DoAnd, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opc320, DoAnd, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opc328, DoAnd, DB, SdB, 1, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opc330, DoAnd, DB, SdB, 1, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opc338, DoAnd, DB, SdB, 1, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opc350, DoAnd, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opc358, DoAnd, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opc360, DoAnd, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opc368, DoAnd, DW, SdW, 1, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opc370, DoAnd, DW, SdW, 1, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opc378, DoAnd, DW, SdW, 1, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opc390, DoAnd, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opc398, DoAnd, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opc3a0, DoAnd, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opc3a8, DoAnd, DL, SdL, 1, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opc3b0, DoAnd, DL, SdL, 1, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opc3b8, DoAnd, DL, SdL, 1, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opc400, DoAnd, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4)
|
||||
Oper (Opc410, DoAnd, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8)
|
||||
Oper (Opc418, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8)
|
||||
Oper (Opc420, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12)
|
||||
Oper (Opc428, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12)
|
||||
Oper (Opc430, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16)
|
||||
Oper (Opc438, DoAnd, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opc440, DoAnd, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4)
|
||||
Oper (Opc450, DoAnd, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8)
|
||||
Oper (Opc458, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8)
|
||||
Oper (Opc460, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12)
|
||||
Oper (Opc468, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12)
|
||||
Oper (Opc470, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16)
|
||||
Oper (Opc478, DoAnd, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opc480, DoAnd, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8)
|
||||
Oper (Opc490, DoAnd, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Opc498, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Opc4a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Opc4a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20)
|
||||
Oper (Opc4b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20)
|
||||
Oper (Opc4b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opc510, DoAnd, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opc518, DoAnd, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opc520, DoAnd, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opc528, DoAnd, DB, SdB, 2, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opc530, DoAnd, DB, SdB, 2, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opc538, DoAnd, DB, SdB, 2, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opc550, DoAnd, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opc558, DoAnd, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opc560, DoAnd, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opc568, DoAnd, DW, SdW, 2, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opc570, DoAnd, DW, SdW, 2, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opc578, DoAnd, DW, SdW, 2, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opc590, DoAnd, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opc598, DoAnd, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opc5a0, DoAnd, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opc5a8, DoAnd, DL, SdL, 2, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opc5b0, DoAnd, DL, SdL, 2, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opc5b8, DoAnd, DL, SdL, 2, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opc600, DoAnd, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4)
|
||||
Oper (Opc610, DoAnd, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8)
|
||||
Oper (Opc618, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8)
|
||||
Oper (Opc620, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12)
|
||||
Oper (Opc628, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12)
|
||||
Oper (Opc630, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16)
|
||||
Oper (Opc638, DoAnd, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opc640, DoAnd, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4)
|
||||
Oper (Opc650, DoAnd, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8)
|
||||
Oper (Opc658, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8)
|
||||
Oper (Opc660, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12)
|
||||
Oper (Opc668, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12)
|
||||
Oper (Opc670, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16)
|
||||
Oper (Opc678, DoAnd, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opc680, DoAnd, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8)
|
||||
Oper (Opc690, DoAnd, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Opc698, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Opc6a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Opc6a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20)
|
||||
Oper (Opc6b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20)
|
||||
Oper (Opc6b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opc710, DoAnd, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opc718, DoAnd, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opc720, DoAnd, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opc728, DoAnd, DB, SdB, 3, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opc730, DoAnd, DB, SdB, 3, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opc738, DoAnd, DB, SdB, 3, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opc750, DoAnd, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opc758, DoAnd, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opc760, DoAnd, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opc768, DoAnd, DW, SdW, 3, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opc770, DoAnd, DW, SdW, 3, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opc778, DoAnd, DW, SdW, 3, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opc790, DoAnd, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opc798, DoAnd, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opc7a0, DoAnd, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opc7a8, DoAnd, DL, SdL, 3, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opc7b0, DoAnd, DL, SdL, 3, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opc7b8, DoAnd, DL, SdL, 3, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opc800, DoAnd, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4)
|
||||
Oper (Opc810, DoAnd, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8)
|
||||
Oper (Opc818, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8)
|
||||
Oper (Opc820, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12)
|
||||
Oper (Opc828, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12)
|
||||
Oper (Opc830, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16)
|
||||
Oper (Opc838, DoAnd, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opc840, DoAnd, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4)
|
||||
Oper (Opc850, DoAnd, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8)
|
||||
Oper (Opc858, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8)
|
||||
Oper (Opc860, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12)
|
||||
Oper (Opc868, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12)
|
||||
Oper (Opc870, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16)
|
||||
Oper (Opc878, DoAnd, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opc880, DoAnd, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8)
|
||||
Oper (Opc890, DoAnd, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Opc898, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Opc8a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Opc8a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20)
|
||||
Oper (Opc8b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20)
|
||||
Oper (Opc8b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opc910, DoAnd, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opc918, DoAnd, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opc920, DoAnd, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opc928, DoAnd, DB, SdB, 4, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opc930, DoAnd, DB, SdB, 4, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opc938, DoAnd, DB, SdB, 4, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opc950, DoAnd, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opc958, DoAnd, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opc960, DoAnd, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opc968, DoAnd, DW, SdW, 4, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opc970, DoAnd, DW, SdW, 4, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opc978, DoAnd, DW, SdW, 4, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opc990, DoAnd, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opc998, DoAnd, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opc9a0, DoAnd, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opc9a8, DoAnd, DL, SdL, 4, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opc9b0, DoAnd, DL, SdL, 4, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opc9b8, DoAnd, DL, SdL, 4, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opca00, DoAnd, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4)
|
||||
Oper (Opca10, DoAnd, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8)
|
||||
Oper (Opca18, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8)
|
||||
Oper (Opca20, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12)
|
||||
Oper (Opca28, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12)
|
||||
Oper (Opca30, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16)
|
||||
Oper (Opca38, DoAnd, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opca40, DoAnd, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4)
|
||||
Oper (Opca50, DoAnd, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8)
|
||||
Oper (Opca58, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8)
|
||||
Oper (Opca60, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12)
|
||||
Oper (Opca68, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12)
|
||||
Oper (Opca70, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16)
|
||||
Oper (Opca78, DoAnd, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opca80, DoAnd, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8)
|
||||
Oper (Opca90, DoAnd, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Opca98, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Opcaa0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Opcaa8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20)
|
||||
Oper (Opcab0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20)
|
||||
Oper (Opcab8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opcb10, DoAnd, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opcb18, DoAnd, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opcb20, DoAnd, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opcb28, DoAnd, DB, SdB, 5, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opcb30, DoAnd, DB, SdB, 5, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opcb38, DoAnd, DB, SdB, 5, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opcb50, DoAnd, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opcb58, DoAnd, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opcb60, DoAnd, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opcb68, DoAnd, DW, SdW, 5, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opcb70, DoAnd, DW, SdW, 5, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opcb78, DoAnd, DW, SdW, 5, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opcb90, DoAnd, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opcb98, DoAnd, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opcba0, DoAnd, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opcba8, DoAnd, DL, SdL, 5, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opcbb0, DoAnd, DL, SdL, 5, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opcbb8, DoAnd, DL, SdL, 5, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opcc00, DoAnd, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4)
|
||||
Oper (Opcc10, DoAnd, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8)
|
||||
Oper (Opcc18, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8)
|
||||
Oper (Opcc20, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12)
|
||||
Oper (Opcc28, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12)
|
||||
Oper (Opcc30, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16)
|
||||
Oper (Opcc38, DoAnd, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opcc40, DoAnd, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4)
|
||||
Oper (Opcc50, DoAnd, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8)
|
||||
Oper (Opcc58, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8)
|
||||
Oper (Opcc60, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12)
|
||||
Oper (Opcc68, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12)
|
||||
Oper (Opcc70, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16)
|
||||
Oper (Opcc78, DoAnd, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opcc80, DoAnd, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8)
|
||||
Oper (Opcc90, DoAnd, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Opcc98, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Opcca0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Opcca8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20)
|
||||
Oper (Opccb0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20)
|
||||
Oper (Opccb8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opcd10, DoAnd, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opcd18, DoAnd, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opcd20, DoAnd, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opcd28, DoAnd, DB, SdB, 6, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opcd30, DoAnd, DB, SdB, 6, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opcd38, DoAnd, DB, SdB, 6, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opcd50, DoAnd, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opcd58, DoAnd, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opcd60, DoAnd, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opcd68, DoAnd, DW, SdW, 6, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opcd70, DoAnd, DW, SdW, 6, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opcd78, DoAnd, DW, SdW, 6, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opcd90, DoAnd, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opcd98, DoAnd, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opcda0, DoAnd, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opcda8, DoAnd, DL, SdL, 6, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opcdb0, DoAnd, DL, SdL, 6, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opcdb8, DoAnd, DL, SdL, 6, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opce00, DoAnd, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4)
|
||||
Oper (Opce10, DoAnd, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8)
|
||||
Oper (Opce18, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8)
|
||||
Oper (Opce20, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12)
|
||||
Oper (Opce28, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12)
|
||||
Oper (Opce30, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16)
|
||||
Oper (Opce38, DoAnd, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Opce40, DoAnd, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4)
|
||||
Oper (Opce50, DoAnd, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8)
|
||||
Oper (Opce58, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8)
|
||||
Oper (Opce60, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12)
|
||||
Oper (Opce68, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12)
|
||||
Oper (Opce70, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16)
|
||||
Oper (Opce78, DoAnd, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Opce80, DoAnd, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8)
|
||||
Oper (Opce90, DoAnd, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Opce98, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Opcea0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Opcea8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20)
|
||||
Oper (Opceb0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20)
|
||||
Oper (Opceb8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Opcf10, DoAnd, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opcf18, DoAnd, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opcf20, DoAnd, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opcf28, DoAnd, DB, SdB, 7, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opcf30, DoAnd, DB, SdB, 7, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opcf38, DoAnd, DB, SdB, 7, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opcf50, DoAnd, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opcf58, DoAnd, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opcf60, DoAnd, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opcf68, DoAnd, DW, SdW, 7, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opcf70, DoAnd, DW, SdW, 7, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opcf78, DoAnd, DW, SdW, 7, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opcf90, DoAnd, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opcf98, DoAnd, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opcfa0, DoAnd, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opcfa8, DoAnd, DL, SdL, 7, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opcfb0, DoAnd, DL, SdL, 7, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opcfb8, DoAnd, DL, SdL, 7, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op8000, DoOr, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4)
|
||||
Oper (Op8010, DoOr, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8)
|
||||
Oper (Op8018, DoOr, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8)
|
||||
Oper (Op8020, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12)
|
||||
Oper (Op8028, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12)
|
||||
Oper (Op8030, DoOr, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16)
|
||||
Oper (Op8038, DoOr, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8040, DoOr, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4)
|
||||
Oper (Op8050, DoOr, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8)
|
||||
Oper (Op8058, DoOr, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8)
|
||||
Oper (Op8060, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12)
|
||||
Oper (Op8068, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12)
|
||||
Oper (Op8070, DoOr, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16)
|
||||
Oper (Op8078, DoOr, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8080, DoOr, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8)
|
||||
Oper (Op8090, DoOr, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Op8098, DoOr, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Op80a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Op80a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20)
|
||||
Oper (Op80b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20)
|
||||
Oper (Op80b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op8110, DoOr, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op8118, DoOr, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op8120, DoOr, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op8128, DoOr, DB, SdB, 0, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op8130, DoOr, DB, SdB, 0, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Op8138, DoOr, DB, SdB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8150, DoOr, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op8158, DoOr, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op8160, DoOr, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op8168, DoOr, DW, SdW, 0, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op8170, DoOr, DW, SdW, 0, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Op8178, DoOr, DW, SdW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8190, DoOr, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op8198, DoOr, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op81a0, DoOr, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op81a8, DoOr, DL, SdL, 0, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Op81b0, DoOr, DL, SdL, 0, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Op81b8, DoOr, DL, SdL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op8200, DoOr, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4)
|
||||
Oper (Op8210, DoOr, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8)
|
||||
Oper (Op8218, DoOr, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8)
|
||||
Oper (Op8220, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12)
|
||||
Oper (Op8228, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12)
|
||||
Oper (Op8230, DoOr, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16)
|
||||
Oper (Op8238, DoOr, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8240, DoOr, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4)
|
||||
Oper (Op8250, DoOr, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8)
|
||||
Oper (Op8258, DoOr, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8)
|
||||
Oper (Op8260, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12)
|
||||
Oper (Op8268, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12)
|
||||
Oper (Op8270, DoOr, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16)
|
||||
Oper (Op8278, DoOr, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8280, DoOr, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8)
|
||||
Oper (Op8290, DoOr, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Op8298, DoOr, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Op82a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Op82a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20)
|
||||
Oper (Op82b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20)
|
||||
Oper (Op82b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op8310, DoOr, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op8318, DoOr, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op8320, DoOr, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op8328, DoOr, DB, SdB, 1, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op8330, DoOr, DB, SdB, 1, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Op8338, DoOr, DB, SdB, 1, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8350, DoOr, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op8358, DoOr, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op8360, DoOr, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op8368, DoOr, DW, SdW, 1, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op8370, DoOr, DW, SdW, 1, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Op8378, DoOr, DW, SdW, 1, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8390, DoOr, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op8398, DoOr, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op83a0, DoOr, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op83a8, DoOr, DL, SdL, 1, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Op83b0, DoOr, DL, SdL, 1, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Op83b8, DoOr, DL, SdL, 1, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op8400, DoOr, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4)
|
||||
Oper (Op8410, DoOr, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8)
|
||||
Oper (Op8418, DoOr, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8)
|
||||
Oper (Op8420, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12)
|
||||
Oper (Op8428, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12)
|
||||
Oper (Op8430, DoOr, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16)
|
||||
Oper (Op8438, DoOr, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8440, DoOr, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4)
|
||||
Oper (Op8450, DoOr, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8)
|
||||
Oper (Op8458, DoOr, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8)
|
||||
Oper (Op8460, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12)
|
||||
Oper (Op8468, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12)
|
||||
Oper (Op8470, DoOr, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16)
|
||||
Oper (Op8478, DoOr, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8480, DoOr, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8)
|
||||
Oper (Op8490, DoOr, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Op8498, DoOr, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Op84a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Op84a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20)
|
||||
Oper (Op84b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20)
|
||||
Oper (Op84b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op8510, DoOr, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op8518, DoOr, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op8520, DoOr, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op8528, DoOr, DB, SdB, 2, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op8530, DoOr, DB, SdB, 2, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Op8538, DoOr, DB, SdB, 2, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8550, DoOr, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op8558, DoOr, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op8560, DoOr, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op8568, DoOr, DW, SdW, 2, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op8570, DoOr, DW, SdW, 2, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Op8578, DoOr, DW, SdW, 2, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8590, DoOr, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op8598, DoOr, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op85a0, DoOr, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op85a8, DoOr, DL, SdL, 2, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Op85b0, DoOr, DL, SdL, 2, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Op85b8, DoOr, DL, SdL, 2, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op8600, DoOr, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4)
|
||||
Oper (Op8610, DoOr, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8)
|
||||
Oper (Op8618, DoOr, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8)
|
||||
Oper (Op8620, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12)
|
||||
Oper (Op8628, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12)
|
||||
Oper (Op8630, DoOr, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16)
|
||||
Oper (Op8638, DoOr, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8640, DoOr, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4)
|
||||
Oper (Op8650, DoOr, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8)
|
||||
Oper (Op8658, DoOr, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8)
|
||||
Oper (Op8660, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12)
|
||||
Oper (Op8668, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12)
|
||||
Oper (Op8670, DoOr, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16)
|
||||
Oper (Op8678, DoOr, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8680, DoOr, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8)
|
||||
Oper (Op8690, DoOr, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Op8698, DoOr, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Op86a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Op86a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20)
|
||||
Oper (Op86b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20)
|
||||
Oper (Op86b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op8710, DoOr, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op8718, DoOr, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op8720, DoOr, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op8728, DoOr, DB, SdB, 3, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op8730, DoOr, DB, SdB, 3, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Op8738, DoOr, DB, SdB, 3, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8750, DoOr, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op8758, DoOr, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op8760, DoOr, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op8768, DoOr, DW, SdW, 3, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op8770, DoOr, DW, SdW, 3, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Op8778, DoOr, DW, SdW, 3, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8790, DoOr, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op8798, DoOr, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op87a0, DoOr, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op87a8, DoOr, DL, SdL, 3, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Op87b0, DoOr, DL, SdL, 3, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Op87b8, DoOr, DL, SdL, 3, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op8800, DoOr, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4)
|
||||
Oper (Op8810, DoOr, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8)
|
||||
Oper (Op8818, DoOr, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8)
|
||||
Oper (Op8820, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12)
|
||||
Oper (Op8828, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12)
|
||||
Oper (Op8830, DoOr, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16)
|
||||
Oper (Op8838, DoOr, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8840, DoOr, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4)
|
||||
Oper (Op8850, DoOr, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8)
|
||||
Oper (Op8858, DoOr, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8)
|
||||
Oper (Op8860, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12)
|
||||
Oper (Op8868, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12)
|
||||
Oper (Op8870, DoOr, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16)
|
||||
Oper (Op8878, DoOr, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8880, DoOr, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8)
|
||||
Oper (Op8890, DoOr, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Op8898, DoOr, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Op88a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Op88a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20)
|
||||
Oper (Op88b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20)
|
||||
Oper (Op88b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op8910, DoOr, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op8918, DoOr, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op8920, DoOr, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op8928, DoOr, DB, SdB, 4, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op8930, DoOr, DB, SdB, 4, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Op8938, DoOr, DB, SdB, 4, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8950, DoOr, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op8958, DoOr, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op8960, DoOr, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op8968, DoOr, DW, SdW, 4, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op8970, DoOr, DW, SdW, 4, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Op8978, DoOr, DW, SdW, 4, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8990, DoOr, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op8998, DoOr, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op89a0, DoOr, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op89a8, DoOr, DL, SdL, 4, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Op89b0, DoOr, DL, SdL, 4, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Op89b8, DoOr, DL, SdL, 4, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op8a00, DoOr, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4)
|
||||
Oper (Op8a10, DoOr, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8)
|
||||
Oper (Op8a18, DoOr, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8)
|
||||
Oper (Op8a20, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12)
|
||||
Oper (Op8a28, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12)
|
||||
Oper (Op8a30, DoOr, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16)
|
||||
Oper (Op8a38, DoOr, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8a40, DoOr, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4)
|
||||
Oper (Op8a50, DoOr, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8)
|
||||
Oper (Op8a58, DoOr, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8)
|
||||
Oper (Op8a60, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12)
|
||||
Oper (Op8a68, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12)
|
||||
Oper (Op8a70, DoOr, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16)
|
||||
Oper (Op8a78, DoOr, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8a80, DoOr, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8)
|
||||
Oper (Op8a90, DoOr, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Op8a98, DoOr, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Op8aa0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Op8aa8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20)
|
||||
Oper (Op8ab0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20)
|
||||
Oper (Op8ab8, DoOr, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op8b10, DoOr, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op8b18, DoOr, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op8b20, DoOr, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op8b28, DoOr, DB, SdB, 5, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op8b30, DoOr, DB, SdB, 5, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Op8b38, DoOr, DB, SdB, 5, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8b50, DoOr, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op8b58, DoOr, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op8b60, DoOr, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op8b68, DoOr, DW, SdW, 5, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op8b70, DoOr, DW, SdW, 5, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Op8b78, DoOr, DW, SdW, 5, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8b90, DoOr, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op8b98, DoOr, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op8ba0, DoOr, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op8ba8, DoOr, DL, SdL, 5, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Op8bb0, DoOr, DL, SdL, 5, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Op8bb8, DoOr, DL, SdL, 5, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op8c00, DoOr, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4)
|
||||
Oper (Op8c10, DoOr, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8)
|
||||
Oper (Op8c18, DoOr, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8)
|
||||
Oper (Op8c20, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12)
|
||||
Oper (Op8c28, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12)
|
||||
Oper (Op8c30, DoOr, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16)
|
||||
Oper (Op8c38, DoOr, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8c40, DoOr, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4)
|
||||
Oper (Op8c50, DoOr, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8)
|
||||
Oper (Op8c58, DoOr, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8)
|
||||
Oper (Op8c60, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12)
|
||||
Oper (Op8c68, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12)
|
||||
Oper (Op8c70, DoOr, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16)
|
||||
Oper (Op8c78, DoOr, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8c80, DoOr, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8)
|
||||
Oper (Op8c90, DoOr, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Op8c98, DoOr, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Op8ca0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Op8ca8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20)
|
||||
Oper (Op8cb0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20)
|
||||
Oper (Op8cb8, DoOr, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op8d10, DoOr, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op8d18, DoOr, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op8d20, DoOr, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op8d28, DoOr, DB, SdB, 6, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op8d30, DoOr, DB, SdB, 6, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Op8d38, DoOr, DB, SdB, 6, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8d50, DoOr, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op8d58, DoOr, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op8d60, DoOr, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op8d68, DoOr, DW, SdW, 6, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op8d70, DoOr, DW, SdW, 6, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Op8d78, DoOr, DW, SdW, 6, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8d90, DoOr, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op8d98, DoOr, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op8da0, DoOr, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op8da8, DoOr, DL, SdL, 6, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Op8db0, DoOr, DL, SdL, 6, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Op8db8, DoOr, DL, SdL, 6, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op8e00, DoOr, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4)
|
||||
Oper (Op8e10, DoOr, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8)
|
||||
Oper (Op8e18, DoOr, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8)
|
||||
Oper (Op8e20, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12)
|
||||
Oper (Op8e28, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12)
|
||||
Oper (Op8e30, DoOr, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16)
|
||||
Oper (Op8e38, DoOr, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8e40, DoOr, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4)
|
||||
Oper (Op8e50, DoOr, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8)
|
||||
Oper (Op8e58, DoOr, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8)
|
||||
Oper (Op8e60, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12)
|
||||
Oper (Op8e68, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12)
|
||||
Oper (Op8e70, DoOr, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16)
|
||||
Oper (Op8e78, DoOr, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op8e80, DoOr, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8)
|
||||
Oper (Op8e90, DoOr, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Op8e98, DoOr, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Op8ea0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Op8ea8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20)
|
||||
Oper (Op8eb0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20)
|
||||
Oper (Op8eb8, DoOr, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op8f10, DoOr, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op8f18, DoOr, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op8f20, DoOr, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op8f28, DoOr, DB, SdB, 7, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op8f30, DoOr, DB, SdB, 7, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Op8f38, DoOr, DB, SdB, 7, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8f50, DoOr, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op8f58, DoOr, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op8f60, DoOr, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op8f68, DoOr, DW, SdW, 7, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op8f70, DoOr, DW, SdW, 7, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Op8f78, DoOr, DW, SdW, 7, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op8f90, DoOr, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op8f98, DoOr, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op8fa0, DoOr, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op8fa8, DoOr, DL, SdL, 7, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Op8fb0, DoOr, DL, SdL, 7, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Op8fb8, DoOr, DL, SdL, 7, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opb100, DoEor, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Opb110, DoEor, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opb118, DoEor, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opb120, DoEor, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opb128, DoEor, DB, SdB, 0, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opb130, DoEor, DB, SdB, 0, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opb138, DoEor, DB, SdB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opb140, DoEor, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Opb150, DoEor, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opb158, DoEor, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opb160, DoEor, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opb168, DoEor, DW, SdW, 0, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opb170, DoEor, DW, SdW, 0, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opb178, DoEor, DW, SdW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opb180, DoEor, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Opb190, DoEor, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opb198, DoEor, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opb1a0, DoEor, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opb1a8, DoEor, DL, SdL, 0, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opb1b0, DoEor, DL, SdL, 0, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opb1b8, DoEor, DL, SdL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opb300, DoEor, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Opb310, DoEor, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opb318, DoEor, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opb320, DoEor, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opb328, DoEor, DB, SdB, 1, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opb330, DoEor, DB, SdB, 1, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opb338, DoEor, DB, SdB, 1, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opb340, DoEor, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Opb350, DoEor, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opb358, DoEor, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opb360, DoEor, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opb368, DoEor, DW, SdW, 1, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opb370, DoEor, DW, SdW, 1, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opb378, DoEor, DW, SdW, 1, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opb380, DoEor, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Opb390, DoEor, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opb398, DoEor, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opb3a0, DoEor, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opb3a8, DoEor, DL, SdL, 1, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opb3b0, DoEor, DL, SdL, 1, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opb3b8, DoEor, DL, SdL, 1, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opb500, DoEor, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Opb510, DoEor, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opb518, DoEor, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opb520, DoEor, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opb528, DoEor, DB, SdB, 2, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opb530, DoEor, DB, SdB, 2, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opb538, DoEor, DB, SdB, 2, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opb540, DoEor, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Opb550, DoEor, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opb558, DoEor, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opb560, DoEor, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opb568, DoEor, DW, SdW, 2, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opb570, DoEor, DW, SdW, 2, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opb578, DoEor, DW, SdW, 2, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opb580, DoEor, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Opb590, DoEor, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opb598, DoEor, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opb5a0, DoEor, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opb5a8, DoEor, DL, SdL, 2, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opb5b0, DoEor, DL, SdL, 2, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opb5b8, DoEor, DL, SdL, 2, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opb700, DoEor, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Opb710, DoEor, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opb718, DoEor, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opb720, DoEor, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opb728, DoEor, DB, SdB, 3, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opb730, DoEor, DB, SdB, 3, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opb738, DoEor, DB, SdB, 3, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opb740, DoEor, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Opb750, DoEor, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opb758, DoEor, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opb760, DoEor, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opb768, DoEor, DW, SdW, 3, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opb770, DoEor, DW, SdW, 3, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opb778, DoEor, DW, SdW, 3, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opb780, DoEor, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Opb790, DoEor, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opb798, DoEor, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opb7a0, DoEor, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opb7a8, DoEor, DL, SdL, 3, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opb7b0, DoEor, DL, SdL, 3, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opb7b8, DoEor, DL, SdL, 3, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opb900, DoEor, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Opb910, DoEor, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opb918, DoEor, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opb920, DoEor, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opb928, DoEor, DB, SdB, 4, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opb930, DoEor, DB, SdB, 4, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opb938, DoEor, DB, SdB, 4, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opb940, DoEor, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Opb950, DoEor, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opb958, DoEor, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opb960, DoEor, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opb968, DoEor, DW, SdW, 4, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opb970, DoEor, DW, SdW, 4, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opb978, DoEor, DW, SdW, 4, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opb980, DoEor, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Opb990, DoEor, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opb998, DoEor, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opb9a0, DoEor, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opb9a8, DoEor, DL, SdL, 4, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opb9b0, DoEor, DL, SdL, 4, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opb9b8, DoEor, DL, SdL, 4, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opbb00, DoEor, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Opbb10, DoEor, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opbb18, DoEor, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opbb20, DoEor, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opbb28, DoEor, DB, SdB, 5, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opbb30, DoEor, DB, SdB, 5, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opbb38, DoEor, DB, SdB, 5, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opbb40, DoEor, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Opbb50, DoEor, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opbb58, DoEor, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opbb60, DoEor, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opbb68, DoEor, DW, SdW, 5, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opbb70, DoEor, DW, SdW, 5, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opbb78, DoEor, DW, SdW, 5, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opbb80, DoEor, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Opbb90, DoEor, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opbb98, DoEor, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opbba0, DoEor, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opbba8, DoEor, DL, SdL, 5, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opbbb0, DoEor, DL, SdL, 5, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opbbb8, DoEor, DL, SdL, 5, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opbd00, DoEor, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Opbd10, DoEor, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opbd18, DoEor, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opbd20, DoEor, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opbd28, DoEor, DB, SdB, 6, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opbd30, DoEor, DB, SdB, 6, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opbd38, DoEor, DB, SdB, 6, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opbd40, DoEor, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Opbd50, DoEor, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opbd58, DoEor, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opbd60, DoEor, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opbd68, DoEor, DW, SdW, 6, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opbd70, DoEor, DW, SdW, 6, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opbd78, DoEor, DW, SdW, 6, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opbd80, DoEor, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Opbd90, DoEor, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opbd98, DoEor, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opbda0, DoEor, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opbda8, DoEor, DL, SdL, 6, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opbdb0, DoEor, DL, SdL, 6, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opbdb8, DoEor, DL, SdL, 6, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Opbf00, DoEor, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Opbf10, DoEor, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Opbf18, DoEor, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Opbf20, DoEor, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Opbf28, DoEor, DB, SdB, 7, DB, DA, Cdai, ins7, GMB, SMB, 16)
|
||||
Oper (Opbf30, DoEor, DB, SdB, 7, DB, DA, Caix, ins7, GMB, SMB, 20)
|
||||
Oper (Opbf38, DoEor, DB, SdB, 7, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Opbf40, DoEor, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Opbf50, DoEor, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Opbf58, DoEor, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Opbf60, DoEor, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Opbf68, DoEor, DW, SdW, 7, DW, DA, Cdai, ins7, GMW, SMW, 16)
|
||||
Oper (Opbf70, DoEor, DW, SdW, 7, DW, DA, Caix, ins7, GMW, SMW, 20)
|
||||
Oper (Opbf78, DoEor, DW, SdW, 7, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Opbf80, DoEor, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Opbf90, DoEor, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Opbf98, DoEor, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Opbfa0, DoEor, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Opbfa8, DoEor, DL, SdL, 7, DL, DA, Cdai, ins7, GML, SML, 24)
|
||||
Oper (Opbfb0, DoEor, DL, SdL, 7, DL, DA, Caix, ins7, GML, SML, 28)
|
||||
Oper (Opbfb8, DoEor, DL, SdL, 7, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op0000, DoOr, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8)
|
||||
Oper (Op0010, DoOr, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16)
|
||||
Oper (Op0018, DoOr, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16)
|
||||
Oper (Op0020, DoOr, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20)
|
||||
Oper (Op0028, DoOr, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20)
|
||||
Oper (Op0030, DoOr, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24)
|
||||
OlogSR (Op0038, DoOr, DoOrSR, 0, DB, SimmB, DB, GMB, SMB, GCB, SCB, 20)
|
||||
Oper (Op0040, DoOr, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8)
|
||||
Oper (Op0050, DoOr, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16)
|
||||
Oper (Op0058, DoOr, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16)
|
||||
Oper (Op0060, DoOr, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20)
|
||||
Oper (Op0068, DoOr, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20)
|
||||
Oper (Op0070, DoOr, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24)
|
||||
OlogSR (Op0078, DoOr, DoOrSR, 1, DW, SimmW, DW, GMW, SMW, GCW, SCW, 20)
|
||||
Oper (Op0080, DoOr, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16)
|
||||
Oper (Op0090, DoOr, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28)
|
||||
Oper (Op0098, DoOr, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28)
|
||||
Oper (Op00a0, DoOr, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32)
|
||||
Oper (Op00a8, DoOr, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32)
|
||||
Oper (Op00b0, DoOr, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36)
|
||||
Oper (Op00b8, DoOr, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc)
|
||||
|
||||
Oper (Op0200, DoAnd, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8)
|
||||
Oper (Op0210, DoAnd, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16)
|
||||
Oper (Op0218, DoAnd, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16)
|
||||
Oper (Op0220, DoAnd, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20)
|
||||
Oper (Op0228, DoAnd, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20)
|
||||
Oper (Op0230, DoAnd, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24)
|
||||
OlogSR (Op0238, DoAnd, DoAndSR, 0, DB, SimmB, DB, GMB, SMB, GCB, SCB, 20)
|
||||
Oper (Op0240, DoAnd, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8)
|
||||
Oper (Op0250, DoAnd, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16)
|
||||
Oper (Op0258, DoAnd, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16)
|
||||
Oper (Op0260, DoAnd, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20)
|
||||
Oper (Op0268, DoAnd, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20)
|
||||
Oper (Op0270, DoAnd, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24)
|
||||
OlogSR (Op0278, DoAnd, DoAndSR, 1, DW, SimmW, DW, GMW, SMW, GCW, SCW, 20)
|
||||
Oper (Op0280, DoAnd, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16)
|
||||
Oper (Op0290, DoAnd, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28)
|
||||
Oper (Op0298, DoAnd, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28)
|
||||
Oper (Op02a0, DoAnd, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32)
|
||||
Oper (Op02a8, DoAnd, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32)
|
||||
Oper (Op02b0, DoAnd, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36)
|
||||
Oper (Op02b8, DoAnd, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc)
|
||||
|
||||
Oper (Op0a00, DoEor, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8)
|
||||
Oper (Op0a10, DoEor, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16)
|
||||
Oper (Op0a18, DoEor, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16)
|
||||
Oper (Op0a20, DoEor, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20)
|
||||
Oper (Op0a28, DoEor, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20)
|
||||
Oper (Op0a30, DoEor, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24)
|
||||
OlogSR (Op0a38, DoEor, DoEorSR, 0, DB, SimmB, DB, GMB, SMB, GCB, SCB, 20)
|
||||
Oper (Op0a40, DoEor, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8)
|
||||
Oper (Op0a50, DoEor, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16)
|
||||
Oper (Op0a58, DoEor, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16)
|
||||
Oper (Op0a60, DoEor, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20)
|
||||
Oper (Op0a68, DoEor, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20)
|
||||
Oper (Op0a70, DoEor, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24)
|
||||
OlogSR (Op0a78, DoEor, DoEorSR, 1, DW, SimmW, DW, GMW, SMW, GCW, SCW, 20)
|
||||
Oper (Op0a80, DoEor, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16)
|
||||
Oper (Op0a90, DoEor, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28)
|
||||
Oper (Op0a98, DoEor, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28)
|
||||
Oper (Op0aa0, DoEor, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32)
|
||||
Oper (Op0aa8, DoEor, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32)
|
||||
Oper (Op0ab0, DoEor, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36)
|
||||
Oper (Op0ab8, DoEor, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc)
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,864 @@
|
|||
/*
|
||||
* Castaway
|
||||
* (C) 1994 - 2002 Martin Doering, Joachim Hoenig
|
||||
*
|
||||
* $File$ - 68k shift instructions
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*
|
||||
* revision history
|
||||
* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring
|
||||
* 22.06.2002 JH V-flag after ASL was broken in some special cases.
|
||||
* 09.07.2002 JH ROXL/ROXR: X-flag not modified when shift count is 0.
|
||||
* 10.07.2002 JH other shift ops: X-flag not modified when shift count is 0.
|
||||
* 10.09.2002 JH Bugfix: ROXL.L
|
||||
* 15.09.2002 JH Minor SR/Bcc/Scc optimization. Fixed V-Flag for ASL.L.
|
||||
* Wrapped 68k operand types in typedefs.
|
||||
* 01.10.2002 JH Bugfix: -(Ax) and (Ax)+ addressing modes were swapped.
|
||||
* *** Many thx to olivencia@wanado.fr for finding this!! ***
|
||||
* 02.10.2002 JH SetV simplified for ASL.
|
||||
*/
|
||||
#ifndef PROTOH
|
||||
static char sccsid[] = "$Id: op68kshift.c,v 1.10 2002/10/05 08:25:08 jhoenig Exp $";
|
||||
#include "68000.h"
|
||||
#include "op68k.h"
|
||||
|
||||
#define addcycles cycles+=source<<1;
|
||||
|
||||
#define DoAslB(target,source) \
|
||||
source&=0x3f; \
|
||||
addcycles \
|
||||
if (source> 0) {\
|
||||
register uint32 cvnz=0;\
|
||||
register uint32 tgt=target<<source;\
|
||||
if (tgt&0x100) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\
|
||||
if ((tgt&0x80)!=(target&0x80)) cvnz+=Vflag;\
|
||||
target=tgt;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
} else {\
|
||||
ClrCVSetNZ(target);\
|
||||
}
|
||||
|
||||
#define DoAslW(target,source) \
|
||||
source&=0x3f; \
|
||||
addcycles \
|
||||
if (source> 0) {\
|
||||
register uint32 cvnz=0;\
|
||||
register uint32 tgt=target<<source;\
|
||||
if (tgt&0x10000) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\
|
||||
if ((tgt&0x8000)!=(target&0x8000)) cvnz+=Vflag;\
|
||||
target=tgt;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
} else {\
|
||||
ClrCVSetNZ(target);\
|
||||
}
|
||||
|
||||
#define DoAslL(target,source) \
|
||||
source&=0x3f; \
|
||||
addcycles \
|
||||
if (source>0) {\
|
||||
register uint32 cvnz=0;\
|
||||
register uint32 tgt=target<<(source-1);\
|
||||
if (tgt&0x80000000) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\
|
||||
tgt<<=1;\
|
||||
if ((((uint32)target)>>31)!=(tgt>>31)) cvnz+=Vflag;\
|
||||
target=tgt;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
} else {\
|
||||
ClrCVSetNZ(target);\
|
||||
}
|
||||
|
||||
#define DoAsr(target,source) \
|
||||
source&=0x3f; \
|
||||
addcycles \
|
||||
if (source>0) {\
|
||||
register uint32 cvnz=0;\
|
||||
target >>= source - 1;\
|
||||
if (target & 0x1) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\
|
||||
target >>= 1;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
} else {\
|
||||
ClrCVSetNZ(target);\
|
||||
}
|
||||
|
||||
#define DoAsrB(target,source) DoAsr(target,source)
|
||||
#define DoAsrW(target,source) DoAsr(target,source)
|
||||
#define DoAsrL(target,source) DoAsr(target,source)
|
||||
|
||||
#define DoLslB(target,source) \
|
||||
source&=0x3f; \
|
||||
addcycles \
|
||||
if (source>0) {\
|
||||
register uint32 cvnz=0;\
|
||||
register uint32 tgt=target<<source;\
|
||||
if (target&0x100) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\
|
||||
target=tgt;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
} else {\
|
||||
ClrCVSetNZ(target);\
|
||||
}
|
||||
|
||||
#define DoLslW(target,source) \
|
||||
source&=0x3f; \
|
||||
addcycles \
|
||||
if (source>0) {\
|
||||
register uint32 cvnz=0;\
|
||||
register uint32 tgt=target<<source;\
|
||||
if (target&0x10000) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\
|
||||
target=tgt;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
} else {\
|
||||
ClrCVSetNZ(target);\
|
||||
}
|
||||
|
||||
#define DoLslL(target,source) \
|
||||
source&=0x3f; \
|
||||
addcycles \
|
||||
if (source> 0) {\
|
||||
register uint32 cvnz=0;\
|
||||
target <<= source - 1;\
|
||||
if (target & 0x80000000) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\
|
||||
target <<= 1;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
} else {\
|
||||
ClrCVSetNZ(target);\
|
||||
}
|
||||
|
||||
#define DoLsr(target,source,type) \
|
||||
source&=0x3f; \
|
||||
addcycles \
|
||||
if (source> 0) {\
|
||||
register uint32 cvnz=0;\
|
||||
if (target&(1<<(source-1))) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\
|
||||
target=((type)target)>>source;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
} else {\
|
||||
ClrCVSetNZ(target);\
|
||||
}
|
||||
|
||||
#define DoLsrB(target,source) DoLsr(target,source,uint8)
|
||||
#define DoLsrW(target,source) DoLsr(target,source,uint16)
|
||||
#define DoLsrL(target,source) DoLsr(target,source,uint32)
|
||||
|
||||
|
||||
#define DoRoxlB(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
SetC(GetX());\
|
||||
} else {\
|
||||
register uint16 tgt1, tgt2;\
|
||||
source %= 9;\
|
||||
tgt1 = (uint8) target;\
|
||||
tgt1 |= (uint16) (GetX()) << 8;\
|
||||
tgt2 = tgt1;\
|
||||
tgt2 >>= (9 - source);\
|
||||
tgt1 <<= source;\
|
||||
tgt1 |= tgt2;\
|
||||
SetXC ((tgt1 >> 8) & 0x1);\
|
||||
target = tgt1;\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRoxlW(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
SetC(GetX());\
|
||||
} else {\
|
||||
register uint32 tgt1, tgt2;\
|
||||
source %= 17;\
|
||||
tgt1 = (uint16) target;\
|
||||
tgt1 |= (uint32) (GetX()) << 16;\
|
||||
tgt2 = tgt1;\
|
||||
tgt2 >>= (17 - source);\
|
||||
tgt1 <<= source;\
|
||||
tgt1 |= tgt2;\
|
||||
SetXC ((tgt1 >> 16) & 0x1);\
|
||||
target = tgt1;\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRoxlL(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
SetC(GetX());\
|
||||
} else {\
|
||||
register uint32 tgt1, tgt2;\
|
||||
source %= 33;\
|
||||
tgt2 = tgt1 = (uint32) target;\
|
||||
if (source != 0) {\
|
||||
tgt1 <<= 1;\
|
||||
tgt1 |= (uint32) (GetX());\
|
||||
tgt1 <<= (source - 1);\
|
||||
tgt2 >>= (32 - source);\
|
||||
SetXC (tgt2 & 0x1);\
|
||||
tgt2 >>= 1;\
|
||||
tgt1 |= tgt2;\
|
||||
target = tgt1;\
|
||||
}\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRoxrB(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
SetC(GetX());\
|
||||
} else {\
|
||||
register uint16 tgt1, tgt2;\
|
||||
source %= 9;\
|
||||
tgt1 = (uint8) target;\
|
||||
tgt1 |= (uint16) (GetX()) << 8;\
|
||||
tgt2 = tgt1;\
|
||||
tgt2 <<= (9 - source);\
|
||||
tgt1 >>= source;\
|
||||
tgt1 |= tgt2;\
|
||||
SetXC ((tgt1 >> 8) & 0x1);\
|
||||
target = tgt1;\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRoxrW(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
SetC(GetX());\
|
||||
} else {\
|
||||
register uint32 tgt1, tgt2;\
|
||||
source %= 17;\
|
||||
tgt1 = (uint16) target;\
|
||||
tgt1 |= (uint32) (GetX()) << 16;\
|
||||
tgt2 = tgt1;\
|
||||
tgt2 <<= (17 - source);\
|
||||
tgt1 >>= source;\
|
||||
tgt1 |= tgt2;\
|
||||
SetXC ((tgt1 >> 16) & 0x1);\
|
||||
target = tgt1;\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRoxrL(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
SetC(GetX());\
|
||||
} else {\
|
||||
register uint32 tgt1, tgt2;\
|
||||
source %= 33;\
|
||||
tgt2 = tgt1 = (uint32) target;\
|
||||
if (source != 0) {\
|
||||
tgt2 <<= 1;\
|
||||
tgt2 |= (uint32) (GetX());\
|
||||
tgt2 <<= (32 - source);\
|
||||
tgt1 >>= (source - 1);\
|
||||
SetXC (tgt1 & 0x1);\
|
||||
tgt1 >>= 1;\
|
||||
tgt1 |= tgt2;\
|
||||
target = tgt1;\
|
||||
}\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRolB(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
ForceC (0);\
|
||||
} else {\
|
||||
register uint8 tgt1, tgt2;\
|
||||
source &= 0x7;\
|
||||
tgt2 = tgt1 = target;\
|
||||
tgt2 >>= (8 - source);\
|
||||
tgt1 <<= source;\
|
||||
tgt1 |= tgt2;\
|
||||
SetC (tgt1 & 0x1);\
|
||||
target = tgt1;\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRolW(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
ForceC (0);\
|
||||
} else {\
|
||||
register uint16 tgt1, tgt2;\
|
||||
source &= 0xf;\
|
||||
tgt2 = tgt1 = target;\
|
||||
tgt2 >>= (16 - source);\
|
||||
tgt1 <<= source;\
|
||||
tgt1 |= tgt2;\
|
||||
SetC (tgt1 & 0x1);\
|
||||
target = tgt1;\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRolL(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
ForceC (0);\
|
||||
} else {\
|
||||
register uint32 tgt1, tgt2;\
|
||||
source &= 0x1f;\
|
||||
tgt2 = tgt1 = (uint32) target;\
|
||||
tgt2 >>= (32 - source);\
|
||||
tgt1 <<= source;\
|
||||
tgt1 |= tgt2;\
|
||||
SetC (tgt1 & 0x1);\
|
||||
target = tgt1;\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRorB(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
ForceC (0);\
|
||||
} else {\
|
||||
register uint8 tgt1, tgt2;\
|
||||
source &= 0x7;\
|
||||
tgt2 = tgt1 = target;\
|
||||
tgt2 <<= (8 - source);\
|
||||
tgt1 >>= source;\
|
||||
tgt1 |= tgt2;\
|
||||
SetC ((tgt1 >> 7) & 0x1);\
|
||||
target = tgt1;\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRorW(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
ForceC (0);\
|
||||
} else {\
|
||||
register uint16 tgt1, tgt2;\
|
||||
source &= 0xf;\
|
||||
tgt2 = tgt1 = target;\
|
||||
tgt2 <<= (16 - source);\
|
||||
tgt1 >>= source;\
|
||||
tgt1 |= tgt2;\
|
||||
SetC ((tgt1 >> 15) & 0x1);\
|
||||
target = tgt1;\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#define DoRorL(target,source) {\
|
||||
source &= 0x3f;\
|
||||
addcycles \
|
||||
ForceV (0);\
|
||||
if (source == 0) {\
|
||||
ForceC (0);\
|
||||
} else {\
|
||||
register uint32 tgt1, tgt2;\
|
||||
source &= 0x1f;\
|
||||
tgt2 = tgt1 = target;\
|
||||
tgt2 <<= (32 - source);\
|
||||
tgt1 >>= source;\
|
||||
tgt1 |= tgt2;\
|
||||
SetC ((tgt1 >> 31) & 0x1);\
|
||||
target = tgt1;\
|
||||
}\
|
||||
SetNZ (target);\
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
Oper (Ope000, DoAsrB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope008, DoLsrB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope010, DoRoxrB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope018, DoRorB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope020, DoAsrB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope028, DoLsrB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope030, DoRoxrB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope038, DoRorB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope040, DoAsrW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope048, DoLsrW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope050, DoRoxrW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope058, DoRorW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope060, DoAsrW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope068, DoLsrW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope070, DoRoxrW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope078, DoRorW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope080, DoAsrL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope088, DoLsrL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope090, DoRoxrL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope098, DoRorL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope0a0, DoAsrL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope0a8, DoLsrL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope0b0, DoRoxrL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope0b8, DoRorL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Ope100, DoAslB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope108, DoLslB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope110, DoRoxlB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope118, DoRolB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope120, DoAslB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope128, DoLslB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope130, DoRoxlB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope138, DoRolB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope140, DoAslW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope148, DoLslW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope150, DoRoxlW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope158, DoRolW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope160, DoAslW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope168, DoLslW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope170, DoRoxlW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope178, DoRolW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope180, DoAslL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope188, DoLslL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope190, DoRoxlL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope198, DoRolL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope1a0, DoAslL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope1a8, DoLslL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope1b0, DoRoxlL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope1b8, DoRolL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Ope200, DoAsrB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope208, DoLsrB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope210, DoRoxrB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope218, DoRorB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope220, DoAsrB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope228, DoLsrB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope230, DoRoxrB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope238, DoRorB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope240, DoAsrW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope248, DoLsrW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope250, DoRoxrW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope258, DoRorW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope260, DoAsrW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope268, DoLsrW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope270, DoRoxrW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope278, DoRorW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope280, DoAsrL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope288, DoLsrL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope290, DoRoxrL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope298, DoRorL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope2a0, DoAsrL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope2a8, DoLsrL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope2b0, DoRoxrL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope2b8, DoRorL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Ope300, DoAslB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope308, DoLslB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope310, DoRoxlB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope318, DoRolB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope320, DoAslB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope328, DoLslB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope330, DoRoxlB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope338, DoRolB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope340, DoAslW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope348, DoLslW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope350, DoRoxlW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope358, DoRolW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope360, DoAslW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope368, DoLslW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope370, DoRoxlW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope378, DoRolW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope380, DoAslL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope388, DoLslL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope390, DoRoxlL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope398, DoRolL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope3a0, DoAslL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope3a8, DoLslL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope3b0, DoRoxlL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope3b8, DoRolL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Ope400, DoAsrB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope408, DoLsrB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope410, DoRoxrB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope418, DoRorB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope420, DoAsrB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope428, DoLsrB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope430, DoRoxrB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope438, DoRorB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope440, DoAsrW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope448, DoLsrW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope450, DoRoxrW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope458, DoRorW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope460, DoAsrW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope468, DoLsrW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope470, DoRoxrW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope478, DoRorW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope480, DoAsrL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope488, DoLsrL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope490, DoRoxrL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope498, DoRorL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope4a0, DoAsrL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope4a8, DoLsrL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope4b0, DoRoxrL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope4b8, DoRorL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Ope500, DoAslB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope508, DoLslB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope510, DoRoxlB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope518, DoRolB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope520, DoAslB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope528, DoLslB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope530, DoRoxlB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope538, DoRolB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope540, DoAslW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope548, DoLslW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope550, DoRoxlW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope558, DoRolW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope560, DoAslW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope568, DoLslW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope570, DoRoxlW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope578, DoRolW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope580, DoAslL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope588, DoLslL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope590, DoRoxlL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope598, DoRolL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope5a0, DoAslL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope5a8, DoLslL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope5b0, DoRoxlL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope5b8, DoRolL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Ope600, DoAsrB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope608, DoLsrB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope610, DoRoxrB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope618, DoRorB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope620, DoAsrB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope628, DoLsrB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope630, DoRoxrB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope638, DoRorB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope640, DoAsrW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope648, DoLsrW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope650, DoRoxrW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope658, DoRorW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope660, DoAsrW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope668, DoLsrW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope670, DoRoxrW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope678, DoRorW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope680, DoAsrL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope688, DoLsrL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope690, DoRoxrL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope698, DoRorL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope6a0, DoAsrL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope6a8, DoLsrL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope6b0, DoRoxrL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope6b8, DoRorL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Ope700, DoAslB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope708, DoLslB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope710, DoRoxlB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope718, DoRolB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope720, DoAslB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope728, DoLslB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope730, DoRoxlB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope738, DoRolB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope740, DoAslW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope748, DoLslW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope750, DoRoxlW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope758, DoRolW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope760, DoAslW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope768, DoLslW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope770, DoRoxlW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope778, DoRolW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope780, DoAslL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope788, DoLslL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope790, DoRoxlL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope798, DoRolL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope7a0, DoAslL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope7a8, DoLslL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope7b0, DoRoxlL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope7b8, DoRolL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Ope800, DoAsrB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope808, DoLsrB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope810, DoRoxrB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope818, DoRorB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope820, DoAsrB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope828, DoLsrB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope830, DoRoxrB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope838, DoRorB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope840, DoAsrW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope848, DoLsrW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope850, DoRoxrW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope858, DoRorW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope860, DoAsrW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope868, DoLsrW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope870, DoRoxrW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope878, DoRorW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope880, DoAsrL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope888, DoLsrL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope890, DoRoxrL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope898, DoRorL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope8a0, DoAsrL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope8a8, DoLsrL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope8b0, DoRoxrL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope8b8, DoRorL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Ope900, DoAslB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope908, DoLslB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope910, DoRoxlB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope918, DoRolB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope920, DoAslB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope928, DoLslB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope930, DoRoxlB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope938, DoRolB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope940, DoAslW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope948, DoLslW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope950, DoRoxlW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope958, DoRolW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope960, DoAslW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope968, DoLslW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope970, DoRoxlW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope978, DoRolW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Ope980, DoAslL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope988, DoLslL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope990, DoRoxlL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope998, DoRolL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope9a0, DoAslL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope9a8, DoLslL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope9b0, DoRoxlL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Ope9b8, DoRolL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Opea00, DoAsrB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea08, DoLsrB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea10, DoRoxrB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea18, DoRorB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea20, DoAsrB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea28, DoLsrB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea30, DoRoxrB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea38, DoRorB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea40, DoAsrW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea48, DoLsrW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea50, DoRoxrW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea58, DoRorW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea60, DoAsrW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea68, DoLsrW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea70, DoRoxrW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea78, DoRorW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opea80, DoAsrL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opea88, DoLsrL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opea90, DoRoxrL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opea98, DoRorL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeaa0, DoAsrL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeaa8, DoLsrL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeab0, DoRoxrL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeab8, DoRorL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Opeb00, DoAslB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb08, DoLslB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb10, DoRoxlB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb18, DoRolB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb20, DoAslB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb28, DoLslB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb30, DoRoxlB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb38, DoRolB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb40, DoAslW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb48, DoLslW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb50, DoRoxlW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb58, DoRolW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb60, DoAslW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb68, DoLslW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb70, DoRoxlW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb78, DoRolW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opeb80, DoAslL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeb88, DoLslL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeb90, DoRoxlL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeb98, DoRolL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeba0, DoAslL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeba8, DoLslL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opebb0, DoRoxlL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opebb8, DoRolL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Opec00, DoAsrB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec08, DoLsrB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec10, DoRoxrB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec18, DoRorB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec20, DoAsrB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec28, DoLsrB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec30, DoRoxrB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec38, DoRorB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec40, DoAsrW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec48, DoLsrW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec50, DoRoxrW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec58, DoRorW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec60, DoAsrW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec68, DoLsrW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec70, DoRoxrW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec78, DoRorW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opec80, DoAsrL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opec88, DoLsrL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opec90, DoRoxrL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opec98, DoRorL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeca0, DoAsrL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeca8, DoLsrL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opecb0, DoRoxrL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opecb8, DoRorL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Oped00, DoAslB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped08, DoLslB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped10, DoRoxlB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped18, DoRolB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped20, DoAslB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped28, DoLslB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped30, DoRoxlB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped38, DoRolB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped40, DoAslW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped48, DoLslW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped50, DoRoxlW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped58, DoRolW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped60, DoAslW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped68, DoLslW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped70, DoRoxlW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped78, DoRolW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Oped80, DoAslL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Oped88, DoLslL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Oped90, DoRoxlL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Oped98, DoRolL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeda0, DoAslL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeda8, DoLslL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opedb0, DoRoxlL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opedb8, DoRolL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Opee00, DoAsrB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee08, DoLsrB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee10, DoRoxrB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee18, DoRorB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee20, DoAsrB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee28, DoLsrB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee30, DoRoxrB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee38, DoRorB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee40, DoAsrW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee48, DoLsrW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee50, DoRoxrW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee58, DoRorW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee60, DoAsrW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee68, DoLsrW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee70, DoRoxrW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee78, DoRorW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opee80, DoAsrL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opee88, DoLsrL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opee90, DoRoxrL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opee98, DoRorL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeea0, DoAsrL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeea8, DoLsrL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeeb0, DoRoxrL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opeeb8, DoRorL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Opef00, DoAslB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef08, DoLslB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef10, DoRoxlB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef18, DoRolB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef20, DoAslB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef28, DoLslB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef30, DoRoxlB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef38, DoRolB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef40, DoAslW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef48, DoLslW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef50, DoRoxlW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef58, DoRolW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef60, DoAslW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef68, DoLslW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef70, DoRoxlW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef78, DoRolW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc)
|
||||
Oper (Opef80, DoAslL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opef88, DoLslL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opef90, DoRoxlL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opef98, DoRolL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opefa0, DoAslL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opefa8, DoLslL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opefb0, DoRoxlL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
Oper (Opefb8, DoRolL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc)
|
||||
|
||||
Oper (Ope0d0, DoAsrW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Ope0d8, DoAsrW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Ope0e0, DoAsrW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Ope0e8, DoAsrW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Ope0f0, DoAsrW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Ope0f8, DoAsrW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Ope1d0, DoAslW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Ope1d8, DoAslW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Ope1e0, DoAslW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Ope1e8, DoAslW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Ope1f0, DoAslW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Ope1f8, DoAslW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Ope2d0, DoLsrW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Ope2d8, DoLsrW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Ope2e0, DoLsrW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Ope2e8, DoLsrW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Ope2f0, DoLsrW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Ope2f8, DoLsrW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Ope3d0, DoLslW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Ope3d8, DoLslW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Ope3e0, DoLslW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Ope3e8, DoLslW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Ope3f0, DoLslW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Ope3f8, DoLslW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Ope4d0, DoRoxrW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Ope4d8, DoRoxrW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Ope4e0, DoRoxrW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Ope4e8, DoRoxrW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Ope4f0, DoRoxrW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Ope4f8, DoRoxrW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Ope5d0, DoRoxlW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Ope5d8, DoRoxlW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Ope5e0, DoRoxlW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Ope5e8, DoRoxlW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Ope5f0, DoRoxlW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Ope5f8, DoRoxlW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Ope6d0, DoRorW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Ope6d8, DoRorW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Ope6e0, DoRorW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Ope6e8, DoRorW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Ope6f0, DoRorW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Ope6f8, DoRorW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Ope7d0, DoRolW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Ope7d8, DoRolW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Ope7e0, DoRolW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Ope7e8, DoRolW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Ope7f0, DoRolW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Ope7f8, DoRolW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
|
||||
|
|
@ -0,0 +1,810 @@
|
|||
/*
|
||||
* Castaway
|
||||
* (C) 1994 - 2002 Martin Doering, Joachim Hoenig
|
||||
*
|
||||
* $File$ - 68k subtract instructions
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*
|
||||
* revision history
|
||||
* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring
|
||||
* 10.07.2002 JH Fixed Z-Flag for SUBX
|
||||
* 08.10.2002 JH Fixed Z-Flag for ADD.B 0x80+0x80 and Add.W 0x8000+0x8000.
|
||||
*/
|
||||
#ifndef PROTOH
|
||||
static char sccsid[] = "$Id: op68ksub.c,v 1.3 2002/10/08 00:18:02 jhoenig Exp $";
|
||||
#include "68000.h"
|
||||
#include "op68k.h"
|
||||
|
||||
/*
|
||||
* Opfuncs.
|
||||
*/
|
||||
|
||||
#define DoSubB(target,source) \
|
||||
{register int32 tgt, cvnz=0;\
|
||||
tgt = target - source;\
|
||||
if ((uint32) source > (uint32) target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\
|
||||
target = tgt;\
|
||||
if (tgt!=target) cvnz+=Vflag;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
};
|
||||
|
||||
#define DoSubW(target,source) \
|
||||
{register int32 tgt, cvnz=0;\
|
||||
tgt = target - source;\
|
||||
if ((uint32) source > (uint32) target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\
|
||||
target = tgt;\
|
||||
if (tgt!=target) cvnz+=Vflag;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
};
|
||||
|
||||
#define DoSubL(target,source) \
|
||||
/* Overflow precondition: source has different sign */\
|
||||
{register int32 precon=(target>>31)-(source>>31), cvnz=0;\
|
||||
if ((uint32) source > (uint32) target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\
|
||||
target -= source;\
|
||||
/* target and source now have same sign: overflow! */\
|
||||
if (precon && (target>>31)==(source>>31)) cvnz+=Vflag;\
|
||||
if (target==0) cvnz+=Zflag;\
|
||||
else if (target<0) cvnz+=Nflag;\
|
||||
ForceCVNZ(cvnz);\
|
||||
};
|
||||
|
||||
#define DoSuba(target,source) target -= source;
|
||||
|
||||
#define DoSubx(target,source) \
|
||||
/* Overflow precondition: source has different sign */\
|
||||
{register int32 precon=(target>>31)-(source>>31);\
|
||||
if (GetX ()) {\
|
||||
SetXC ((uint32) source >= (uint32) target);\
|
||||
target -= source;\
|
||||
target -= 1;\
|
||||
} else {\
|
||||
SetXC ((uint32) source > (uint32) target);\
|
||||
target -= source;\
|
||||
}\
|
||||
/* target and source now have same sign: overflow! */\
|
||||
SetV(precon && (target>>31)==(source>>31));\
|
||||
ZeroZ(target!=0);\
|
||||
SetN(target < 0);};
|
||||
#endif
|
||||
|
||||
|
||||
Oper (Op9000, DoSubB, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4)
|
||||
Oper (Op9010, DoSubB, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8)
|
||||
Oper (Op9018, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8)
|
||||
Oper (Op9020, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12)
|
||||
Oper (Op9028, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12)
|
||||
Oper (Op9030, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16)
|
||||
Oper (Op9038, DoSubB, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9040, DoSubW, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4)
|
||||
Oper (Op9048, DoSubW, DW, SaW, ins7, DW, DR, Cd, 0, GRW, SRW, 4)
|
||||
Oper (Op9050, DoSubW, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8)
|
||||
Oper (Op9058, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8)
|
||||
Oper (Op9060, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12)
|
||||
Oper (Op9068, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12)
|
||||
Oper (Op9070, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16)
|
||||
Oper (Op9078, DoSubW, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9080, DoSubL, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8)
|
||||
Oper (Op9088, DoSubL, DL, SaL, ins7, DL, DR, Cd, 0, GRL, SRL, 8)
|
||||
Oper (Op9090, DoSubL, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Op9098, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Op90a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16)
|
||||
Oper (Op90a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20)
|
||||
Oper (Op90b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20)
|
||||
Oper (Op90b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Op90c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 0, GRL, SRL, 8)
|
||||
Oper (Op90c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 0, GRL, SRL, 8)
|
||||
Oper (Op90d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 0, GRL, SRL, 12)
|
||||
Oper (Op90d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 0, GRL, SRL, 12)
|
||||
Oper (Op90e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16)
|
||||
Oper (Op90e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16)
|
||||
Oper (Op90f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 0, GRL, SRL, 20)
|
||||
Oper (Op90f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Op9100, DoSubx, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4)
|
||||
Oper (Op9108, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20)
|
||||
Oper (Op9110, DoSubB, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op9118, DoSubB, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op9120, DoSubB, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op9128, DoSubB, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op9130, DoSubB, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op9138, DoSubB, DB, SdB, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9140, DoSubx, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4)
|
||||
Oper (Op9148, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 0, GMW, SMW, 20)
|
||||
Oper (Op9150, DoSubW, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op9158, DoSubW, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op9160, DoSubW, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op9168, DoSubW, DW, SdW, 0, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op9170, DoSubW, DW, SdW, 0, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op9178, DoSubW, DW, SdW, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9180, DoSubx, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8)
|
||||
Oper (Op9188, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 0, GML, SML, 32)
|
||||
Oper (Op9190, DoSubL, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op9198, DoSubL, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op91a0, DoSubL, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op91a8, DoSubL, DL, SdL, 0, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op91b0, DoSubL, DL, SdL, 0, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op91b8, DoSubL, DL, SdL, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Op91c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 0, GRL, SRL, 8)
|
||||
Oper (Op91c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 0, GRL, SRL, 8)
|
||||
Oper (Op91d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 0, GRL, SRL, 16)
|
||||
Oper (Op91d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 0, GRL, SRL, 16)
|
||||
Oper (Op91e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 16)
|
||||
Oper (Op91e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 20)
|
||||
Oper (Op91f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 0, GRL, SRL, 20)
|
||||
Oper (Op91f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op9200, DoSubB, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4)
|
||||
Oper (Op9210, DoSubB, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8)
|
||||
Oper (Op9218, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8)
|
||||
Oper (Op9220, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12)
|
||||
Oper (Op9228, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12)
|
||||
Oper (Op9230, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16)
|
||||
Oper (Op9238, DoSubB, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9240, DoSubW, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4)
|
||||
Oper (Op9248, DoSubW, DW, SaW, ins7, DW, DR, Cd, 1, GRW, SRW, 4)
|
||||
Oper (Op9250, DoSubW, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8)
|
||||
Oper (Op9258, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8)
|
||||
Oper (Op9260, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12)
|
||||
Oper (Op9268, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12)
|
||||
Oper (Op9270, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16)
|
||||
Oper (Op9278, DoSubW, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9280, DoSubL, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8)
|
||||
Oper (Op9288, DoSubL, DL, SaL, ins7, DL, DR, Cd, 1, GRL, SRL, 8)
|
||||
Oper (Op9290, DoSubL, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Op9298, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Op92a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16)
|
||||
Oper (Op92a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20)
|
||||
Oper (Op92b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20)
|
||||
Oper (Op92b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Op92c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 1, GRL, SRL, 8)
|
||||
Oper (Op92c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 1, GRL, SRL, 8)
|
||||
Oper (Op92d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 1, GRL, SRL, 12)
|
||||
Oper (Op92d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 1, GRL, SRL, 12)
|
||||
Oper (Op92e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16)
|
||||
Oper (Op92e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16)
|
||||
Oper (Op92f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 1, GRL, SRL, 20)
|
||||
Oper (Op92f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Op9300, DoSubx, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4)
|
||||
Oper (Op9308, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20)
|
||||
Oper (Op9310, DoSubB, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op9318, DoSubB, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op9320, DoSubB, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op9328, DoSubB, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op9330, DoSubB, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op9338, DoSubB, DB, SdB, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9340, DoSubx, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4)
|
||||
Oper (Op9348, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 1, GMW, SMW, 20)
|
||||
Oper (Op9350, DoSubW, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op9358, DoSubW, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op9360, DoSubW, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op9368, DoSubW, DW, SdW, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op9370, DoSubW, DW, SdW, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op9378, DoSubW, DW, SdW, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9380, DoSubx, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8)
|
||||
Oper (Op9388, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 1, GML, SML, 32)
|
||||
Oper (Op9390, DoSubL, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op9398, DoSubL, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op93a0, DoSubL, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op93a8, DoSubL, DL, SdL, 1, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op93b0, DoSubL, DL, SdL, 1, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op93b8, DoSubL, DL, SdL, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Op93c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 1, GRL, SRL, 8)
|
||||
Oper (Op93c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 1, GRL, SRL, 8)
|
||||
Oper (Op93d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 1, GRL, SRL, 16)
|
||||
Oper (Op93d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 1, GRL, SRL, 16)
|
||||
Oper (Op93e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 16)
|
||||
Oper (Op93e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 20)
|
||||
Oper (Op93f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 1, GRL, SRL, 20)
|
||||
Oper (Op93f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op9400, DoSubB, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4)
|
||||
Oper (Op9410, DoSubB, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8)
|
||||
Oper (Op9418, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8)
|
||||
Oper (Op9420, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12)
|
||||
Oper (Op9428, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12)
|
||||
Oper (Op9430, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16)
|
||||
Oper (Op9438, DoSubB, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9440, DoSubW, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4)
|
||||
Oper (Op9448, DoSubW, DW, SaW, ins7, DW, DR, Cd, 2, GRW, SRW, 4)
|
||||
Oper (Op9450, DoSubW, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8)
|
||||
Oper (Op9458, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8)
|
||||
Oper (Op9460, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12)
|
||||
Oper (Op9468, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12)
|
||||
Oper (Op9470, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16)
|
||||
Oper (Op9478, DoSubW, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9480, DoSubL, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8)
|
||||
Oper (Op9488, DoSubL, DL, SaL, ins7, DL, DR, Cd, 2, GRL, SRL, 8)
|
||||
Oper (Op9490, DoSubL, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Op9498, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Op94a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16)
|
||||
Oper (Op94a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20)
|
||||
Oper (Op94b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20)
|
||||
Oper (Op94b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Op94c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 2, GRL, SRL, 8)
|
||||
Oper (Op94c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 2, GRL, SRL, 8)
|
||||
Oper (Op94d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 2, GRL, SRL, 12)
|
||||
Oper (Op94d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 2, GRL, SRL, 12)
|
||||
Oper (Op94e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16)
|
||||
Oper (Op94e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16)
|
||||
Oper (Op94f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 2, GRL, SRL, 20)
|
||||
Oper (Op94f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Op9500, DoSubx, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4)
|
||||
Oper (Op9508, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20)
|
||||
Oper (Op9510, DoSubB, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op9518, DoSubB, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op9520, DoSubB, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op9528, DoSubB, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op9530, DoSubB, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op9538, DoSubB, DB, SdB, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9540, DoSubx, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4)
|
||||
Oper (Op9548, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 2, GMW, SMW, 20)
|
||||
Oper (Op9550, DoSubW, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op9558, DoSubW, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op9560, DoSubW, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op9568, DoSubW, DW, SdW, 2, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op9570, DoSubW, DW, SdW, 2, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op9578, DoSubW, DW, SdW, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9580, DoSubx, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8)
|
||||
Oper (Op9588, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 2, GML, SML, 32)
|
||||
Oper (Op9590, DoSubL, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op9598, DoSubL, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op95a0, DoSubL, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op95a8, DoSubL, DL, SdL, 2, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op95b0, DoSubL, DL, SdL, 2, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op95b8, DoSubL, DL, SdL, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Op95c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 2, GRL, SRL, 8)
|
||||
Oper (Op95c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 2, GRL, SRL, 8)
|
||||
Oper (Op95d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 2, GRL, SRL, 16)
|
||||
Oper (Op95d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 2, GRL, SRL, 16)
|
||||
Oper (Op95e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 16)
|
||||
Oper (Op95e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 20)
|
||||
Oper (Op95f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 2, GRL, SRL, 20)
|
||||
Oper (Op95f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op9600, DoSubB, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4)
|
||||
Oper (Op9610, DoSubB, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8)
|
||||
Oper (Op9618, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8)
|
||||
Oper (Op9620, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12)
|
||||
Oper (Op9628, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12)
|
||||
Oper (Op9630, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16)
|
||||
Oper (Op9638, DoSubB, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9640, DoSubW, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4)
|
||||
Oper (Op9648, DoSubW, DW, SaW, ins7, DW, DR, Cd, 3, GRW, SRW, 4)
|
||||
Oper (Op9650, DoSubW, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8)
|
||||
Oper (Op9658, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8)
|
||||
Oper (Op9660, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12)
|
||||
Oper (Op9668, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12)
|
||||
Oper (Op9670, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16)
|
||||
Oper (Op9678, DoSubW, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9680, DoSubL, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8)
|
||||
Oper (Op9688, DoSubL, DL, SaL, ins7, DL, DR, Cd, 3, GRL, SRL, 8)
|
||||
Oper (Op9690, DoSubL, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Op9698, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Op96a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16)
|
||||
Oper (Op96a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20)
|
||||
Oper (Op96b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20)
|
||||
Oper (Op96b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Op96c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 3, GRL, SRL, 8)
|
||||
Oper (Op96c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 3, GRL, SRL, 8)
|
||||
Oper (Op96d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 3, GRL, SRL, 12)
|
||||
Oper (Op96d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 3, GRL, SRL, 12)
|
||||
Oper (Op96e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16)
|
||||
Oper (Op96e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16)
|
||||
Oper (Op96f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 3, GRL, SRL, 20)
|
||||
Oper (Op96f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Op9700, DoSubx, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4)
|
||||
Oper (Op9708, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20)
|
||||
Oper (Op9710, DoSubB, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op9718, DoSubB, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op9720, DoSubB, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op9728, DoSubB, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op9730, DoSubB, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op9738, DoSubB, DB, SdB, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9740, DoSubx, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4)
|
||||
Oper (Op9748, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 3, GMW, SMW, 20)
|
||||
Oper (Op9750, DoSubW, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op9758, DoSubW, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op9760, DoSubW, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op9768, DoSubW, DW, SdW, 3, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op9770, DoSubW, DW, SdW, 3, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op9778, DoSubW, DW, SdW, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9780, DoSubx, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8)
|
||||
Oper (Op9788, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 3, GML, SML, 32)
|
||||
Oper (Op9790, DoSubL, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op9798, DoSubL, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op97a0, DoSubL, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op97a8, DoSubL, DL, SdL, 3, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op97b0, DoSubL, DL, SdL, 3, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op97b8, DoSubL, DL, SdL, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Op97c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 3, GRL, SRL, 8)
|
||||
Oper (Op97c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 3, GRL, SRL, 8)
|
||||
Oper (Op97d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 3, GRL, SRL, 16)
|
||||
Oper (Op97d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 3, GRL, SRL, 16)
|
||||
Oper (Op97e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 16)
|
||||
Oper (Op97e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 20)
|
||||
Oper (Op97f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 3, GRL, SRL, 20)
|
||||
Oper (Op97f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op9800, DoSubB, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4)
|
||||
Oper (Op9810, DoSubB, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8)
|
||||
Oper (Op9818, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8)
|
||||
Oper (Op9820, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12)
|
||||
Oper (Op9828, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12)
|
||||
Oper (Op9830, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16)
|
||||
Oper (Op9838, DoSubB, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9840, DoSubW, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4)
|
||||
Oper (Op9848, DoSubW, DW, SaW, ins7, DW, DR, Cd, 4, GRW, SRW, 4)
|
||||
Oper (Op9850, DoSubW, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8)
|
||||
Oper (Op9858, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8)
|
||||
Oper (Op9860, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12)
|
||||
Oper (Op9868, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12)
|
||||
Oper (Op9870, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16)
|
||||
Oper (Op9878, DoSubW, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9880, DoSubL, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8)
|
||||
Oper (Op9888, DoSubL, DL, SaL, ins7, DL, DR, Cd, 4, GRL, SRL, 8)
|
||||
Oper (Op9890, DoSubL, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Op9898, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Op98a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16)
|
||||
Oper (Op98a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20)
|
||||
Oper (Op98b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20)
|
||||
Oper (Op98b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Op98c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 4, GRL, SRL, 8)
|
||||
Oper (Op98c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 4, GRL, SRL, 8)
|
||||
Oper (Op98d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 4, GRL, SRL, 12)
|
||||
Oper (Op98d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 4, GRL, SRL, 12)
|
||||
Oper (Op98e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16)
|
||||
Oper (Op98e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16)
|
||||
Oper (Op98f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 4, GRL, SRL, 20)
|
||||
Oper (Op98f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Op9900, DoSubx, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4)
|
||||
Oper (Op9908, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20)
|
||||
Oper (Op9910, DoSubB, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op9918, DoSubB, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op9920, DoSubB, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op9928, DoSubB, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op9930, DoSubB, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op9938, DoSubB, DB, SdB, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9940, DoSubx, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4)
|
||||
Oper (Op9948, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 4, GMW, SMW, 20)
|
||||
Oper (Op9950, DoSubW, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op9958, DoSubW, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op9960, DoSubW, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op9968, DoSubW, DW, SdW, 4, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op9970, DoSubW, DW, SdW, 4, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op9978, DoSubW, DW, SdW, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9980, DoSubx, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8)
|
||||
Oper (Op9988, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 4, GML, SML, 32)
|
||||
Oper (Op9990, DoSubL, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op9998, DoSubL, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op99a0, DoSubL, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op99a8, DoSubL, DL, SdL, 4, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op99b0, DoSubL, DL, SdL, 4, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op99b8, DoSubL, DL, SdL, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Op99c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 4, GRL, SRL, 8)
|
||||
Oper (Op99c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 4, GRL, SRL, 8)
|
||||
Oper (Op99d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 4, GRL, SRL, 16)
|
||||
Oper (Op99d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 4, GRL, SRL, 16)
|
||||
Oper (Op99e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 16)
|
||||
Oper (Op99e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 20)
|
||||
Oper (Op99f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 4, GRL, SRL, 20)
|
||||
Oper (Op99f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op9a00, DoSubB, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4)
|
||||
Oper (Op9a10, DoSubB, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8)
|
||||
Oper (Op9a18, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8)
|
||||
Oper (Op9a20, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12)
|
||||
Oper (Op9a28, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12)
|
||||
Oper (Op9a30, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16)
|
||||
Oper (Op9a38, DoSubB, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9a40, DoSubW, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4)
|
||||
Oper (Op9a48, DoSubW, DW, SaW, ins7, DW, DR, Cd, 5, GRW, SRW, 4)
|
||||
Oper (Op9a50, DoSubW, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8)
|
||||
Oper (Op9a58, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8)
|
||||
Oper (Op9a60, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12)
|
||||
Oper (Op9a68, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12)
|
||||
Oper (Op9a70, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16)
|
||||
Oper (Op9a78, DoSubW, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9a80, DoSubL, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8)
|
||||
Oper (Op9a88, DoSubL, DL, SaL, ins7, DL, DR, Cd, 5, GRL, SRL, 8)
|
||||
Oper (Op9a90, DoSubL, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Op9a98, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Op9aa0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16)
|
||||
Oper (Op9aa8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20)
|
||||
Oper (Op9ab0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20)
|
||||
Oper (Op9ab8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9ac0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 5, GRL, SRL, 8)
|
||||
Oper (Op9ac8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 5, GRL, SRL, 8)
|
||||
Oper (Op9ad0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 5, GRL, SRL, 12)
|
||||
Oper (Op9ad8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 5, GRL, SRL, 12)
|
||||
Oper (Op9ae0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16)
|
||||
Oper (Op9ae8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16)
|
||||
Oper (Op9af0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 5, GRL, SRL, 20)
|
||||
Oper (Op9af8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Op9b00, DoSubx, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4)
|
||||
Oper (Op9b08, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20)
|
||||
Oper (Op9b10, DoSubB, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op9b18, DoSubB, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op9b20, DoSubB, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op9b28, DoSubB, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op9b30, DoSubB, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op9b38, DoSubB, DB, SdB, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9b40, DoSubx, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4)
|
||||
Oper (Op9b48, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 5, GMW, SMW, 20)
|
||||
Oper (Op9b50, DoSubW, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op9b58, DoSubW, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op9b60, DoSubW, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op9b68, DoSubW, DW, SdW, 5, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op9b70, DoSubW, DW, SdW, 5, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op9b78, DoSubW, DW, SdW, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9b80, DoSubx, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8)
|
||||
Oper (Op9b88, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 5, GML, SML, 32)
|
||||
Oper (Op9b90, DoSubL, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op9b98, DoSubL, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op9ba0, DoSubL, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op9ba8, DoSubL, DL, SdL, 5, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op9bb0, DoSubL, DL, SdL, 5, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op9bb8, DoSubL, DL, SdL, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Op9bc0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 5, GRL, SRL, 8)
|
||||
Oper (Op9bc8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 5, GRL, SRL, 8)
|
||||
Oper (Op9bd0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 5, GRL, SRL, 16)
|
||||
Oper (Op9bd8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 5, GRL, SRL, 16)
|
||||
Oper (Op9be0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 16)
|
||||
Oper (Op9be8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 20)
|
||||
Oper (Op9bf0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 5, GRL, SRL, 20)
|
||||
Oper (Op9bf8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op9c00, DoSubB, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4)
|
||||
Oper (Op9c10, DoSubB, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8)
|
||||
Oper (Op9c18, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8)
|
||||
Oper (Op9c20, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12)
|
||||
Oper (Op9c28, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12)
|
||||
Oper (Op9c30, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16)
|
||||
Oper (Op9c38, DoSubB, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9c40, DoSubW, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4)
|
||||
Oper (Op9c48, DoSubW, DW, SaW, ins7, DW, DR, Cd, 6, GRW, SRW, 4)
|
||||
Oper (Op9c50, DoSubW, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8)
|
||||
Oper (Op9c58, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8)
|
||||
Oper (Op9c60, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12)
|
||||
Oper (Op9c68, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12)
|
||||
Oper (Op9c70, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16)
|
||||
Oper (Op9c78, DoSubW, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9c80, DoSubL, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8)
|
||||
Oper (Op9c88, DoSubL, DL, SaL, ins7, DL, DR, Cd, 6, GRL, SRL, 8)
|
||||
Oper (Op9c90, DoSubL, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Op9c98, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Op9ca0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16)
|
||||
Oper (Op9ca8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20)
|
||||
Oper (Op9cb0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20)
|
||||
Oper (Op9cb8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9cc0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 6, GRL, SRL, 8)
|
||||
Oper (Op9cc8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 6, GRL, SRL, 8)
|
||||
Oper (Op9cd0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 6, GRL, SRL, 12)
|
||||
Oper (Op9cd8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 6, GRL, SRL, 12)
|
||||
Oper (Op9ce0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16)
|
||||
Oper (Op9ce8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16)
|
||||
Oper (Op9cf0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 6, GRL, SRL, 20)
|
||||
Oper (Op9cf8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Op9d00, DoSubx, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4)
|
||||
Oper (Op9d08, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20)
|
||||
Oper (Op9d10, DoSubB, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op9d18, DoSubB, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op9d20, DoSubB, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op9d28, DoSubB, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op9d30, DoSubB, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op9d38, DoSubB, DB, SdB, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9d40, DoSubx, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4)
|
||||
Oper (Op9d48, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 6, GMW, SMW, 20)
|
||||
Oper (Op9d50, DoSubW, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op9d58, DoSubW, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op9d60, DoSubW, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op9d68, DoSubW, DW, SdW, 6, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op9d70, DoSubW, DW, SdW, 6, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op9d78, DoSubW, DW, SdW, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9d80, DoSubx, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8)
|
||||
Oper (Op9d88, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 6, GML, SML, 32)
|
||||
Oper (Op9d90, DoSubL, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op9d98, DoSubL, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op9da0, DoSubL, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op9da8, DoSubL, DL, SdL, 6, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op9db0, DoSubL, DL, SdL, 6, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op9db8, DoSubL, DL, SdL, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Op9dc0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 6, GRL, SRL, 8)
|
||||
Oper (Op9dc8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 6, GRL, SRL, 8)
|
||||
Oper (Op9dd0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 6, GRL, SRL, 16)
|
||||
Oper (Op9dd8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 6, GRL, SRL, 16)
|
||||
Oper (Op9de0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 16)
|
||||
Oper (Op9de8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 20)
|
||||
Oper (Op9df0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 6, GRL, SRL, 20)
|
||||
Oper (Op9df8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op9e00, DoSubB, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4)
|
||||
Oper (Op9e10, DoSubB, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8)
|
||||
Oper (Op9e18, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8)
|
||||
Oper (Op9e20, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12)
|
||||
Oper (Op9e28, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12)
|
||||
Oper (Op9e30, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16)
|
||||
Oper (Op9e38, DoSubB, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9e40, DoSubW, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4)
|
||||
Oper (Op9e48, DoSubW, DW, SaW, ins7, DW, DR, Cd, 7, GRW, SRW, 4)
|
||||
Oper (Op9e50, DoSubW, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8)
|
||||
Oper (Op9e58, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8)
|
||||
Oper (Op9e60, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12)
|
||||
Oper (Op9e68, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12)
|
||||
Oper (Op9e70, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16)
|
||||
Oper (Op9e78, DoSubW, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc)
|
||||
Oper (Op9e80, DoSubL, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8)
|
||||
Oper (Op9e88, DoSubL, DL, SaL, ins7, DL, DR, Cd, 7, GRL, SRL, 8)
|
||||
Oper (Op9e90, DoSubL, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Op9e98, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Op9ea0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16)
|
||||
Oper (Op9ea8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20)
|
||||
Oper (Op9eb0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20)
|
||||
Oper (Op9eb8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9ec0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 7, GRL, SRL, 8)
|
||||
Oper (Op9ec8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 7, GRL, SRL, 8)
|
||||
Oper (Op9ed0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 7, GRL, SRL, 12)
|
||||
Oper (Op9ed8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 7, GRL, SRL, 12)
|
||||
Oper (Op9ee0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16)
|
||||
Oper (Op9ee8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16)
|
||||
Oper (Op9ef0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 7, GRL, SRL, 20)
|
||||
Oper (Op9ef8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+15)&0xfffffffc)
|
||||
|
||||
Oper (Op9f00, DoSubx, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4)
|
||||
Oper (Op9f08, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB15, 7, GMB, SMB, 20)
|
||||
Oper (Op9f10, DoSubB, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op9f18, DoSubB, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op9f20, DoSubB, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op9f28, DoSubB, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op9f30, DoSubB, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op9f38, DoSubB, DB, SdB, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9f40, DoSubx, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4)
|
||||
Oper (Op9f48, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 7, GMW, SMW, 20)
|
||||
Oper (Op9f50, DoSubW, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op9f58, DoSubW, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op9f60, DoSubW, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op9f68, DoSubW, DW, SdW, 7, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op9f70, DoSubW, DW, SdW, 7, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op9f78, DoSubW, DW, SdW, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op9f80, DoSubx, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8)
|
||||
Oper (Op9f88, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 7, GML, SML, 32)
|
||||
Oper (Op9f90, DoSubL, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op9f98, DoSubL, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op9fa0, DoSubL, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op9fa8, DoSubL, DL, SdL, 7, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op9fb0, DoSubL, DL, SdL, 7, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op9fb8, DoSubL, DL, SdL, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
Oper (Op9fc0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 7, GRL, SRL, 8)
|
||||
Oper (Op9fc8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 7, GRL, SRL, 8)
|
||||
Oper (Op9fd0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 7, GRL, SRL, 16)
|
||||
Oper (Op9fd8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 7, GRL, SRL, 16)
|
||||
Oper (Op9fe0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 16)
|
||||
Oper (Op9fe8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 20)
|
||||
Oper (Op9ff0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 7, GRL, SRL, 20)
|
||||
Oper (Op9ff8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+19)&0xfffffffc)
|
||||
|
||||
Oper (Op0400, DoSubB, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8)
|
||||
Oper (Op0410, DoSubB, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16)
|
||||
Oper (Op0418, DoSubB, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16)
|
||||
Oper (Op0420, DoSubB, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20)
|
||||
Oper (Op0428, DoSubB, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20)
|
||||
Oper (Op0430, DoSubB, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24)
|
||||
Oper (Op0438, DoSubB, DB, SimmB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+23)&0xfffffffc)
|
||||
Oper (Op0440, DoSubW, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8)
|
||||
Oper (Op0450, DoSubW, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16)
|
||||
Oper (Op0458, DoSubW, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16)
|
||||
Oper (Op0460, DoSubW, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20)
|
||||
Oper (Op0468, DoSubW, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20)
|
||||
Oper (Op0470, DoSubW, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24)
|
||||
Oper (Op0478, DoSubW, DW, SimmW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+23)&0xfffffffc)
|
||||
Oper (Op0480, DoSubL, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16)
|
||||
Oper (Op0490, DoSubL, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28)
|
||||
Oper (Op0498, DoSubL, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28)
|
||||
Oper (Op04a0, DoSubL, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32)
|
||||
Oper (Op04a8, DoSubL, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32)
|
||||
Oper (Op04b0, DoSubL, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36)
|
||||
Oper (Op04b8, DoSubL, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc)
|
||||
|
||||
Oper (Op5100, DoSubB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5110, DoSubB, DB, Ss, 8, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5118, DoSubB, DB, Ss, 8, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5120, DoSubB, DB, Ss, 8, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5128, DoSubB, DB, Ss, 8, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5130, DoSubB, DB, Ss, 8, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5138, DoSubB, DB, Ss, 8, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5140, DoSubW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5148, DoSuba, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5150, DoSubW, DW, Ss, 8, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5158, DoSubW, DW, Ss, 8, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5160, DoSubW, DW, Ss, 8, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5168, DoSubW, DW, Ss, 8, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5170, DoSubW, DW, Ss, 8, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5178, DoSubW, DW, Ss, 8, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5180, DoSubL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5188, DoSuba, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5190, DoSubL, DL, Ss, 8, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5198, DoSubL, DL, Ss, 8, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op51a0, DoSubL, DL, Ss, 8, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op51a8, DoSubL, DL, Ss, 8, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op51b0, DoSubL, DL, Ss, 8, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op51b8, DoSubL, DL, Ss, 8, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5300, DoSubB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5310, DoSubB, DB, Ss, 1, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5318, DoSubB, DB, Ss, 1, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5320, DoSubB, DB, Ss, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5328, DoSubB, DB, Ss, 1, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5330, DoSubB, DB, Ss, 1, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5338, DoSubB, DB, Ss, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5340, DoSubW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5348, DoSuba, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5350, DoSubW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5358, DoSubW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5360, DoSubW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5368, DoSubW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5370, DoSubW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5378, DoSubW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5380, DoSubL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5388, DoSuba, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5390, DoSubL, DL, Ss, 1, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5398, DoSubL, DL, Ss, 1, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op53a0, DoSubL, DL, Ss, 1, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op53a8, DoSubL, DL, Ss, 1, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op53b0, DoSubL, DL, Ss, 1, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op53b8, DoSubL, DL, Ss, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5500, DoSubB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5510, DoSubB, DB, Ss, 2, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5518, DoSubB, DB, Ss, 2, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5520, DoSubB, DB, Ss, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5528, DoSubB, DB, Ss, 2, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5530, DoSubB, DB, Ss, 2, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5538, DoSubB, DB, Ss, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5540, DoSubW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5548, DoSuba, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5550, DoSubW, DW, Ss, 2, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5558, DoSubW, DW, Ss, 2, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5560, DoSubW, DW, Ss, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5568, DoSubW, DW, Ss, 2, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5570, DoSubW, DW, Ss, 2, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5578, DoSubW, DW, Ss, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5580, DoSubL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5588, DoSuba, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5590, DoSubL, DL, Ss, 2, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5598, DoSubL, DL, Ss, 2, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op55a0, DoSubL, DL, Ss, 2, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op55a8, DoSubL, DL, Ss, 2, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op55b0, DoSubL, DL, Ss, 2, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op55b8, DoSubL, DL, Ss, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5700, DoSubB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5710, DoSubB, DB, Ss, 3, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5718, DoSubB, DB, Ss, 3, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5720, DoSubB, DB, Ss, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5728, DoSubB, DB, Ss, 3, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5730, DoSubB, DB, Ss, 3, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5738, DoSubB, DB, Ss, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5740, DoSubW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5748, DoSuba, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5750, DoSubW, DW, Ss, 3, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5758, DoSubW, DW, Ss, 3, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5760, DoSubW, DW, Ss, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5768, DoSubW, DW, Ss, 3, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5770, DoSubW, DW, Ss, 3, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5778, DoSubW, DW, Ss, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5780, DoSubL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5788, DoSuba, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5790, DoSubL, DL, Ss, 3, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5798, DoSubL, DL, Ss, 3, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op57a0, DoSubL, DL, Ss, 3, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op57a8, DoSubL, DL, Ss, 3, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op57b0, DoSubL, DL, Ss, 3, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op57b8, DoSubL, DL, Ss, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5900, DoSubB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5910, DoSubB, DB, Ss, 4, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5918, DoSubB, DB, Ss, 4, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5920, DoSubB, DB, Ss, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5928, DoSubB, DB, Ss, 4, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5930, DoSubB, DB, Ss, 4, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5938, DoSubB, DB, Ss, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5940, DoSubW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5948, DoSuba, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5950, DoSubW, DW, Ss, 4, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5958, DoSubW, DW, Ss, 4, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5960, DoSubW, DW, Ss, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5968, DoSubW, DW, Ss, 4, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5970, DoSubW, DW, Ss, 4, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5978, DoSubW, DW, Ss, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5980, DoSubL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5988, DoSuba, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5990, DoSubL, DL, Ss, 4, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5998, DoSubL, DL, Ss, 4, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op59a0, DoSubL, DL, Ss, 4, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op59a8, DoSubL, DL, Ss, 4, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op59b0, DoSubL, DL, Ss, 4, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op59b8, DoSubL, DL, Ss, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5b00, DoSubB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5b10, DoSubB, DB, Ss, 5, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5b18, DoSubB, DB, Ss, 5, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5b20, DoSubB, DB, Ss, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5b28, DoSubB, DB, Ss, 5, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5b30, DoSubB, DB, Ss, 5, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5b38, DoSubB, DB, Ss, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5b40, DoSubW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5b48, DoSuba, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5b50, DoSubW, DW, Ss, 5, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5b58, DoSubW, DW, Ss, 5, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5b60, DoSubW, DW, Ss, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5b68, DoSubW, DW, Ss, 5, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5b70, DoSubW, DW, Ss, 5, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5b78, DoSubW, DW, Ss, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5b80, DoSubL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5b88, DoSuba, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5b90, DoSubL, DL, Ss, 5, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5b98, DoSubL, DL, Ss, 5, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op5ba0, DoSubL, DL, Ss, 5, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op5ba8, DoSubL, DL, Ss, 5, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op5bb0, DoSubL, DL, Ss, 5, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op5bb8, DoSubL, DL, Ss, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5d00, DoSubB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5d10, DoSubB, DB, Ss, 6, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5d18, DoSubB, DB, Ss, 6, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5d20, DoSubB, DB, Ss, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5d28, DoSubB, DB, Ss, 6, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5d30, DoSubB, DB, Ss, 6, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5d38, DoSubB, DB, Ss, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5d40, DoSubW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5d48, DoSuba, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5d50, DoSubW, DW, Ss, 6, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5d58, DoSubW, DW, Ss, 6, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5d60, DoSubW, DW, Ss, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5d68, DoSubW, DW, Ss, 6, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5d70, DoSubW, DW, Ss, 6, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5d78, DoSubW, DW, Ss, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5d80, DoSubL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5d88, DoSuba, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5d90, DoSubL, DL, Ss, 6, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5d98, DoSubL, DL, Ss, 6, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op5da0, DoSubL, DL, Ss, 6, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op5da8, DoSubL, DL, Ss, 6, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op5db0, DoSubL, DL, Ss, 6, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op5db8, DoSubL, DL, Ss, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
||||
Oper (Op5f00, DoSubB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, 4)
|
||||
Oper (Op5f10, DoSubB, DB, Ss, 7, DB, DA, Cain, ins7, GMB, SMB, 12)
|
||||
Oper (Op5f18, DoSubB, DB, Ss, 7, DB, DA, CaipB, ins7, GMB, SMB, 12)
|
||||
Oper (Op5f20, DoSubB, DB, Ss, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16)
|
||||
Oper (Op5f28, DoSubB, DB, Ss, 7, DB, DA, Fdai, ins7, GMB, SMB, 16)
|
||||
Oper (Op5f30, DoSubB, DB, Ss, 7, DB, DA, Faix, ins7, GMB, SMB, 20)
|
||||
Oper (Op5f38, DoSubB, DB, Ss, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5f40, DoSubW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, 4)
|
||||
Oper (Op5f48, DoSuba, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5f50, DoSubW, DW, Ss, 7, DW, DA, Cain, ins7, GMW, SMW, 12)
|
||||
Oper (Op5f58, DoSubW, DW, Ss, 7, DW, DA, CaipW, ins7, GMW, SMW, 12)
|
||||
Oper (Op5f60, DoSubW, DW, Ss, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16)
|
||||
Oper (Op5f68, DoSubW, DW, Ss, 7, DW, DA, Fdai, ins7, GMW, SMW, 16)
|
||||
Oper (Op5f70, DoSubW, DW, Ss, 7, DW, DA, Faix, ins7, GMW, SMW, 20)
|
||||
Oper (Op5f78, DoSubW, DW, Ss, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc)
|
||||
Oper (Op5f80, DoSubL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, 8)
|
||||
Oper (Op5f88, DoSuba, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8)
|
||||
Oper (Op5f90, DoSubL, DL, Ss, 7, DL, DA, Cain, ins7, GML, SML, 20)
|
||||
Oper (Op5f98, DoSubL, DL, Ss, 7, DL, DA, CaipL, ins7, GML, SML, 20)
|
||||
Oper (Op5fa0, DoSubL, DL, Ss, 7, DL, DA, CmaiL, ins7, GML, SML, 24)
|
||||
Oper (Op5fa8, DoSubL, DL, Ss, 7, DL, DA, Fdai, ins7, GML, SML, 24)
|
||||
Oper (Op5fb0, DoSubL, DL, Ss, 7, DL, DA, Faix, ins7, GML, SML, 28)
|
||||
Oper (Op5fb8, DoSubL, DL, Ss, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc)
|
||||
|
|
@ -0,0 +1 @@
|
|||
#define operin unsigned long *reg
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* proto.h - FAST 68000 emulator instruction prototypes
|
||||
* Version 1.0
|
||||
* Copyright (C) 1994, 1995 Joachim Hönig
|
||||
* (hoenig@informatik.uni-erlangen.de)
|
||||
*
|
||||
* This file is part of FAST, the Fine Atari ST Emulator.
|
||||
*
|
||||
* FAST is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* FAST is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with FAST; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
/*
|
||||
* Prototypes of all 68000 opcodes defined in op68k*.c
|
||||
*/
|
||||
|
||||
#include "operin.h"
|
||||
|
||||
#undef Oper
|
||||
#define Oper(a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12) \
|
||||
extern unsigned long a1(operin);
|
||||
|
||||
#define PROTOH
|
||||
|
||||
#include "op68kadd.cpp"
|
||||
#include "op68karith.cpp"
|
||||
#include "op68ksub.cpp"
|
||||
#include "op68klogop.cpp"
|
||||
#include "op68kmisc.cpp"
|
||||
#include "op68kmove.cpp"
|
||||
#include "op68kshift.cpp"
|
||||
|
||||
extern unsigned long Op4840(operin); /* SWAP */
|
||||
extern unsigned long Op4848(operin); /* BKPT */
|
||||
extern unsigned long Op4880(operin); /* EXT.W */
|
||||
extern unsigned long Op4890(operin); /* MOVEM.W to (ax) */
|
||||
extern unsigned long Op48a0(operin); /* MOVEM.W to -(ax) */
|
||||
extern unsigned long Op48a8(operin); /* MOVEM.W to d(ax) */
|
||||
extern unsigned long Op48b0(operin); /* MOVEM.W to d(ax,rx) */
|
||||
extern unsigned long Op48b8(operin); /* MOVEM.W to w l */
|
||||
extern unsigned long Op48c0(operin); /* EXT.L */
|
||||
extern unsigned long Op48d0(operin); /* MOVEM.L to (ax) */
|
||||
extern unsigned long Op48e0(operin); /* MOVEM.L to -(ax) */
|
||||
extern unsigned long Op48e8(operin); /* MOVEM.L to d(ax) */
|
||||
extern unsigned long Op48f0(operin); /* MOVEM.L to d(ax,rx) */
|
||||
extern unsigned long Op48f8(operin); /* MOVEM.L to w l */
|
||||
extern unsigned long Op4c90(operin); /* MOVEM.W from (ax) */
|
||||
extern unsigned long Op4c98(operin); /* MOVEM.W from (ax)+ */
|
||||
extern unsigned long Op4ca8(operin); /* MOVEM.W from d(ax) */
|
||||
extern unsigned long Op4cb0(operin); /* MOVEM.W from d(ax,rx) */
|
||||
extern unsigned long Op4cb8(operin); /* MOVEM.W from ea */
|
||||
extern unsigned long Op4cd0(operin); /* MOVEM.L from (ax) */
|
||||
extern unsigned long Op4cd8(operin); /* MOVEM.L from (ax)+ */
|
||||
extern unsigned long Op4ce8(operin); /* MOVEM.L from d(ax) */
|
||||
extern unsigned long Op4cf0(operin); /* MOVEM.L from d(ax,rx) */
|
||||
extern unsigned long Op4cf8(operin); /* MOVEM.L from ea */
|
||||
extern unsigned long Op4e40(operin); /* TRAP */
|
||||
extern unsigned long Op4e50(operin); /* LINK */
|
||||
extern unsigned long Op4e58(operin); /* UNLK */
|
||||
extern unsigned long Op4e60(operin); /* MOVE ax,usp */
|
||||
extern unsigned long Op4e68(operin); /* MOVE usp,ax */
|
||||
extern unsigned long Op4e70(operin); /* RESET, NOP, STOP, RTE,
|
||||
* RTD, RTS, TRAPV, RTR */
|
||||
extern unsigned long Op4e78(operin); /* MOVEC */
|
||||
|
||||
extern unsigned long Opc140(operin); /* EXG */
|
||||
extern unsigned long Opc148(operin); /* EXG */
|
||||
extern unsigned long Opc188(operin); /* EXG */
|
||||
extern unsigned long Opc340(operin); /* EXG */
|
||||
extern unsigned long Opc348(operin); /* EXG */
|
||||
extern unsigned long Opc388(operin); /* EXG */
|
||||
extern unsigned long Opc540(operin); /* EXG */
|
||||
extern unsigned long Opc548(operin); /* EXG */
|
||||
extern unsigned long Opc588(operin); /* EXG */
|
||||
extern unsigned long Opc740(operin); /* EXG */
|
||||
extern unsigned long Opc748(operin); /* EXG */
|
||||
extern unsigned long Opc788(operin); /* EXG */
|
||||
extern unsigned long Opc940(operin); /* EXG */
|
||||
extern unsigned long Opc948(operin); /* EXG */
|
||||
extern unsigned long Opc988(operin); /* EXG */
|
||||
extern unsigned long Opcb40(operin); /* EXG */
|
||||
extern unsigned long Opcb48(operin); /* EXG */
|
||||
extern unsigned long Opcb88(operin); /* EXG */
|
||||
extern unsigned long Opcd40(operin); /* EXG */
|
||||
extern unsigned long Opcd48(operin); /* EXG */
|
||||
extern unsigned long Opcd88(operin); /* EXG */
|
||||
extern unsigned long Opcf40(operin); /* EXG */
|
||||
extern unsigned long Opcf48(operin); /* EXG */
|
||||
extern unsigned long Opcf88(operin); /* EXG */
|
||||
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,275 @@
|
|||
/*
|
||||
* Castaway
|
||||
* (C) 1994 - 2002 Martin Doering, Joachim Hoenig
|
||||
*
|
||||
* 68000.c - 68000 emulator jump table and misc subroutines
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*
|
||||
* revision history
|
||||
* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring
|
||||
* 09.06.2002 JH Use of mmap for memory access discontinued
|
||||
* 12.06.2002 JH Correct bus error/address error exception stack frame
|
||||
* 13.06.2002 JH Merged in Martin's BCD implementation (untested),
|
||||
* completed jump table. STOP is now the only
|
||||
* unimplemented instruction.
|
||||
* 14.06.2002 JH Implemented STOP, shutdown CPU after multiple bus errors.
|
||||
* Removed inst parameter from CPU opcode functions.
|
||||
* 19.06.2002 JH CPURun() returns # of executed instructions.
|
||||
* 20.06.2002 JH added yet another SR implementation variant.
|
||||
* 02.07.2002 JH Support different CPU types. Removed MOVE CCR,<EA> from
|
||||
* 68000 jump table.
|
||||
* 20.08.2002 JH Fixed CPU shutdown.
|
||||
* 27.08.2002 JH Bugfix: S and T flag incorrectly reported for group 0 exceptions
|
||||
* Implemented additional 68010 registers and instructions.
|
||||
* 31.08.2002 JH Implemented M68010 exception stack frames.
|
||||
* 08.10.2002 JH Implemented Trace exception
|
||||
*/
|
||||
static char sccsid[] = "$Id: 68000.c,v 1.18 2002/10/10 19:52:11 jhoenig Exp $";
|
||||
#include "config.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <assert.h>
|
||||
#include <setjmp.h>
|
||||
#include "68000.h"
|
||||
#include "mem.h"
|
||||
#include "st.h"
|
||||
#include "op68k.h"
|
||||
#include "proto.h"
|
||||
#include "operin.h"
|
||||
|
||||
|
||||
#if (CPU_TYPE == 68000 || CPU_TYPE == 68008)
|
||||
#include "op68000.h"
|
||||
#elif (CPU_TYPE == 68010) // broken
|
||||
#include "op68010.h"
|
||||
#endif
|
||||
extern int disass;
|
||||
unsigned long reg[23];
|
||||
unsigned long dfc, sfc, vbr;
|
||||
#define biginst reg[18]
|
||||
#define pc reg[19]
|
||||
#define usp reg[20]
|
||||
#define ssp reg[21]
|
||||
#define recalc_int reg[22]
|
||||
|
||||
|
||||
extern void StartDisass();
|
||||
unsigned short SaveWordTrc;
|
||||
unsigned char GetTrc;
|
||||
unsigned short int0=0;
|
||||
unsigned long exaddress=0x12345678;
|
||||
int intmask, intpri;
|
||||
char cpu_state;
|
||||
unsigned cpu_type;
|
||||
volatile unsigned cpu_count;
|
||||
|
||||
jmp_buf trap_buf;
|
||||
|
||||
|
||||
unsigned short GetSRB(void)
|
||||
{
|
||||
uint32 cvnz=reg[16]; //-------c-------v-------n-------z
|
||||
uint32 stx=reg[17]; //---------------s-------t-------x
|
||||
uint32 sr=(cvnz>>24)+(cvnz>>15)+(cvnz<<2)+(cvnz>>5)+(stx<<4);
|
||||
return sr&(unsigned short)0xff;
|
||||
}
|
||||
|
||||
unsigned short GetSRW(void)
|
||||
{
|
||||
uint32 cvnz=reg[16]; //-------c-------v-------n-------z
|
||||
uint32 stx=reg[17]; //---------------s-------t-------x
|
||||
uint32 sr=(cvnz>>24)+(cvnz>>15)+(cvnz<<2)+(cvnz>>5)+(stx<<4);
|
||||
uint32 sr2=(stx<<7)+(stx>>3)+(intmask<<8);
|
||||
return (sr&(unsigned short)0xff)+(sr2&(unsigned short)0xff00);
|
||||
}
|
||||
|
||||
|
||||
void SetSRB(unsigned long sr)
|
||||
{
|
||||
uint32 cvnz=((sr&1)<<24)+((sr&2)<<15)+((sr&4)>>2)+((sr&8)<<5);
|
||||
reg[16]=cvnz;
|
||||
SetX(sr&0x10);
|
||||
}
|
||||
|
||||
void SetSRW(unsigned long sr)
|
||||
{
|
||||
uint32 cvnz=((sr&1)<<24)+((sr&2)<<15)+((sr&4)>>2)+((sr&8)<<5);
|
||||
reg[16]=cvnz;
|
||||
SetX (sr&0x10);
|
||||
SetI ((sr&0x700)>>8);
|
||||
SetS (sr&0x2000);
|
||||
SetT (sr&0x8000);
|
||||
}
|
||||
|
||||
void ExceptionGroup0(
|
||||
int number,
|
||||
unsigned long address,
|
||||
int ReadWrite)
|
||||
{
|
||||
short sr = GetSRW(), context = 0;
|
||||
#ifdef DEBUG
|
||||
ON_TRAP(number);
|
||||
assert(cpu_state != -3);
|
||||
#endif
|
||||
if ((exaddress+1!=address)&&(exaddress+2!=address)&&(exaddress+3!=address)){
|
||||
if (cpu_state == 0) {
|
||||
cpu_state = -3;
|
||||
longjmp(trap_buf, 1);
|
||||
}
|
||||
#if CPU_TYPE == 68000
|
||||
else if (cpu_state > 0) {
|
||||
context |= 0x8;
|
||||
}
|
||||
if (ReadWrite) context |= 0x10;
|
||||
#else
|
||||
if (ReadWrite) context |= 0x100;
|
||||
#endif
|
||||
if (GetS()) context |= 0x4;
|
||||
if (ReadWrite && address == pc) context |= 0x2;
|
||||
else context |= 0x1;
|
||||
cpu_state = 0; /* begin group 0 exception processing */
|
||||
SetS (1);
|
||||
SetT (0);
|
||||
#if CPU_TYPE == 68010
|
||||
reg[15] -= 44; /* Rerun info */
|
||||
reg[15] -= 4; SetMemL(reg[15], address); /* fault address */
|
||||
reg[15] -= 2; SetMemW(reg[15], context);
|
||||
reg[15] -= 2; SetMemW(reg[15], 0x8000 | (number * 4));
|
||||
reg[15] -= 4; SetMemL(reg[15], GetPC());
|
||||
reg[15] -= 2; SetMemW(reg[15], sr);
|
||||
#else
|
||||
reg[15] = reg[15] - 14;
|
||||
SetMemW(reg[15], context);
|
||||
SetMemL(reg[15] + 2, address);
|
||||
SetMemW(reg[15] + 6, (uint16)biginst);
|
||||
SetMemW(reg[15] + 8, sr);
|
||||
SetMemL(reg[15] + 10, GetPC());
|
||||
#endif
|
||||
|
||||
SetPC (GetMemL ((long) number * 4) + vbr);
|
||||
/* end exception processing */
|
||||
cpu_state = -1;
|
||||
exaddress=address;
|
||||
|
||||
}
|
||||
int0=1;
|
||||
}
|
||||
|
||||
void ExceptionGroup1(int number)
|
||||
{
|
||||
|
||||
uint32 sp, newpc=pc;
|
||||
short sr = GetSRW();
|
||||
|
||||
if (number!=TRAPV) newpc-=2;
|
||||
SetS(1);
|
||||
SetT(0);
|
||||
sp=reg[15];
|
||||
sp-=4; SetMemL(sp, newpc);
|
||||
sp-=2; SetMemW(sp, sr);
|
||||
reg[15]=sp;
|
||||
SetPC (GetMemL(number*4+vbr));
|
||||
int0=1;
|
||||
}
|
||||
|
||||
void Interrupt(int number, int level)
|
||||
{
|
||||
uint32 sp;
|
||||
short sr = GetSRW();
|
||||
SetI(level); SetS(1); SetT(0);
|
||||
sp=reg[15];
|
||||
sp-=4; SetMemL(sp, GetPC());
|
||||
sp-=2; SetMemW(sp, sr);
|
||||
reg[15]=sp;
|
||||
SetPC (GetMemL(number*4+vbr));
|
||||
}
|
||||
|
||||
void ExceptionGroup2(int number)
|
||||
{
|
||||
uint32 sp;
|
||||
short sr = GetSRW();
|
||||
SetS(1); SetT(0);
|
||||
sp=reg[15];
|
||||
sp-=4; SetMemL(sp, GetPC());
|
||||
sp-=2; SetMemW(sp, sr);
|
||||
reg[15]=sp;
|
||||
SetPC (GetMemL(number*4+vbr));
|
||||
}
|
||||
|
||||
unsigned long Trace()
|
||||
{
|
||||
uint32 sp;
|
||||
short sr;
|
||||
register unsigned long cycleco=0;
|
||||
register unsigned long address,timeinst;
|
||||
register int8 *mymembase=membase;
|
||||
register int8 *myrombase=rombase;
|
||||
register uint32 myinst;
|
||||
address = pc&MEMADDRMASK;
|
||||
// disass=1;
|
||||
int0=0;
|
||||
if (address<MEMSIZE) myinst=biginst=ReadSL(mymembase+address);
|
||||
else if (address>=ROMBASE) myinst=biginst=ReadSL(myrombase+address);
|
||||
else { ExceptionGroup1(ADDRESSERR); return cycleco; }
|
||||
#ifdef DISASS
|
||||
if (disass==1) StoreTrace();
|
||||
#endif
|
||||
pc+=2;
|
||||
cycleco+=(*jmp_table[(myinst<<16)>>19])(reg);
|
||||
|
||||
if (!int0){
|
||||
sr = GetSRW();
|
||||
SetS(1); SetT(0);
|
||||
sp=reg[15];
|
||||
sp-=4; SetMemL(sp, GetPC());
|
||||
sp-=2; SetMemW(sp, sr);
|
||||
reg[15]=sp;
|
||||
SetPC (GetMemL(TRACE*4+vbr));
|
||||
return cycleco;
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
unsigned long IllIns(operin)
|
||||
{
|
||||
ExceptionGroup1(ILLINSTR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long Line_A(operin)
|
||||
{
|
||||
ExceptionGroup1(LINE_A);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long Line_F(operin)
|
||||
{
|
||||
ExceptionGroup1(LINE_F);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long Stop(void)
|
||||
{
|
||||
if (!GetS())
|
||||
ExceptionGroup1(PRIV);
|
||||
SetSRW(GetMPCW());
|
||||
pc += 2;
|
||||
cpu_state = -2; /* stopped */
|
||||
//longjmp(trap_buf, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void HWReset(void)
|
||||
{
|
||||
reg[15] = GetMemL (0l);
|
||||
SetPC(GetMemL (4l));
|
||||
SetI(7);
|
||||
SetT(0);
|
||||
SetS(1);
|
||||
cpu_state = -1; /* running */
|
||||
cpu_type = CPU_TYPE;
|
||||
}
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
/*
|
||||
* Castaway
|
||||
* (C) 1994 - 2002 Martin Doering, Joachim Hoenig
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*/
|
||||
#ifndef _68000H
|
||||
#define _68000H
|
||||
|
||||
#include "config.h" // wg. define
|
||||
#include "operin.h"
|
||||
|
||||
/*
|
||||
* Supported CPU types
|
||||
* CPU CPU_TYPE
|
||||
* MC68000 68000
|
||||
* MC68008 68000
|
||||
* MC68EC000 not supported (yet)
|
||||
* MC68010 68010
|
||||
* MC68020 68020
|
||||
* MC68EC020 not supported (yet)
|
||||
* MC68030 not supported (yet)
|
||||
* MC68EC030 not supported (yet)
|
||||
* MC68040 not supported (yet)
|
||||
* MC68EC040 not supported (yet)
|
||||
* CPU32 not supported (yet)
|
||||
*/
|
||||
#define CPU_TYPE 68000
|
||||
|
||||
/*
|
||||
* Exception vector numbers (trap numbers).
|
||||
*/
|
||||
#define RESET 0
|
||||
#define BUSERR 2
|
||||
#define ADDRESSERR 3
|
||||
#define ILLINSTR 4
|
||||
#define DIVZ 5
|
||||
#define TRAPCHK 6
|
||||
#define TRAPV 7
|
||||
#define PRIV 8
|
||||
#define TRACE 9
|
||||
#define LINE_A 10
|
||||
#define LINE_F 11
|
||||
#if CPU_TYPE != 68000
|
||||
#define FORMATERR 14
|
||||
#endif
|
||||
#define AUTOINT1 25
|
||||
#define AUTOINT2 26
|
||||
#define AUTOINT3 27
|
||||
#define AUTOINT4 28
|
||||
#define AUTOINT5 29
|
||||
#define AUTOINT6 30
|
||||
#define AUTOINT7 31
|
||||
#define TRAP0 32 + 0
|
||||
#define TRAP1 32 + 1
|
||||
#define TRAP2 32 + 2
|
||||
#define TRAP3 32 + 3
|
||||
#define TRAP4 32 + 4
|
||||
#define TRAP5 32 + 5
|
||||
#define TRAP6 32 + 6
|
||||
#define TRAP7 32 + 7
|
||||
#define TRAP8 32 + 8
|
||||
#define TRAP9 32 + 9
|
||||
#define TRAP10 32 + 10
|
||||
#define TRAP11 32 + 11
|
||||
#define TRAP12 32 + 12
|
||||
#define TRAP13 32 + 13
|
||||
#define TRAP14 32 + 14
|
||||
#define TRAP15 32 + 15
|
||||
|
||||
/* Group 0 exceptions (address error / bus error) */
|
||||
extern void ExceptionGroup0(
|
||||
int number, /* trap number */
|
||||
unsigned long address, /* fault address */
|
||||
int ReadWrite); /* read = true, write = false */
|
||||
/* Group 1 exceptions: illegal instruction, privilege violation, interrupts */
|
||||
extern void ExceptionGroup1(int number);
|
||||
extern void Interrupt(int number, int level);
|
||||
/* Group 2 exceptions: traps, divide by zero */
|
||||
extern void ExceptionGroup2(int number);
|
||||
|
||||
extern void HWReset(void); /* Reset */
|
||||
extern unsigned long IllIns(operin); /* Illegal instruction */
|
||||
extern unsigned long Line_A(operin); /* Axxx instruction opcode */
|
||||
extern unsigned long Line_F(operin); /* Fxxx instruction opcode */
|
||||
extern unsigned long Stop(void); /* Stop instruction */
|
||||
|
||||
extern unsigned char tracemode; //For Trace Switching
|
||||
extern unsigned short SaveWordTrc;
|
||||
extern unsigned char GetTrc;
|
||||
|
||||
/*
|
||||
* CPU Registers
|
||||
*
|
||||
* WARNING:
|
||||
* Never access registers directly from outside the emulator.
|
||||
* The internal representation of registers may change.
|
||||
*/
|
||||
/* Data and address registers are stored in native byte order.
|
||||
* register numbering: 0=d0, 1=d1, ..., 8=a0, 9=a1, ... 15=a7 */
|
||||
extern unsigned long reg[23];
|
||||
#define biginst reg[18]
|
||||
#define pc reg[19]
|
||||
#define usp reg[20]
|
||||
#define ssp reg[21]
|
||||
#define recalc_int reg[22]
|
||||
|
||||
|
||||
#define ins7 (biginst & 7)
|
||||
#define ins15 (biginst & 15)
|
||||
|
||||
/* 68010 registers */
|
||||
extern unsigned long dfc, sfc, vbr;
|
||||
/* 68020 registers */
|
||||
extern unsigned long caar, cacr, isp, msp;
|
||||
|
||||
extern int intmask;
|
||||
extern char cpu_state; /* 0, 1, 2 while processing exceptions,
|
||||
* -1 executing, -2 stopped, -3 shutdown */
|
||||
extern unsigned cpu_type; /* 68000, 68010 */
|
||||
|
||||
/*
|
||||
* Interrupts
|
||||
*
|
||||
* The state of interrupt lines IPL0-IPL2 is stored in the variable
|
||||
* intpri. The emulator acknowledges interrupts by calling QueryIRQ().
|
||||
* It expects the interrupt vector number to be returned.
|
||||
* WARNING:
|
||||
* Never update intpri asynchronously. Use the CPUEvent() function
|
||||
* to force CPURun() to return before updating intpri.
|
||||
*/
|
||||
extern int intpri;
|
||||
extern int QueryIRQ(int level); /* get interrupt vector number */
|
||||
|
||||
#define GetS() *(((int8*)reg)+70)
|
||||
#define GetFC2() GetS()
|
||||
#define GetFC1() address == pc
|
||||
#define GetFC0() address != pc
|
||||
#define GetFC() (((GetFC2() << 1) | GetFC1()) << 1) | GetFC0()
|
||||
|
||||
/*
|
||||
* memory access jump tables
|
||||
*/
|
||||
#define MEMADDRMASK 0x00ffffffl
|
||||
#define MEMADDRMASKS 0x00fffffel
|
||||
#define MEMIDXSHIFT 11
|
||||
#define MEMADDRSIZE (MEMADDRMASK + 1)
|
||||
#define MEMTABLESIZE (MEMADDRSIZE >> MEMIDXSHIFT)
|
||||
#define MEMBANKSIZE (MEMADDRSIZE / MEMTABLESIZE)
|
||||
#define MEMBANKMASK (MEMBANKSIZE - 1)
|
||||
|
||||
/* Fetch byte from address */
|
||||
char GetMemB(unsigned long address);
|
||||
short GetMemW(unsigned long address);
|
||||
long GetMemL(unsigned long address);
|
||||
void SetMemB (unsigned long address, unsigned char value);
|
||||
void SetMemW(unsigned long address, unsigned short value);
|
||||
void SetMemL(unsigned long address, unsigned long value);
|
||||
#ifdef DEBUG
|
||||
extern int stop_on;
|
||||
extern int verb_on;
|
||||
/* go to sleep (gives debugger a chance to attach) */
|
||||
void DebugStop(void);
|
||||
#ifdef TRACEBACK
|
||||
/*
|
||||
* execution trace
|
||||
*/
|
||||
struct state {
|
||||
uint32 reg[16];
|
||||
uint32 stack[8];
|
||||
uint32 pc, usp, ssp;
|
||||
uint16 inst[5];
|
||||
uint16 sr;
|
||||
|
||||
};
|
||||
extern int hide_supervisor;
|
||||
extern unsigned long instcnt;
|
||||
extern int tbi;
|
||||
extern struct state traceback[TRACEBACK];
|
||||
extern int trace_on;
|
||||
/* print execution trace of last TRACEBACK instructions and sleep */
|
||||
void TraceStop(void);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
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