kopia lustrzana https://github.com/Jean-MarcHarvengt/MCUME
changed z80 emulator to the cycle-stepped one
AlinTigaeru
rodzic
88ef857bca
commit
a2553293f9
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@ -11,8 +11,10 @@ extern "C" {
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#include "emuapi.h"
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#include "platform_config.h"
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}
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#include "processor/Z80.h"
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#include "processor/Tables.h"
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#ifndef CHIPS_IMPL
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#define CHIPS_IMPL
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#endif
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#include "z80.h"
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#include "crtc.h"
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#include "ga.h"
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#include "roms/rom464.h"
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@ -29,14 +31,58 @@ extern "C" {
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uint8_t RAM[0x10000]; // 64k
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unsigned char* bitstream = 0; // 16k video ram to be used by PIO.
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unsigned char* bitstream_init_pos = 0;
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static Z80 CPU;
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static z80_t CPU;
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uint64_t pins;
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bool interrupt_generated = false;
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int sline = 0;
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int cycles_left = 0;
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bool test_flag = false;
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// Implementations of system-specific emuapi Init, Step etc. functions.
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// Helper functions
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char read_z80(uint16_t Addr)
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{
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if(Addr <= LOWER_ROM_END && ga_config.lower_rom_enable)
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{
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// printf("At program counter %x, Z80 read from address %x in OS ROM\n", CPU.PC.W, Addr);
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return gb_rom_464_0[Addr];
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}
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else if(Addr >= UPPER_ROM_BEGIN && ga_config.upper_rom_enable)
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{
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// printf("At program counter %x, Z80 read from address %x in BASIC ROM\n", CPU.PC.W, Addr);
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return gb_rom_464_1[Addr - 0xC000];
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}
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else
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{
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// printf("At program counter %x, Z80 read from address %x in RAM\n", CPU.PC.W, Addr);
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return RAM[Addr];
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}
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}
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void write_z80(uint16_t Addr, uint8_t Value)
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{
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RAM[Addr] = Value;
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}
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void out_z80(uint16_t Port, uint8_t Value)
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{
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if(!(Port & 0x8000)) write_gate_array(Value); // The Gate Array is selected when bit 15 is set to 0.
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if(!(Port & 0x4000)) write_crt_controller(Port, Value); // The CRTC is selected when bit 14 is set to 0.
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if(!(Port & 0x2000))
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{
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// upper rom bank number. ROM banking needs to be done regardless of CPC model
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// The Upper ROM Bank Number (in range of 0x00..0xFF) to be mapped to memory at 0xC000..0xFFFF
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// byte req_bank_number = Value & 15;
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// if(ga_config.upper_rom_enable)
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// {
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// }
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}
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}
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uint8_t in_z80(uint16_t Port)
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{
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if(!(Port & 0x4000)) return read_crt_controller(Port); // The CRTC is selected when bit 14 is set to 0.
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return 0xFF;
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}
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/**
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* Creates initial emulation state (i.e. sets up color palette, clears memory etc.)
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@ -49,9 +95,8 @@ void cpc_Init(void)
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emu_SetPaletteEntry(firmware_palette[i].R, firmware_palette[i].G, firmware_palette[i].B, i);
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}
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if (bitstream == 0) bitstream = (unsigned char *)emu_Malloc(WIDTH*HEIGHT); //*HEIGHT
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bitstream_init_pos = bitstream;
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ResetZ80(&CPU, CYCLES_PER_FRAME);
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pins = z80_init(&CPU);
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memset(RAM, 0, sizeof(RAM));
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}
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@ -60,12 +105,9 @@ void cpc_Init(void)
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*/
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void cpc_Start(char* filename)
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{
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CPU.PC.W = 0x0000;
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//CPU.IFF = IFF_IM1;
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ga_config.lower_rom_enable = true;
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ga_config.upper_rom_enable = false;
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ga_config.interrupt_counter = 0;
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// write_gate_array(0xC0);
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}
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/**
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@ -73,24 +115,77 @@ void cpc_Start(char* filename)
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*/
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void cpc_Step(void)
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{
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for(;!is_hsync_active();)
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//for(;!is_hsync_active();)
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//{
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// if not (z80 wait and ga wait) then tick, otherwise stall.
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// or rather the tick will be a stall if both waits are asserted, i think that's better.
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bool interrupt_acknowledged = false;
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if(!(pins&Z80_WAIT && ga_config.wait_signal))
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{
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cycles_left = ExecZ80(&CPU, 24); // execute for the duration of 6 NOPs (maximum instruction length)
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for(int k = 0; k < (24 - cycles_left) / 4; k++)
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pins = z80_tick(&CPU, pins);
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if (pins & Z80_MREQ)
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{
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crtc_step();
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interrupt_generated = ga_step();
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if(interrupt_generated)
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const uint16_t addr = Z80_GET_ADDR(pins);
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if (pins & Z80_RD)
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{
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// printf("Interrupting!\n");
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IntZ80(&CPU, INT_RST38);
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ga_config.interrupt_counter &= 0x1f;
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uint8_t data = read_z80(addr);
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Z80_SET_DATA(pins, data);
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}
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else if (pins & Z80_WR)
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{
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uint8_t data = Z80_GET_DATA(pins);
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write_z80(addr, data);
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}
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}
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else if (pins & Z80_IORQ)
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{
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const uint16_t port = Z80_GET_ADDR(pins);
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if (pins & Z80_M1)
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{
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// an interrupt acknowledge cycle, depending on the emulated system,
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// put either an instruction byte, or an interrupt vector on the data bus
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Z80_SET_DATA(pins, 0x0038);
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interrupt_acknowledged = true;
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}
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else if (pins & Z80_RD)
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{
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// handle IO input request at port
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in_z80(port);
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}
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else if (pins & Z80_WR)
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{
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// handle IO output request at port
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uint8_t data = Z80_GET_DATA(pins);
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out_z80(port, data);
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}
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}
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}
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emu_DrawLine8(bitstream, WIDTH, HEIGHT, sline);
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sline = (sline + 1) % NBLINES;
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crtc_step();
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interrupt_generated = ga_step();
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if(interrupt_generated)
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{
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// To request an interrupt, or inject a wait state just set the respective pin
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// (Z80_INT, Z80_NMI, Z80_WAIT), don't forget to clear the pin again later (the
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// details on when those pins are set and cleared depend heavily on the
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// emulated system).
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// request an interrupt from the CPU
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// TODO how to set the Z80_INT pin?
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}
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if(interrupt_acknowledged)
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{
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ga_config.interrupt_counter &= 0x1f;
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}
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if(is_hsync_active())
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{
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sline = (sline + 1) % NBLINES;
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emu_DrawLine8(bitstream, WIDTH, HEIGHT, sline);
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}
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if(is_vsync_active())
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{
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@ -108,70 +203,10 @@ void cpc_Step(void)
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crtc_step();
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ga_step();
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}
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}
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/**
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* Input handler.
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*/
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void cpc_Input(int bClick)
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{
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}
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void draw_vsync()
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{
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emu_DrawVsync();
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}
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// System-specific implementations of the Z80 instructions required by the portable Z80 emulator.
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void OutZ80(word Port, byte Value)
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{
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if(!(Port & 0x8000)) write_gate_array(Value); // The Gate Array is selected when bit 15 is set to 0.
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if(!(Port & 0x4000)) write_crt_controller(Port, Value); // The CRTC is selected when bit 14 is set to 0.
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if(!(Port & 0x2000))
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{
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// upper rom bank number. ROM banking needs to be done regardless of CPC model
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// The Upper ROM Bank Number (in range of 0x00..0xFF) to be mapped to memory at 0xC000..0xFFFF
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// byte req_bank_number = Value & 15;
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// if(ga_config.upper_rom_enable)
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// {
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// }
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}
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}
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byte InZ80(word Port)
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{
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if(!(Port & 0x4000)) return read_crt_controller(Port); // The CRTC is selected when bit 14 is set to 0.
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return 0xFF;
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}
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void WrZ80(word Addr, byte Value)
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{
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RAM[Addr] = Value;
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}
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void PatchZ80(Z80 *R)
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{
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// do nothing
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}
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byte RdZ80(word Addr)
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{
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if(Addr <= LOWER_ROM_END && ga_config.lower_rom_enable)
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{
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// printf("At program counter %x, Z80 read from address %x in OS ROM\n", CPU.PC.W, Addr);
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return gb_rom_464_0[Addr];
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}
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else if(Addr >= UPPER_ROM_BEGIN && ga_config.upper_rom_enable)
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{
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// printf("At program counter %x, Z80 read from address %x in BASIC ROM\n", CPU.PC.W, Addr);
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return gb_rom_464_1[Addr - 0xC000];
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}
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else
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{
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// printf("At program counter %x, Z80 read from address %x in RAM\n", CPU.PC.W, Addr);
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return RAM[Addr];
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}
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}
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@ -28,40 +28,44 @@ uint8_t char_line_count = 0;
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uint8_t scanline_count = 0;
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uint8_t vertical_adjust_count = 0;
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uint16_t memory_start_addr = 0;
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uint8_t microsec_count_crtc = 0;
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void crtc_step()
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{
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horizontal_count++;
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if(horizontal_count > registers[0])
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if(microsec_count_crtc == 3)
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{
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// horizontal counter is equal to the Horizontal Total Register.
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horizontal_count = 0;
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scanline_count++;
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}
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if(scanline_count > registers[9])
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{
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// The counter for Maximum Raster Address is equal to it.
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// The height of a character is 8 rasters, so when we reach 8 rasters we increment the char line count.
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scanline_count = 0;
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char_line_count++;
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horizontal_count++;
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}
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if(horizontal_count > registers[0])
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{
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// horizontal counter is equal to the Horizontal Total Register.
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horizontal_count = 0;
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scanline_count++;
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}
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if(char_line_count > registers[4])
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{
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// The vertical counter reaches the Vertical Total register.
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char_line_count = 0;
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}
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if(scanline_count > registers[9])
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{
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// The counter for Maximum Raster Address is equal to it.
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// The height of a character is 8 rasters, so when we reach 8 rasters we increment the char line count.
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scanline_count = 0;
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char_line_count++;
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}
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if(char_line_count == 0 && horizontal_count == 0)
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{
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memory_start_addr = ((uint16_t) registers[12] << 8) | registers[13];
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}
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if(char_line_count > registers[4])
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{
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// The vertical counter reaches the Vertical Total register.
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char_line_count = 0;
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}
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if(char_line_count == 0 && horizontal_count == 0)
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{
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memory_start_addr = ((uint16_t) registers[12] << 8) | registers[13];
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}
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}
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microsec_count_crtc = (microsec_count_crtc + 1) % 4;
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}
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uint16_t crtc_generate_addr()
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@ -98,7 +102,7 @@ bool is_vsync_active()
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int8_t char_height = (int8_t) registers[9] + 1;
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int8_t char_lines_counted = (int8_t) char_line_count - registers[7];
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return char_height * char_lines_counted + (int8_t) scanline_count >= 0 &&
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char_height * char_lines_counted + (int8_t) scanline_count <= 16*8;
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char_height * char_lines_counted + (int8_t) scanline_count <= 16;
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}
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@ -8,6 +8,7 @@
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#include "cpc.h"
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struct GAConfig ga_config;
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uint8_t microsecond_count_ga = 0;
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/**
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* Some of the colours are duplicates, because select_pen_colour() uses the least significant
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@ -87,7 +88,6 @@ bool update_interrupts()
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ga_config.interrupt_counter++;
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ga_config.vsync_delay_count++;
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if(ga_config.interrupt_counter == 52)
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{
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//printf("Interrupt generated! \n");
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@ -212,23 +212,29 @@ void address_to_pixels()
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break;
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}
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free(pixels);
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}
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}
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}
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}
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bool ga_step()
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{
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bool interrupt_generated = update_interrupts();
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//if(is_within_display())
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//{
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address_to_pixels();
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//}
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ga_config.hsync_active = is_hsync_active();
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ga_config.vsync_active = is_vsync_active();
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ga_config.wait_signal = microsecond_count_ga == 2;
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return interrupt_generated;
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if(microsecond_count_ga == 3)
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{
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bool interrupt_generated = update_interrupts();
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//if(is_within_display())
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//{
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address_to_pixels();
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//}
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ga_config.hsync_active = is_hsync_active();
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ga_config.vsync_active = is_vsync_active();
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microsecond_count_ga = (microsecond_count_ga + 1) % 4;
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return interrupt_generated;
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}
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microsecond_count_ga = (microsecond_count_ga + 1) % 4;
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return false;
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}
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void select_pen(uint8_t value)
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@ -30,6 +30,7 @@ struct GAConfig {
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bool hsync_active = false;
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bool vsync_active = false;
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uint8_t ram_banking = 0; // unused in CPC 464
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bool wait_signal = true;
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};
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extern struct RGB firmware_palette[27];
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@ -13,44 +13,44 @@
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/** changes to this file. **/
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/*************************************************************/
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static const byte Cycles[256] =
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{
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4,12, 8, 8, 4, 4, 8, 4, 4,12, 8, 8, 4, 4, 8, 4,
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8,12, 8, 8, 4, 4, 8, 4,12,12, 8, 8, 4, 4, 8, 4,
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8,12,16, 8, 4, 4, 8, 4, 8,12,16, 8, 4, 4, 8, 4,
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8,12,16, 8,12,12,12, 4, 8,12,16, 8, 4, 4, 8, 4,
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4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
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4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
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4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
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8, 8, 8, 8, 8, 8, 4, 8, 4, 4, 4, 4, 4, 4, 8, 4,
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4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
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4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
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4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
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4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
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8,12,12,12,12,12, 8,12, 8,12,12, 0,12,20, 8,12,
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8,12,12,12,12,12, 8,12, 8, 4,12,12,12, 0, 8,12,
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8,12,12,20,12,12, 8,12, 8, 4,12, 4,12, 0, 8,12,
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8,12,12, 4,12,12, 8,12, 8, 8,12, 4,12, 0, 8,12
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};
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static const byte Cycles[256] =
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{
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4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
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8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
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7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4,
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7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4,
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4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
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4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
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4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
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7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
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4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
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4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
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4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
|
||||
4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
|
||||
5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11,
|
||||
5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11,
|
||||
5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11,
|
||||
5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11
|
||||
};
|
||||
|
||||
static const byte CyclesCB[256] =
|
||||
{
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
|
||||
8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
|
||||
8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
|
||||
8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8,
|
||||
8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
|
||||
8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8
|
||||
};
|
||||
|
||||
static const byte CyclesED[256] =
|
||||
|
|
@ -59,10 +59,10 @@ static const byte CyclesED[256] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
12,12,16,20, 8,16, 8, 12,12,12,16,20, 0,16, 0, 12,
|
||||
12,12,16,20, 0, 0, 8, 12,12,12,16,20, 0, 0, 8, 12,
|
||||
12,12,16,20, 0, 0, 0,20,12,12,16,20, 0, 0, 0,20,
|
||||
12, 0,16,20, 0, 0, 0, 0,12,12,16,20, 0, 0, 0, 0,
|
||||
12,12,15,20, 8,14, 8, 9,12,12,15,20, 0,14, 0, 9,
|
||||
12,12,15,20, 0, 0, 8, 9,12,12,15,20, 0, 0, 8, 9,
|
||||
12,12,15,20, 0, 0, 0,18,12,12,15,20, 0, 0, 0,18,
|
||||
12, 0,15,20, 0, 0, 0, 0,12,12,15,20, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
16,16,16,16, 0, 0, 0, 0,16,16,16,16, 0, 0, 0, 0,
|
||||
|
|
@ -75,42 +75,42 @@ static const byte CyclesED[256] =
|
|||
|
||||
static const byte CyclesXX[256] =
|
||||
{
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0,16, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0,16, 0, 0, 0, 0, 0, 0,
|
||||
0,16,20,12, 12, 12, 12, 0, 0,16,20,12, 12, 12, 12, 0,
|
||||
0, 0, 0, 0,24,24,20, 0, 0,16, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 12, 12,20, 0, 0, 0, 0, 0, 12, 12,20, 0,
|
||||
0, 0, 0, 0, 12, 12,20, 0, 0, 0, 0, 0, 12, 12,20, 0,
|
||||
12, 12, 12, 12, 12, 12,20, 12, 12, 12, 12, 12, 12, 12,20, 12,
|
||||
20,20,20,20,20,20,20,20, 0, 0, 0, 0, 12, 12,20, 0,
|
||||
0, 0, 0, 0, 12, 12,20, 0, 0, 0, 0, 0, 12, 12,20, 0,
|
||||
0, 0, 0, 0, 12, 12,20, 0, 0, 0, 0, 0, 12, 12,20, 0,
|
||||
0, 0, 0, 0, 12, 12,20, 0, 0, 0, 0, 0, 12, 12,20, 0,
|
||||
0, 0, 0, 0, 12, 12,20, 0, 0, 0, 0, 0, 12, 12,20, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
|
||||
0,14,20,10, 9, 9, 9, 0, 0,15,20,10, 9, 9, 9, 0,
|
||||
0, 0, 0, 0,23,23,19, 0, 0,15, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
|
||||
0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
|
||||
9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9,
|
||||
19,19,19,19,19,19,19,19, 0, 0, 0, 0, 9, 9,19, 0,
|
||||
0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
|
||||
0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
|
||||
0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
|
||||
0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0,16, 0,24, 0,16, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0,12, 0, 0, 0, 0, 0, 0
|
||||
0,14, 0,23, 0,15, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0,10, 0, 0, 0, 0, 0, 0
|
||||
};
|
||||
|
||||
static const byte CyclesXXCB[256] =
|
||||
{
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
|
||||
20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
|
||||
20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
|
||||
20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0,
|
||||
0, 0, 0, 0, 0, 0,24, 0, 0, 0, 0, 0, 0, 0,24, 0
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
|
||||
0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0
|
||||
};
|
||||
|
||||
static const byte ZSTable[256] =
|
||||
|
|
|
|||
|
|
@ -495,6 +495,7 @@ void ResetZ80(Z80 *R, register int Cycles)
|
|||
R->ICount = R->IPeriod;
|
||||
R->IRequest = INT_NONE;
|
||||
R->IBackup = 0;
|
||||
R->wait = false;
|
||||
|
||||
JumpZ80(R->PC.W);
|
||||
}
|
||||
|
|
@ -507,48 +508,55 @@ void ResetZ80(Z80 *R, register int Cycles)
|
|||
#ifdef EXECZ80
|
||||
int ExecZ80(register Z80 *R, register int RunCycles) //
|
||||
{
|
||||
register byte I;
|
||||
register pair J;
|
||||
|
||||
for(R->ICount=RunCycles;;)
|
||||
if(!R->wait)
|
||||
{
|
||||
while(R->ICount>0)
|
||||
register byte I;
|
||||
register pair J;
|
||||
|
||||
for(R->ICount=RunCycles;;)
|
||||
{
|
||||
while(R->ICount>0)
|
||||
{
|
||||
#ifdef DEBUG
|
||||
/* Turn tracing on when reached trap address */
|
||||
if(R->PC.W==R->Trap) R->Trace=1;
|
||||
/* Call single-step debugger, exit if requested */
|
||||
if(R->Trace)
|
||||
if(!DebugZ80(R)) return(R->ICount);
|
||||
/* Turn tracing on when reached trap address */
|
||||
if(R->PC.W==R->Trap) R->Trace=1;
|
||||
/* Call single-step debugger, exit if requested */
|
||||
if(R->Trace)
|
||||
if(!DebugZ80(R)) return(R->ICount);
|
||||
#endif
|
||||
|
||||
/* Read opcode and count cycles */
|
||||
I=OpZ80(R->PC.W++);
|
||||
/* Count cycles */
|
||||
R->ICount-=Cycles[I];
|
||||
/* Interpret opcode */
|
||||
switch(I)
|
||||
{
|
||||
/* Read opcode and count cycles */
|
||||
I=OpZ80(R->PC.W++);
|
||||
/* Count cycles */
|
||||
R->ICount-=Cycles[I];
|
||||
/* Interpret opcode */
|
||||
switch(I)
|
||||
{
|
||||
#include "Codes.h"
|
||||
case PFX_CB: CodesCB(R);break;
|
||||
case PFX_ED: CodesED(R);break;
|
||||
case PFX_FD: CodesFD(R);break;
|
||||
case PFX_DD: CodesDD(R);break;
|
||||
case PFX_CB: CodesCB(R);break;
|
||||
case PFX_ED: CodesED(R);break;
|
||||
case PFX_FD: CodesFD(R);break;
|
||||
case PFX_DD: CodesDD(R);break;
|
||||
}
|
||||
|
||||
/* Unless we have come here after EI, exit */
|
||||
if(!(R->IFF&IFF_EI)) return(R->ICount);
|
||||
else
|
||||
{
|
||||
/* Done with AfterEI state */
|
||||
R->IFF=(R->IFF&~IFF_EI)|IFF_1;
|
||||
/* Restore the ICount */
|
||||
R->ICount+=R->IBackup-1;
|
||||
/* Interrupt CPU if needed */
|
||||
if((R->IRequest!=INT_NONE)&&(R->IRequest!=INT_QUIT)) IntZ80(R,R->IRequest);
|
||||
}
|
||||
|
||||
/* Unless we have come here after EI, exit */
|
||||
if(!(R->IFF&IFF_EI)) return(R->ICount);
|
||||
else
|
||||
{
|
||||
/* Done with AfterEI state */
|
||||
R->IFF=(R->IFF&~IFF_EI)|IFF_1;
|
||||
/* Restore the ICount */
|
||||
R->ICount+=R->IBackup-1;
|
||||
/* Interrupt CPU if needed */
|
||||
if((R->IRequest!=INT_NONE)&&(R->IRequest!=INT_QUIT)) IntZ80(R,R->IRequest);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return RunCycles;
|
||||
}
|
||||
}
|
||||
#endif /* EXECZ80 */
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#define Z80_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
|
||||
#define EXECZ80 // run a few cycles
|
||||
|
|
@ -101,6 +102,7 @@ typedef struct
|
|||
word Trap; /* Set Trap to address to trace from */
|
||||
byte Trace; /* Set Trace=1 to start tracing */
|
||||
void *User; /* Arbitrary user data (ID,RAM*,etc.) */
|
||||
bool wait;
|
||||
} Z80;
|
||||
|
||||
/** ResetZ80() ***********************************************/
|
||||
|
|
|
|||
Plik diff jest za duży
Load Diff
Ładowanie…
Reference in New Issue