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fix line break issue at locomotive word

pull/31/head
AlinTigaeru 2023-03-08 18:42:52 +00:00
rodzic 68c26ba800
commit 324adc5bd8
5 zmienionych plików z 37 dodań i 63 usunięć
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26
MCUME_pico/picocpc/cpc.cpp
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@ -44,9 +44,9 @@ void write_to_bitstream(char pixel)
x = position % WIDTH;
y = position / WIDTH;
bitstream[x + WIDTH * y] = pixel;
bitstream[x + y * WIDTH] = VGA_RGB(firmware_palette[hardware_colours[pixel]].R,
firmware_palette[hardware_colours[pixel]].G,
firmware_palette[hardware_colours[pixel]].B);
position++;
if(position == WIDTH * HEIGHT)
@ -90,16 +90,16 @@ void out_z80(uint16_t Port, uint8_t Value)
{
if(!(Port & 0x8000)) write_gate_array(Value); // The Gate Array is selected when bit 15 is set to 0.
if(!(Port & 0x4000)) write_crt_controller(Port, Value); // The CRTC is selected when bit 14 is set to 0.
if(!(Port & 0x2000))
{
// upper rom bank number. ROM banking needs to be done regardless of CPC model
// The Upper ROM Bank Number (in range of 0x00..0xFF) to be mapped to memory at 0xC000..0xFFFF
// if(!(Port & 0x2000))
// {
// // upper rom bank number. ROM banking needs to be done regardless of CPC model
// // The Upper ROM Bank Number (in range of 0x00..0xFF) to be mapped to memory at 0xC000..0xFFFF
// byte req_bank_number = Value & 15;
// if(ga_config.upper_rom_enable)
// {
// }
}
// // byte req_bank_number = Value & 15;
// // if(ga_config.upper_rom_enable)
// // {
// // }
// }
}
uint8_t in_z80(uint16_t Port)
@ -124,7 +124,7 @@ void cpc_Init(void)
pins = z80_init(&CPU);
memset(RAM, 0, sizeof(RAM));
vsync_wait = true;
//vsync_wait = true;
}
/**

2
MCUME_pico/picocpc/cpc.h
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@ -11,6 +11,8 @@ extern unsigned char* bitstream;
extern struct GAConfig ga_config;
extern bool vsync_wait;
#define VGA_RGB(r,g,b) ( (((r>>5)&0x07)<<5) | (((g>>5)&0x07)<<2) | (((b>>6)&0x3)<<0) )
extern void write_to_bitstream(char pixel);
extern void draw_vsync();
extern void cpc_Init(void);

12
MCUME_pico/picocpc/crtc.cpp
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@ -5,7 +5,7 @@
#include "crtc.h"
uint8_t registers[16] = {
0, // horizontal_total
64, // horizontal_total
0, // horitzontal_displayed
0, // horizontal_sync_position
0, // horizontal_and_vertical_sync_widths -> VVVVHHHH, so bits 0-3 correspond to hsync width, 4-7 to vsync.
@ -80,7 +80,6 @@ uint16_t crtc_generate_addr()
uint16_t bits_0_10 = (current_memory_addr & 0b0000001111111111) << 1;
uint16_t bits_11_13 = (scanline_count & 0b0000000000000111) << 11;
uint16_t bits_14_15 = (current_memory_addr & 0b0011000000000000) << 2;
return bits_14_15 | bits_11_13 | bits_0_10;
}
@ -94,18 +93,17 @@ bool is_hsync_active()
// HSYNC is active if the horizontal counter is in the
// "horizontal_and_vertical_sync_widths"-defined width starting from the horizontal_sync_position register.
return horizontal_count >= registers[2] &&
horizontal_count <= registers[2] + (registers[3] & 0b1111);
horizontal_count < registers[2] + (registers[3] & 0b1111);
}
bool is_vsync_active()
{
int8_t char_height = (int8_t) registers[9] + 1;
const uint8_t char_height = registers[9] + 1;
int8_t char_lines_counted = (int8_t) char_line_count - registers[7];
return char_height * char_lines_counted + (int8_t) scanline_count >= 0 &&
char_height * char_lines_counted + (int8_t) scanline_count <= 16;
return char_height * char_lines_counted + scanline_count >= 0 &&
char_height * char_lines_counted + scanline_count < 16 * 8;
}
void write_crt_controller(unsigned short address, uint8_t value)
{
switch(address & 0xFF00)

59
MCUME_pico/picocpc/ga.cpp
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@ -125,17 +125,12 @@ char ga_rgb_to_vga(uint8_t r, uint8_t g, uint8_t b)
void address_to_pixels()
{
if(!ga_config.vsync_active && is_vsync_active())
if(ga_config.vsync_active && !is_vsync_active())
{
vsync_wait = false;
return;
}
// if(ga_config.hsync_active || ga_config.vsync_active)
// {
// // need to output border/black somehow. how to do that considering the 320x200 buffer?
// return;
// }
if(!is_within_display())
{
return;
@ -146,7 +141,6 @@ void address_to_pixels()
uint16_t address = crtc_generate_addr() + i;
uint8_t encodedByte = RAM[address];
uint8_t pixel0, pixel1, pixel2, pixel3;
uint8_t* pixels = (uint8_t*) calloc(4, 8*sizeof(uint8_t));
switch(ga_config.screen_mode)
{
case 0:
@ -158,15 +152,8 @@ void address_to_pixels()
(encodedByte & 0x04) >> 1 |
(encodedByte & 0x10) >> 2 |
(encodedByte & 0x01) << 3;
pixels[0] = pixel0;
pixels[1] = pixel1;
for(int pixelIdx = 0; pixelIdx < 2; pixelIdx++)
{
write_to_bitstream(ga_rgb_to_vga(firmware_palette[hardware_colours[ga_config.pen_colours[pixels[pixelIdx]]]].R,
firmware_palette[hardware_colours[ga_config.pen_colours[pixels[pixelIdx]]]].G,
firmware_palette[hardware_colours[ga_config.pen_colours[pixels[pixelIdx]]]].B));
}
write_to_bitstream(ga_config.pen_colours[pixel0]);
write_to_bitstream(ga_config.pen_colours[pixel1]);
break;
case 1:
pixel0 = (encodedByte & 0x80) >> 7 |
@ -177,30 +164,20 @@ void address_to_pixels()
(encodedByte & 0x20) >> 5;
pixel3 = (encodedByte & 0x10) >> 4 |
(encodedByte & 0x01) << 1;
pixels[0] = pixel0;
pixels[1] = pixel1;
pixels[2] = pixel2;
pixels[3] = pixel3;
for(int pixelIdx = 0; pixelIdx < 4; pixelIdx++)
{
write_to_bitstream(ga_rgb_to_vga(firmware_palette[hardware_colours[ga_config.pen_colours[pixels[pixelIdx]]]].R,
firmware_palette[hardware_colours[ga_config.pen_colours[pixels[pixelIdx]]]].G,
firmware_palette[hardware_colours[ga_config.pen_colours[pixels[pixelIdx]]]].B));
}
write_to_bitstream(ga_config.pen_colours[pixel0]);
write_to_bitstream(ga_config.pen_colours[pixel1]);
write_to_bitstream(ga_config.pen_colours[pixel2]);
write_to_bitstream(ga_config.pen_colours[pixel3]);
break;
case 2:
uint8_t pixel;
for (int color = 0; color < 8; color++)
{
pixel = (encodedByte >> 7 - color) & 1;
write_to_bitstream(ga_rgb_to_vga(firmware_palette[hardware_colours[ga_config.pen_colours[pixel]]].R,
firmware_palette[hardware_colours[ga_config.pen_colours[pixel]]].G,
firmware_palette[hardware_colours[ga_config.pen_colours[pixel]]].B));
write_to_bitstream(ga_config.pen_colours[pixel]);
}
break;
}
free(pixels);
}
}
}
@ -211,18 +188,18 @@ bool ga_step()
if(microsecond_count_ga == 3)
{
bool interrupt_generated = update_interrupts();
//if(is_within_display())
//{
address_to_pixels();
//}
ga_config.hsync_active = is_hsync_active();
ga_config.vsync_active = is_vsync_active();
microsecond_count_ga = (microsecond_count_ga + 1) % 4;
return interrupt_generated;
}
microsecond_count_ga = (microsecond_count_ga + 1) % 4;
return false;
else
{
microsecond_count_ga = (microsecond_count_ga + 1) % 4;
return false;
}
}
void select_pen(uint8_t value)
@ -249,7 +226,7 @@ void select_pen_colour(uint8_t value)
void rom_and_screen_mgmt(uint8_t value)
{
if(!ga_config.hsync_active && is_hsync_active())
if(ga_config.hsync_active && !is_hsync_active())
{
// Screen mode config, dictated by the least significant 2 bits.
// Effective at next line.
@ -278,9 +255,7 @@ void rom_and_screen_mgmt(uint8_t value)
if ((value >> 3) & 0b1) ga_config.upper_rom_enable = false; else ga_config.upper_rom_enable = true;
// Interrupt delay control.
if ((value >> 4) & 0b1) {
ga_config.interrupt_counter = 0;
}
if ((value >> 4) & 0b1) ga_config.interrupt_counter = 0;
}
/** Bit 7 Bit 6 Function

1
MCUME_pico/picocpc/ga.h
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@ -13,7 +13,6 @@ void select_pen_colour(uint8_t value);
void rom_and_screen_mgmt(uint8_t value);
#define PEN_NUMBER 17 // Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.
#define VGA_RGB(r,g,b) ( (((r>>5)&0x07)<<5) | (((g>>5)&0x07)<<2) | (((b>>6)&0x3)<<0) )
struct RGB {
uint8_t R, G, B;