kopia lustrzana https://github.com/M17-Project/M17_spec
BERT proposal update with pictures.
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###############
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Data Link Layer
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===============
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###############
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The Data Link layer is split into three modes:
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* Packet mode
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@ -30,7 +31,7 @@ As is the convention with other networking protocols, all values are
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encoded in big endian byte order.
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Stream Mode
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-----------
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===========
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In Stream Mode, an *indefinite* amount of payload data is sent continuously without breaks in the
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physical layer. The *stream* is broken up into parts, called *frames* to not confuse them with *packets* sent
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@ -267,7 +268,7 @@ message and then 16 zero bits to the CRC algorithm.
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- 0x1C31
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Packet Mode
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-----------
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===========
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In *packet mode*, a finite amount of payload data (for example – text
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messages or application layer data) is wrapped with a packet, sent
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@ -428,14 +429,14 @@ sent, followed by an indefinite sequence of BERT frames. Notably, a link setup
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be sent in BERT mode.
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Purpose
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-------
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~~~~~~~
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The primary purpose of defining a bit error rate testing standard for M17 is to enhance
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interoperability testing across M17 hardware and software implementations, and to aid in the
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configuration and tuning of ad hoc communications equipment common in amateur radio.
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BERT Frame
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----------
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~~~~~~~~~~
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Each BERT frame is preceeded by the BERT sync word, 0xDF55.
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@ -447,7 +448,25 @@ frames even with a PRBS generator with a relatively short period.
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The PRBS uses the ITU standard PRBS9 polynomial :math:`x^{9}+x^{5}+1`
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.. figure:: ../images/prbs9.png
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This is the traditional form for a linear feedback shift register (LFSR) used
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to generate a psuedorandom binary sequence.
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.. figure:: ../images/m17-traditional-lfsr.png
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However, the M17 LFSR is a slightly different. The M17 PRBS9 uses the
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generated bit as the output bit rather than the high-bit before the shift.
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.. figure:: ../images/m17-prbs9.png
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This will result in the same sequence, just shifted by nine bits.
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.. math:: {M17\_PRBS}_{n} = {PRBS9}_{n + 9}
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The reason for this is that it allows for easier synchronization. This is
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equivalent to a multiplicative scrambler (a self-synchronizing scrambler)
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fed with a stream of 0s.
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.. figure:: ../images/m17-equivalent-scrambler.png
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.. code-block:: c++
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@ -501,7 +520,7 @@ This provides the same error correction coding used for the stream payload.
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- Payload
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BERT Receiver
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-------------
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~~~~~~~~~~~~~
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The receiver detects the frame is a BERT frame based on the sync word
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received. If the PRBS9 generator is reset at this point, the sender and
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@ -509,15 +528,19 @@ receiver should be synchonized at the start. This, however, is not common
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nor is it required. PRBS generators can be self-synchronizing.
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Synchronization
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~~~~~~~~~~~~~~~
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---------------
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The receiver will synchronize the PRBS by first XORing the received bit
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with the LFSR taps. If the result of the XOR is a 1, it is an error (the
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expected feedback bit and the input do not match) and the sync count is
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reset. The received bit is then shifted into the LFSR state register in
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place of the feedback bit. Once a sequence of eighteen (18) consecutive
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good bits are recovered (18 is twice the length of the LFSR), the stream
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is considered syncronized.
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reset. The received bit is then also shifted into the LFSR state register.
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Once a sequence of eighteen (18) consecutive good bits are recovered (twice
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the length of the LFSR), the stream is considered syncronized.
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.. figure:: ../images/m17-prbs9-sync.png
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During synchronization, bits received and bit errors are not counted towards
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the overall bit error rate.
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.. code-block:: c++
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@ -546,10 +569,13 @@ is considered syncronized.
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};
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Counting Bit Errors
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~~~~~~~~~~~~~~~~~~~
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-------------------
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After synchronization, each bit that does not match the output of the
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free-running LFSR is counted as a bit error.
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After synchronization, BERT mode switchs to error-counting mode, where the
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received bits are compared to a free-running PRBS9 generator. Each bit that
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does not match the output of the free-running LFSR is counted as a bit error.
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.. figure:: ../images/m17-prbs9-validation.png
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.. code-block:: c++
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@ -573,7 +599,7 @@ free-running LFSR is counted as a bit error.
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};
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Resynchronization
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~~~~~~~~~~~~~~~~~
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-----------------
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The receiver must keep track of the number of bit errors over a period of
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128 bits. If more than 18 bit errors occur, the synchronization process
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@ -584,7 +610,7 @@ Bits received and errors which occur during resynchronization are not counted
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towards the bit error rate.
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References
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----------
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~~~~~~~~~~
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- http://www.itu.int/rec/T-REC-O.150-199210-S
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- http://www.pldworld.com/_hdl/5/-thorsten-gaertner.de/vhdl/PRBS.pdf
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