kopia lustrzana https://github.com/RobertGawron/IonizationChamber
cleanup
RobertGawron
rodzic
5df277b93a
commit
3520c59edf
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@ -1,5 +1,5 @@
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# Use an official Ubuntu as a base image
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FROM ubuntu:20.04 AS build
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FROM ubuntu:25.04 AS build
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# Set environment variables to prevent interaction during installation
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ENV DEBIAN_FRONTEND=noninteractive
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@ -11,84 +11,8 @@ RUN apt-get update && apt-get install -y \
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cmake \
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pkg-config \
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libusb-1.0-0-dev \
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&& rm -rf /var/lib/apt/lists/*
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# Install stm8flash
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RUN git clone https://github.com/vdudouyt/stm8flash.git
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RUN cd stm8flash && make -j$(nproc)
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# Use another Ubuntu image for runtime
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FROM ubuntu:20.04 AS runtime
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# Set environment variables to prevent interaction during installation
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ENV DEBIAN_FRONTEND=noninteractive
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# Install runtime dependencies
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RUN apt-get update && apt-get install -y \
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libusb-1.0-0 \
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sdcc \
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build-essential \
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cmake \
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git \
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make \
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pkg-config \
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libusb-1.0-0-dev \
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screen \
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doxygen \
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uncrustify \
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python3-pip \
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poppler-utils \
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cppcheck \
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r-base-core \
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shellcheck \
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dos2unix \
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&& rm -rf /var/lib/apt/lists/*
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RUN apt-get update && apt-get install -y \
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python3-venv \
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&& rm -rf /var/lib/apt/lists/*
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# Copy the stm8flash binary from the build stage
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COPY --from=build /stm8flash/stm8flash /usr/bin/
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# Install flake8 in a Python virtual environment
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RUN python3 -m venv /workspace/venv && \
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/workspace/venv/bin/pip install --upgrade pip && \
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/workspace/venv/bin/pip install flake8 flake8-html pyserial CodeChecker coverxygen
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# Install R libraries
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RUN R -e "install.packages('latticeExtra', repos='http://cran.rstudio.com/')"
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RUN R -e "install.packages('gridExtra', repos='http://cran.rstudio.com/')"
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RUN R -e "install.packages('Hmisc', repos='http://cran.rstudio.com/')"
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# Create workspace directory and set it as the working directory
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RUN mkdir -p /workspace/build
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WORKDIR /workspace/build
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RUN apt-get update && apt-get install -y \
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libcunit1-dev \
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libcmocka-dev \
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tree \
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vim \
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lcov \
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gcovr \
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clang
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RUN /workspace/venv/bin/pip install --upgrade pip && \
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/workspace/venv/bin/pip install \
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prospector \
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vjunit
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RUN apt-get update && apt-get install -y \
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uncrustify
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RUN apt-get update && apt-get install -y \
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clang-tidy
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RUN apt-get update && apt-get install -y \
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openocd
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# Command to run the container
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CMD ["bash"]
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@ -29,7 +29,11 @@ docker-compose exec ionizationchamber bash
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End of Work
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To log out from the Docker container, press Ctrl+D.
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To stop and clean up the Docker environment, use:
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To stop and clean up the Docker
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environment, use:
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docker-compose down --remove-orphans
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@ -274,5 +278,87 @@ stm8flash -c stlinkv2 -p stm8s003f3 -w /workspace/firmwarev3/IonizationChamber.e
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------------
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openocd -f interface/stlink.cfg -f target/stm8s.cfg -c "program /workspace/firmwarev3/IonizationChamber.elf verify reset exit"
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openocd -f interface/stlink.cfg -f target/stm8s.cfg -c "program IonizationChamber.elf verify reset exit"
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-------------
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SWITCH TO MAKFILE
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openocd -f interface/stlink.cfg -f target/stm8s.cfg -c "init; reset halt; load_image IonizationChamber.elf 0x8000; reset halt; exit"
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openocd \
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-f interface/stlink.cfg \
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-f target/stm8s.cfg \
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-c "init; reset halt; load_image /workspace/Software/Firmware/IonizationChamber.elf 0x8000; reset halt"
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stm8-gdb /workspace/Software/Firmware/IonizationChamber.elf \
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-ex "set architecture stm8" \
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-ex "target extended-remote :3333"
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for sdcc to have elf
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sudo apt install build-essential libboost-all-dev bison flex texinfo zlib1g-dev
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we dont have elf possibility in this shit
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need to update docker for ubuntu version
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sudo apt install software-properties-common
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root@faedc67c011c:/workspace/Software/Firmware# add-apt-repository ppa:mhier/libboost-latest
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it all failed try again:
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sudo add-apt-repository ppa:mhier/libboost-latest
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sudo apt update
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Step 2: Install the desired Boost version (e.g., 1.83)
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sudo apt install libboost1.83-dev
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and then faild, disable other chips:
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./configure --enable-stm8 --disable-hc08 --disable-s08 --disable-mcs51 --disable-z80 --disable-z180 --disable-r2k --disable-r3ka --disable-gbz80 --disable-tlcs90 --disable-ds390 --disable-ds400 --disable-pic14 --disable-pic16 --disable-ucsim
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===========================
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give up, start new docker
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apt install autoconf automake libtool
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git clone git@github.com:ntfreak/openocd.git
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cd openocd
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./bootstrap
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./configure
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make -j24
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make install
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what?
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git config --global --add safe.directory /workspace/Software/downloads/openocd
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./configure --disable-werror
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-- shit didint work
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apt-get install texinfo
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ok make sure the link is ok to the gz file
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CPPFLAGS="-D_XOPEN_SOURCE=1"
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@ -29,14 +29,13 @@
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/* Includes ------------------------------------------------------------------*/
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#include "stm8_it.h"
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#include "application_builder.h"
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#include "user_interface.h"
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#include "app_builder.h"
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/** @addtogroup Template_Project
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* @{
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*/
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#include "application_builder.h" // Include the flag declaration
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extern unsigned char timer_flag;
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/* Private typedef -----------------------------------------------------------*/
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@ -241,12 +240,13 @@ INTERRUPT_HANDLER(TIM1_UPD_OVF_TRG_BRK_IRQHandler, 11)
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USER_INTERFACE_COLLECTING_DATA_MSG,
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USER_INTERFACE_DISABLE);
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*/
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/*
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user_interface_update_message(
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USER_INTERFACE_COLLECTING_DATA_MSG,
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USER_INTERFACE_ENABLE);
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app_tick_flag = 1;
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*/
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xx app_builder_tick();
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// app_tick_flag = 1;
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TIM1_ClearITPendingBit(TIM1_IT_UPDATE);
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}
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@ -191,10 +191,7 @@
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#define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x02) /*!< [23:16] sub1 version */
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#define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */
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#define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */
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#define __STM8S_STDPERIPH_VERSION ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\
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|(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\
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|(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\
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|(__STM8S_STDPERIPH_VERSION_RC))
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#define __STM8S_STDPERIPH_VERSION ((__STM8S_STDPERIPH_VERSION_MAIN << 24) | (__STM8S_STDPERIPH_VERSION_SUB1 << 16) | (__STM8S_STDPERIPH_VERSION_SUB2 << 8) | (__STM8S_STDPERIPH_VERSION_RC))
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/******************************************************************************/
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@ -239,15 +236,31 @@ typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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typedef enum
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{
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FALSE = 0,
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TRUE = !FALSE
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} bool;
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typedef enum {FALSE = 0, TRUE = !FALSE} bool;
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus,
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ITStatus, BitStatus, BitAction;
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typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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#define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
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typedef enum
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{
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ERROR = 0,
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SUCCESS = !ERROR
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} ErrorStatus;
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#define U8_MAX (255)
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#define S8_MAX (127)
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@ -281,8 +294,7 @@ typedef struct GPIO_struct
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__IO uint8_t DDR; /*!< Data Direction Register */
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__IO uint8_t CR1; /*!< Configuration Register 1 */
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__IO uint8_t CR2; /*!< Configuration Register 2 */
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}
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GPIO_TypeDef;
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} GPIO_TypeDef;
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/** @addtogroup GPIO_Registers_Reset_Value
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* @{
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@ -342,8 +354,7 @@ GPIO_TypeDef;
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__IO uint8_t AWSRL; /*!< ADC1 watchdog status register low */
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__IO uint8_t AWCRH; /*!< ADC1 watchdog control register high */
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__IO uint8_t AWCRL; /*!< ADC1 watchdog control register low */
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}
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ADC1_TypeDef;
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} ADC1_TypeDef;
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/** @addtogroup ADC1_Registers_Reset_Value
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* @{
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@ -405,8 +416,7 @@ GPIO_TypeDef;
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__IO uint8_t DRL; /*!< ADC2 Data low */
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__IO uint8_t TDRH; /*!< ADC2 Schmitt trigger disable register high */
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__IO uint8_t TDRL; /*!< ADC2 Schmitt trigger disable register low */
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}
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ADC2_TypeDef;
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} ADC2_TypeDef;
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/** @addtogroup ADC2_Registers_Reset_Value
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* @{
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@ -450,8 +460,7 @@ typedef struct AWU_struct
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__IO uint8_t CSR; /*!< AWU Control status register */
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__IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */
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__IO uint8_t TBR; /*!< AWU Time base selection register */
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}
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AWU_TypeDef;
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} AWU_TypeDef;
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/** @addtogroup AWU_Registers_Reset_Value
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* @{
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@ -488,8 +497,7 @@ AWU_TypeDef;
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typedef struct BEEP_struct
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{
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__IO uint8_t CSR; /*!< BEEP Control status register */
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}
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BEEP_TypeDef;
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} BEEP_TypeDef;
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/** @addtogroup BEEP_Registers_Reset_Value
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* @{
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@ -529,8 +537,7 @@ typedef struct CLK_struct
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uint8_t RESERVED1; /*!< Reserved byte */
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__IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */
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__IO uint8_t SWIMCCR; /*!< SWIM clock control register */
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}
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CLK_TypeDef;
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} CLK_TypeDef;
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/** @addtogroup CLK_Registers_Reset_Value
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* @{
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@ -651,8 +658,7 @@ typedef struct TIM1_struct
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__IO uint8_t BKR; /*!< Break Register */
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__IO uint8_t DTR; /*!< dead-time register */
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__IO uint8_t OISR; /*!< Output idle register */
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}
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TIM1_TypeDef;
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} TIM1_TypeDef;
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/** @addtogroup TIM1_Registers_Reset_Value
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* @{
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@ -856,8 +862,7 @@ typedef struct TIM2_struct
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__IO uint8_t CCR2L; /*!< capture/compare register 2 low */
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__IO uint8_t CCR3H; /*!< capture/compare register 3 high */
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__IO uint8_t CCR3L; /*!< capture/compare register 3 low */
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}
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TIM2_TypeDef;
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} TIM2_TypeDef;
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/** @addtogroup TIM2_Registers_Reset_Value
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* @{
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@ -976,8 +981,7 @@ typedef struct TIM3_struct
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__IO uint8_t CCR1L; /*!< capture/compare register 1 low */
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__IO uint8_t CCR2H; /*!< capture/compare register 2 high */
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__IO uint8_t CCR2L; /*!< capture/compare register 2 low */
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}
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TIM3_TypeDef;
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} TIM3_TypeDef;
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/** @addtogroup TIM3_Registers_Reset_Value
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* @{
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@ -1076,8 +1080,7 @@ typedef struct TIM4_struct
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__IO uint8_t CNTR; /*!< counter register */
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__IO uint8_t PSCR; /*!< prescaler register */
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__IO uint8_t ARR; /*!< auto-reload register */
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}
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TIM4_TypeDef;
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} TIM4_TypeDef;
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/** @addtogroup TIM4_Registers_Reset_Value
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* @{
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@ -1276,8 +1279,7 @@ typedef struct TIM6_struct
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__IO uint8_t CNTR; /*!< counter register */
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__IO uint8_t PSCR; /*!< prescaler register */
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__IO uint8_t ARR; /*!< auto-reload register */
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}
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TIM6_TypeDef;
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} TIM6_TypeDef;
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/** @addtogroup TIM6_Registers_Reset_Value
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* @{
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*/
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@ -1350,8 +1352,7 @@ typedef struct I2C_struct
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__IO uint8_t CCRH; /*!< I2C clock control register high */
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__IO uint8_t TRISER; /*!< I2C maximum rise time register */
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uint8_t RESERVED2; /*!< Reserved byte */
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}
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I2C_TypeDef;
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} I2C_TypeDef;
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/** @addtogroup I2C_Registers_Reset_Value
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* @{
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@ -1450,8 +1451,7 @@ typedef struct ITC_struct
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__IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */
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__IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */
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__IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */
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}
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ITC_TypeDef;
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} ITC_TypeDef;
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/** @addtogroup ITC_Registers_Reset_Value
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* @{
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@ -1482,8 +1482,7 @@ typedef struct EXTI_struct
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{
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__IO uint8_t CR1; /*!< External Interrupt Control Register for PORTA to PORTD */
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__IO uint8_t CR2; /*!< External Interrupt Control Register for PORTE and TLI */
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}
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EXTI_TypeDef;
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} EXTI_TypeDef;
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/** @addtogroup EXTI_Registers_Reset_Value
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* @{
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@ -1512,8 +1511,6 @@ EXTI_TypeDef;
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* @}
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*/
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/*----------------------------------------------------------------------------*/
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/**
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* @brief FLASH program and Data memory (FLASH)
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@ -1532,8 +1529,7 @@ typedef struct FLASH_struct
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__IO uint8_t PUKR; /*!< Flash program memory unprotection register */
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uint8_t RESERVED3; /*!< Reserved byte */
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__IO uint8_t DUKR; /*!< Data EEPROM unprotection register */
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}
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FLASH_TypeDef;
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} FLASH_TypeDef;
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/** @addtogroup FLASH_Registers_Reset_Value
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* @{
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@ -1606,8 +1602,7 @@ typedef struct OPT_struct
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uint8_t RESERVED2; /*!< Reserved Option byte*/
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__IO uint8_t OPT7; /*!< Option byte 7: flash wait states */
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__IO uint8_t NOPT7; /*!< Complementary Option byte 7 */
|
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}
|
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OPT_TypeDef;
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} OPT_TypeDef;
|
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|
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/*----------------------------------------------------------------------------*/
|
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/**
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@ -1619,8 +1614,7 @@ typedef struct IWDG_struct
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__IO uint8_t KR; /*!< Key Register */
|
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__IO uint8_t PR; /*!< Prescaler Register */
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__IO uint8_t RLR; /*!< Reload Register */
|
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}
|
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IWDG_TypeDef;
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} IWDG_TypeDef;
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||||
|
||||
/** @addtogroup IWDG_Registers_Reset_Value
|
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* @{
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@ -1642,8 +1636,7 @@ typedef struct WWDG_struct
|
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{
|
||||
__IO uint8_t CR; /*!< Control Register */
|
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__IO uint8_t WR; /*!< Window Register */
|
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}
|
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WWDG_TypeDef;
|
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} WWDG_TypeDef;
|
||||
|
||||
/** @addtogroup WWDG_Registers_Reset_Value
|
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* @{
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@ -1679,8 +1672,7 @@ WWDG_TypeDef;
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typedef struct RST_struct
|
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{
|
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__IO uint8_t SR; /*!< Reset status register */
|
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}
|
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RST_TypeDef;
|
||||
} RST_TypeDef;
|
||||
|
||||
/** @addtogroup RST_Registers_Bits_Definition
|
||||
* @{
|
||||
|
|
@ -1711,8 +1703,7 @@ typedef struct SPI_struct
|
|||
__IO uint8_t CRCPR; /*!< SPI CRC polynomial register */
|
||||
__IO uint8_t RXCRCR; /*!< SPI Rx CRC register */
|
||||
__IO uint8_t TXCRCR; /*!< SPI Tx CRC register */
|
||||
}
|
||||
SPI_TypeDef;
|
||||
} SPI_TypeDef;
|
||||
|
||||
/** @addtogroup SPI_Registers_Reset_Value
|
||||
* @{
|
||||
|
|
@ -1785,8 +1776,7 @@ typedef struct UART1_struct
|
|||
__IO uint8_t CR5; /*!< UART1 control register 5 */
|
||||
__IO uint8_t GTR; /*!< UART1 guard time register */
|
||||
__IO uint8_t PSCR; /*!< UART1 prescaler register */
|
||||
}
|
||||
UART1_TypeDef;
|
||||
} UART1_TypeDef;
|
||||
|
||||
/** @addtogroup UART1_Registers_Reset_Value
|
||||
* @{
|
||||
|
|
@ -1884,8 +1874,7 @@ typedef struct UART2_struct
|
|||
__IO uint8_t CR6; /*!< UART1 control register 6 */
|
||||
__IO uint8_t GTR; /*!< UART1 guard time register */
|
||||
__IO uint8_t PSCR; /*!< UART1 prescaler register */
|
||||
}
|
||||
UART2_TypeDef;
|
||||
} UART2_TypeDef;
|
||||
|
||||
/** @addtogroup UART2_Registers_Reset_Value
|
||||
* @{
|
||||
|
|
@ -1971,7 +1960,6 @@ UART2_TypeDef;
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief LIN Universal Asynchronous Receiver Transmitter (UART3)
|
||||
|
|
@ -1989,8 +1977,7 @@ typedef struct UART3_struct
|
|||
__IO uint8_t CR4; /*!< control register 4 */
|
||||
uint8_t RESERVED; /*!< Reserved byte */
|
||||
__IO uint8_t CR6; /*!< control register 5 */
|
||||
}
|
||||
UART3_TypeDef;
|
||||
} UART3_TypeDef;
|
||||
|
||||
/** @addtogroup UART3_Registers_Reset_Value
|
||||
* @{
|
||||
|
|
@ -2083,8 +2070,7 @@ typedef struct UART4_struct
|
|||
__IO uint8_t CR6; /*!< UART4 control register 6 */
|
||||
__IO uint8_t GTR; /*!< UART4 guard time register */
|
||||
__IO uint8_t PSCR; /*!< UART4 prescaler register */
|
||||
}
|
||||
UART4_TypeDef;
|
||||
} UART4_TypeDef;
|
||||
|
||||
/** @addtogroup UART4_Registers_Reset_Value
|
||||
* @{
|
||||
|
|
@ -2386,7 +2372,6 @@ typedef struct
|
|||
#define CAN_IER_FOVIE ((uint8_t)0x08)
|
||||
#define CAN_IER_WKUIE ((uint8_t)0x80)
|
||||
|
||||
|
||||
/* CAN diagnostic Register bits */
|
||||
#define CAN_DGR_LBKM ((uint8_t)0x01)
|
||||
#define CAN_DGR_SLIM ((uint8_t)0x02)
|
||||
|
|
@ -2394,7 +2379,6 @@ typedef struct
|
|||
#define CAN_DGR_RX ((uint8_t)0x08)
|
||||
#define CAN_DGR_TXM2E ((uint8_t)0x10)
|
||||
|
||||
|
||||
/* CAN page select Register bits */
|
||||
#define CAN_PSR_PS0 ((uint8_t)0x01)
|
||||
#define CAN_PSR_PS1 ((uint8_t)0x02)
|
||||
|
|
@ -2414,7 +2398,6 @@ typedef struct
|
|||
#define CAN_MIDR1_RTR ((uint8_t)0x20)
|
||||
#define CAN_MIDR1_IDE ((uint8_t)0x40)
|
||||
|
||||
|
||||
/************************* Filter Page ****************************************/
|
||||
|
||||
/* CAN Error Status Register bits */
|
||||
|
|
@ -2530,8 +2513,7 @@ typedef struct
|
|||
typedef struct CFG_struct
|
||||
{
|
||||
__IO uint8_t GCR; /*!< Global Configuration register */
|
||||
}
|
||||
CFG_TypeDef;
|
||||
} CFG_TypeDef;
|
||||
|
||||
/** @addtogroup CFG_Registers_Reset_Value
|
||||
* @{
|
||||
|
|
@ -2715,7 +2697,6 @@ CFG_TypeDef;
|
|||
|
||||
#define DM ((DM_TypeDef *)DM_BaseAddress)
|
||||
|
||||
|
||||
#ifdef USE_STDPERIPH_DRIVER
|
||||
#include "stm8s_conf.h"
|
||||
#endif
|
||||
|
|
@ -2734,23 +2715,69 @@ CFG_TypeDef;
|
|||
#define wfi() _wfi_() /* Wait For Interrupt */
|
||||
#define halt() _halt_() /* Halt */
|
||||
#elif defined(_COSMIC_)
|
||||
#define enableInterrupts() {_asm("rim\n");} /* enable interrupts */
|
||||
#define disableInterrupts() {_asm("sim\n");} /* disable interrupts */
|
||||
#define rim() {_asm("rim\n");} /* enable interrupts */
|
||||
#define sim() {_asm("sim\n");} /* disable interrupts */
|
||||
#define nop() {_asm("nop\n");} /* No Operation */
|
||||
#define trap() {_asm("trap\n");} /* Trap (soft IT) */
|
||||
#define wfi() {_asm("wfi\n");} /* Wait For Interrupt */
|
||||
#define halt() {_asm("halt\n");} /* Halt */
|
||||
#define enableInterrupts() \
|
||||
{ \
|
||||
_asm("rim\n"); \
|
||||
} /* enable interrupts */
|
||||
#define disableInterrupts() \
|
||||
{ \
|
||||
_asm("sim\n"); \
|
||||
} /* disable interrupts */
|
||||
#define rim() \
|
||||
{ \
|
||||
_asm("rim\n"); \
|
||||
} /* enable interrupts */
|
||||
#define sim() \
|
||||
{ \
|
||||
_asm("sim\n"); \
|
||||
} /* disable interrupts */
|
||||
#define nop() \
|
||||
{ \
|
||||
_asm("nop\n"); \
|
||||
} /* No Operation */
|
||||
#define trap() \
|
||||
{ \
|
||||
_asm("trap\n"); \
|
||||
} /* Trap (soft IT) */
|
||||
#define wfi() \
|
||||
{ \
|
||||
_asm("wfi\n"); \
|
||||
} /* Wait For Interrupt */
|
||||
#define halt() \
|
||||
{ \
|
||||
_asm("halt\n"); \
|
||||
} /* Halt */
|
||||
#elif defined(_SDCC_)
|
||||
#define enableInterrupts() {__asm__("rim\n");} /* enable interrupts */
|
||||
#define disableInterrupts() {__asm__("sim\n");} /* disable interrupts */
|
||||
#define rim() {__asm__("rim\n");} /* enable interrupts */
|
||||
#define sim() {__asm__("sim\n");} /* disable interrupts */
|
||||
#define nop() {__asm__("nop\n");} /* No Operation */
|
||||
#define trap() {__asm__("trap\n");} /* Trap (soft IT) */
|
||||
#define wfi() {__asm__("wfi\n");} /* Wait For Interrupt */
|
||||
#define halt() {__asm__("halt\n");} /* Halt */
|
||||
#define enableInterrupts() \
|
||||
xxx { __asm__("rim\n"); } /* enable interrupts */
|
||||
#define disableInterrupts() \
|
||||
{ \
|
||||
__asm__("sim\n"); \
|
||||
} /* disable interrupts */
|
||||
#define rim() \
|
||||
{ \
|
||||
__asm__("rim\n"); \
|
||||
} /* enable interrupts */
|
||||
#define sim() \
|
||||
{ \
|
||||
__asm__("sim\n"); \
|
||||
} /* disable interrupts */
|
||||
#define nop() \
|
||||
{ \
|
||||
__asm__("nop\n"); \
|
||||
} /* No Operation */
|
||||
#define trap() \
|
||||
{ \
|
||||
__asm__("trap\n"); \
|
||||
} /* Trap (soft IT) */
|
||||
#define wfi() \
|
||||
{ \
|
||||
__asm__("wfi\n"); \
|
||||
} /* Wait For Interrupt */
|
||||
#define halt() \
|
||||
{ \
|
||||
__asm__("halt\n"); \
|
||||
} /* Halt */
|
||||
#else /*_IAR_*/
|
||||
#include <intrinsics.h>
|
||||
#define enableInterrupts() __enable_interrupt() /* enable interrupts */
|
||||
|
|
@ -2763,7 +2790,6 @@ CFG_TypeDef;
|
|||
#define halt() __halt() /* Halt */
|
||||
#endif /*_RAISONANCE_*/
|
||||
|
||||
|
||||
/*============================== Interrupt vector Handling ========================*/
|
||||
|
||||
#ifdef _COSMIC_
|
||||
|
|
@ -2817,9 +2843,7 @@ Comments : The different parameters of commands are
|
|||
#define ClrBit(VAR, Place) ((VAR) &= (uint8_t)((uint8_t)((uint8_t)1 << (uint8_t)(Place)) ^ (uint8_t)255))
|
||||
|
||||
#define ChgBit(VAR, Place) ((VAR) ^= (uint8_t)((uint8_t)1 << (uint8_t)(Place)))
|
||||
#define AffBit(VAR,Place,Value) ((Value) ? \
|
||||
((VAR) |= ((uint8_t)1<<(Place))) : \
|
||||
((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))
|
||||
#define AffBit(VAR, Place, Value) ((Value) ? ((VAR) |= ((uint8_t)1 << (Place))) : ((VAR) &= (((uint8_t)1 << (Place)) ^ (uint8_t)255)))
|
||||
#define MskBit(Dest, Msk, Src) ((Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)))
|
||||
|
||||
#define ValBit(VAR, Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1 << (uint8_t)(Place)))
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
# STM8 Debug Configuration for OpenOCD 0.10.0
|
||||
interface stlink
|
||||
transport select swim
|
||||
|
||||
# STM8S003 Settings
|
||||
set CHIPNAME stm8s003
|
||||
|
||||
# Target setup
|
||||
swim newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
|
||||
target create $CHIPNAME.cpu stm8 -endian little -chain-position $CHIPNAME.cpu
|
||||
|
||||
# Flash configuration (8KB)
|
||||
flash bank $_FLASHNAME stm8 0x8000 0 0 0 $CHIPNAME.cpu
|
||||
|
||||
# Reset configuration
|
||||
reset_config srst_only
|
||||
|
||||
# Speed settings
|
||||
stlink_set_swd_freq 100
|
||||
|
||||
# Initialize
|
||||
init
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
# stm8s003.cfg
|
||||
source [find target/swim.cfg]
|
||||
transport select swim
|
||||
|
||||
# Chip parameters (adjust as needed)
|
||||
set CHIPNAME stm8s003
|
||||
set WORKAREASIZE 0x400 # RAM size
|
||||
|
||||
# Flash configuration
|
||||
flash bank $_FLASHNAME stm8 0x8000 0 0 0 $_TARGETNAME
|
||||
Ładowanie…
Reference in New Issue