kopia lustrzana https://github.com/Hamlib/Hamlib
154 wiersze
4.0 KiB
C
154 wiersze
4.0 KiB
C
/*
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* Hamlib Drake backend - R-8A description
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* Copyright (c) 2001-2003 by Stephane Fillod
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*
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* $Id: r8a.c,v 1.1 2004-03-10 23:32:01 fillods Exp $
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*
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* This library is free software; you can redistribute it and/or modify
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* it under the terms of the GNU Library General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Library General Public License for more details.
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*
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* You should have received a copy of the GNU Library General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <stdlib.h>
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#include <hamlib/rig.h>
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#include "drake.h"
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#define R8A_MODES (RIG_MODE_SSB|RIG_MODE_CW|RIG_MODE_RTTY|RIG_MODE_AM|RIG_MODE_AMS|RIG_MODE_FM)
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#define R8A_FUNC (RIG_FUNC_MN|RIG_FUNC_LOCK|RIG_FUNC_NB)
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#define R8A_LEVEL_ALL (RIG_LEVEL_PREAMP|RIG_LEVEL_ATT|RIG_LEVEL_AGC)
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#define R8A_PARM_ALL (RIG_PARM_NONE)
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#define R8A_VFO (RIG_VFO_A|RIG_VFO_B)
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#define R8A_VFO_OPS (RIG_OP_UP|RIG_OP_DOWN|RIG_OP_TO_VFO|RIG_OP_FROM_VFO|RIG_OP_MCL|RIG_OP_CPY)
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#define R8A_ANTS (RIG_ANT_1|RIG_ANT_2|RIG_ANT_3)
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/*
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* R-8A rig capabilities.
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*
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* specs: http://www.dxing.com/rx/r8.htm
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*
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*/
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const struct rig_caps r8a_caps = {
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.rig_model = RIG_MODEL_DKR8A,
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.model_name = "R-8A",
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.mfg_name = "Drake",
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.version = "0.2",
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.copyright = "LGPL",
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.status = RIG_STATUS_UNTESTED, /* and only basic support */
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.rig_type = RIG_TYPE_RECEIVER,
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.ptt_type = RIG_PTT_NONE,
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.dcd_type = RIG_DCD_NONE,
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.port_type = RIG_PORT_SERIAL,
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.serial_rate_min = 9600,
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.serial_rate_max = 9600,
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.serial_data_bits = 8,
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.serial_stop_bits = 1,
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.serial_parity = RIG_PARITY_NONE,
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.serial_handshake = RIG_HANDSHAKE_HARDWARE,
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.write_delay = 0,
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.post_write_delay = 1,
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.timeout = 200,
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.retry = 3,
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.has_get_func = R8A_FUNC,
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.has_set_func = R8A_FUNC,
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.has_get_level = R8A_LEVEL_ALL,
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.has_set_level = RIG_LEVEL_SET(R8A_LEVEL_ALL),
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.has_get_parm = R8A_PARM_ALL,
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.has_set_parm = RIG_PARM_SET(R8A_PARM_ALL),
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.level_gran = {}, /* FIXME: granularity */
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.parm_gran = {},
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.ctcss_list = NULL,
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.dcs_list = NULL,
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.preamp = { 10, RIG_DBLST_END },
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.attenuator = { 10, RIG_DBLST_END },
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.max_rit = Hz(0),
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.max_xit = Hz(0),
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.max_ifshift = Hz(0),
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.targetable_vfo = 0,
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.transceive = RIG_TRN_OFF, /* TODO: acutally has RIG_TRN_RIG */
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.bank_qty = 0,
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.chan_desc_sz = 7,
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.vfo_ops = R8A_VFO_OPS,
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.chan_list = {
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{ 0, 999, RIG_MTYPE_MEM },
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RIG_CHAN_END
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},
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.rx_range_list1 = {
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{kHz(100),MHz(30),R8A_MODES,-1,-1,R8A_VFO,R8A_ANTS},
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RIG_FRNG_END,
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},
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.tx_range_list1 = { RIG_FRNG_END, },
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.rx_range_list2 = {
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{kHz(100),MHz(30),R8A_MODES,-1,-1,R8A_VFO,R8A_ANTS},
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RIG_FRNG_END,
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},
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.tx_range_list2 = { RIG_FRNG_END, },
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.tuning_steps = {
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{R8A_MODES,10},
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{R8A_MODES,100},
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{R8A_MODES,kHz(1)},
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{R8A_MODES,kHz(10)},
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RIG_TS_END,
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},
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/* mode/filter list, remember: order matters! */
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.filters = {
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{RIG_MODE_SSB|RIG_MODE_CW|RIG_MODE_RTTY|RIG_MODE_AM, kHz(2.3)}, /* normal */
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{RIG_MODE_SSB|RIG_MODE_CW|RIG_MODE_RTTY|RIG_MODE_AM, kHz(6)}, /* wide */
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{RIG_MODE_SSB|RIG_MODE_CW|RIG_MODE_RTTY|RIG_MODE_AM, kHz(4)},
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{RIG_MODE_SSB|RIG_MODE_CW|RIG_MODE_RTTY|RIG_MODE_AM, kHz(1.8)}, /* narrow */
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{RIG_MODE_SSB|RIG_MODE_CW|RIG_MODE_RTTY|RIG_MODE_AM, Hz(500)},
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{RIG_MODE_FM, kHz(12)},
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RIG_FLT_END,
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},
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.priv = NULL,
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.rig_init = drake_init,
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.rig_cleanup = drake_cleanup,
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.set_freq = drake_set_freq,
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.set_vfo = drake_set_vfo,
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.set_mode = drake_set_mode,
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.set_ant = drake_set_ant,
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.set_mem = drake_set_mem,
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.vfo_op = drake_vfo_op,
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.set_func = drake_set_func,
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.set_level = drake_set_level,
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.set_powerstat = drake_set_powerstat,
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.get_info = drake_get_info,
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};
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/*
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* Function definitions below
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*/
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