kopia lustrzana https://github.com/Hamlib/Hamlib
515 wiersze
13 KiB
C
515 wiersze
13 KiB
C
/*
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* Hamlib backend - SDR-1000
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* Copyright (c) 2003-2010 by Stephane Fillod
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*
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <hamlib/config.h>
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#include <stdlib.h>
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#include <string.h> /* String function definitions */
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#include <unistd.h> /* UNIX standard function definitions */
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#include <math.h>
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#include "hamlib/rig.h"
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#include "parallel.h"
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#include "misc.h"
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#include "bandplan.h"
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#include "register.h"
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#include "flexradio.h"
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static int sdr1k_set_freq(RIG *rig, vfo_t vfo, freq_t freq);
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static int sdr1k_get_freq(RIG *rig, vfo_t vfo, freq_t *freq);
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static int sdr1k_reset(RIG *rig, reset_t reset);
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static int sdr1k_init(RIG *rig);
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static int sdr1k_open(RIG *rig);
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static int sdr1k_close(RIG *rig);
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static int sdr1k_cleanup(RIG *rig);
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static int sdr1k_set_ptt(RIG *rig, vfo_t vfo, ptt_t ptt);
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static int sdr1k_set_level(RIG *rig, vfo_t vfo, setting_t level, value_t val);
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typedef enum { L_EXT = 0, L_BAND = 1, L_DDS0 = 2, L_DDS1 = 3 } latch_t;
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#define TR 0x40
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#define MUTE 0x80
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#define GAIN 0x80
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#define WRB 0x40
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#define RESET 0x80
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/* DDS Control Constants */
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#define COMP_PD 0x10 /* DDS Comparator power down */
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#define DIG_PD 0x01 /* DDS Digital Power down */
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#define BYPASS_PLL 0x20 /* Bypass DDS PLL */
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#define INT_IOUD 0x01 /* Internal IO Update */
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#define OSK_EN 0x20 /* Offset Shift Keying enable */
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#define OSK_INT 0x10 /* Offset Shift Keying */
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#define BYPASS_SINC 0x40 /* Bypass Inverse Sinc Filter */
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#define PLL_RANGE 0x40 /* Set PLL Range */
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static int write_latch(RIG *rig, latch_t which, unsigned value, unsigned mask);
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static int dds_write_reg(RIG *rig, unsigned addr, unsigned data);
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static int set_bit(RIG *rig, latch_t reg, unsigned bit, unsigned state);
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#define DEFAULT_XTAL MHz(200)
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#define DEFAULT_PLL_MULT 1
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#define DEFAULT_DAC_MULT 4095
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struct sdr1k_priv_data
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{
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unsigned shadow[4]; /* shadow latches */
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freq_t dds_freq; /* current freq */
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freq_t xtal; /* base XTAL */
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int pll_mult; /* PLL mult */
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};
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#define SDR1K_FUNC RIG_FUNC_MUTE
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#define SDR1K_LEVEL RIG_LEVEL_PREAMP
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#define SDR1K_PARM RIG_PARM_NONE
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#define SDR1K_MODES (RIG_MODE_NONE)
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#define SDR1K_VFO RIG_VFO_A
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#define SDR1K_ANTS 0
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/* ************************************************************************* */
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/*
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* http://www.flex-radio.com
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* SDR-1000 rig capabilities.
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*
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*
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* TODO: RIG_FUNC_MUTE, set_external_pin?
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*
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* def set_mute (self, mute = 1):
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* self.set_bit(1, 7, mute)
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*
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* def set_unmute (self):
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* self.set_bit(1, 7, 0)
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*
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* def set_external_pin (self, pin, on = 1):
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* assert (pin < 8 and pin > 0), "Out of range 1..7"
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* self.set_bit(0, pin-1, on)
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*
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* def read_input_pin
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*
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* set_conf(XTAL,PLL_mult,spur_red)
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*
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* What about IOUD_Clock?
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*/
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const struct rig_caps sdr1k_rig_caps =
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{
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RIG_MODEL(RIG_MODEL_SDR1000),
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.model_name = "SDR-1000",
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.mfg_name = "Flex-radio",
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.version = "20200323.0",
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.copyright = "LGPL",
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.status = RIG_STATUS_ALPHA,
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.rig_type = RIG_TYPE_TUNER,
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.targetable_vfo = 0,
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.ptt_type = RIG_PTT_RIG,
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.dcd_type = RIG_DCD_NONE,
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.port_type = RIG_PORT_PARALLEL,
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.has_get_func = SDR1K_FUNC,
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.has_set_func = SDR1K_FUNC,
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.has_get_level = SDR1K_LEVEL,
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.has_set_level = RIG_LEVEL_SET(SDR1K_LEVEL),
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.has_get_parm = SDR1K_PARM,
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.has_set_parm = RIG_PARM_SET(SDR1K_PARM),
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.chan_list = {
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RIG_CHAN_END,
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},
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.scan_ops = RIG_SCAN_NONE,
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.vfo_ops = RIG_OP_NONE,
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.transceive = RIG_TRN_OFF,
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.attenuator = { RIG_DBLST_END, },
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.preamp = { 14, RIG_DBLST_END, },
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.rx_range_list1 = { {
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.startf = Hz(1), .endf = MHz(65), .modes = SDR1K_MODES,
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.low_power = -1, .high_power = -1, SDR1K_VFO
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},
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RIG_FRNG_END,
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},
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.tx_range_list1 = {
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/* restricted to ham band */
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FRQ_RNG_HF(1, SDR1K_MODES, W(1), W(1), SDR1K_VFO, SDR1K_ANTS),
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FRQ_RNG_6m(1, SDR1K_MODES, W(1), W(1), SDR1K_VFO, SDR1K_ANTS),
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RIG_FRNG_END,
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},
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.rx_range_list2 = { {
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.startf = Hz(1), .endf = MHz(65), .modes = SDR1K_MODES,
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.low_power = -1, .high_power = -1, SDR1K_VFO
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},
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RIG_FRNG_END,
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},
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.tx_range_list2 = {
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/* restricted to ham band */
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FRQ_RNG_HF(2, SDR1K_MODES, W(1), W(1), SDR1K_VFO, SDR1K_ANTS),
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FRQ_RNG_6m(2, SDR1K_MODES, W(1), W(1), SDR1K_VFO, SDR1K_ANTS),
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RIG_FRNG_END,
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},
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.tuning_steps = { {SDR1K_MODES, 1},
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RIG_TS_END,
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},
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.priv = NULL, /* priv */
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.rig_init = sdr1k_init,
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.rig_open = sdr1k_open,
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.rig_close = sdr1k_close,
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.rig_cleanup = sdr1k_cleanup,
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.set_freq = sdr1k_set_freq,
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.get_freq = sdr1k_get_freq,
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.set_ptt = sdr1k_set_ptt,
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.reset = sdr1k_reset,
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.set_level = sdr1k_set_level,
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// .set_func = sdr1k_set_func,
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.hamlib_check_rig_caps = HAMLIB_CHECK_RIG_CAPS
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};
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/* ************************************************************************* */
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int sdr1k_init(RIG *rig)
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{
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struct sdr1k_priv_data *priv;
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rig->state.priv = (struct sdr1k_priv_data *)malloc(sizeof(
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struct sdr1k_priv_data));
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if (!rig->state.priv)
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{
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/* whoops! memory shortage! */
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return -RIG_ENOMEM;
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}
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priv = rig->state.priv;
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priv->dds_freq = RIG_FREQ_NONE;
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priv->xtal = DEFAULT_XTAL;
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priv->pll_mult = DEFAULT_PLL_MULT;
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return RIG_OK;
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}
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static void pdelay(RIG *rig)
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{
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unsigned char r;
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par_read_data(&rig->state.rigport, &r); /* ~1us */
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}
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int sdr1k_open(RIG *rig)
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{
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struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
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priv->shadow[0] = 0;
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priv->shadow[1] = 0;
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priv->shadow[2] = 0;
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priv->shadow[3] = 0;
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sdr1k_reset(rig, 1);
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return RIG_OK;
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}
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int sdr1k_close(RIG *rig)
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{
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/* TODO: release relays? */
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return RIG_OK;
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}
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int sdr1k_cleanup(RIG *rig)
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{
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struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
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if (priv)
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{
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free(priv);
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}
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rig->state.priv = NULL;
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return RIG_OK;
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}
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static int set_band(RIG *rig, freq_t freq)
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{
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int band, ret;
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/* set_band */
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if (freq <= MHz(2.25))
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{
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band = 0;
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}
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else if (freq <= MHz(5.5))
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{
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band = 1;
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}
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else if (freq <= MHz(11))
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{
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band = 3; /* due to wiring mistake on board */
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}
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else if (freq <= MHz(22))
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{
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band = 2; /* due to wiring mistake on board */
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}
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else if (freq <= MHz(37.5))
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{
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band = 4;
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}
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else
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{
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band = 5;
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}
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ret = write_latch(rig, L_BAND, 1 << band, 0x3f);
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// cppcheck-suppress *
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rig_debug(RIG_DEBUG_VERBOSE, "%s %"PRIll" band %d\n", __func__, (int64_t)freq,
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band);
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return ret;
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}
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/*
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* set DDS frequency.
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* NB: due to spur reduction, effective frequency might not be the expected one
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*/
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int sdr1k_set_freq(RIG *rig, vfo_t vfo, freq_t freq)
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{
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struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
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int i;
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double ftw;
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double DDS_step_size;
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freq_t frqval;
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// why is spur_red always true?
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// int spur_red = 1;
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#define spur_red 1
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int ret;
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ret = set_band(rig, freq);
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if (ret != RIG_OK)
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{
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return ret;
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}
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/* Calculate DDS step for spu reduction
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* DDS steps = 3051.7578125Hz
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*/
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DDS_step_size = ((double)priv->xtal * priv->pll_mult) / 65536;
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rig_debug(RIG_DEBUG_VERBOSE, "%s DDS step size %g %g %g\n", __func__,
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DDS_step_size, (double)freq / DDS_step_size,
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rint((double)freq / DDS_step_size));
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// why is spur_red always true?
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if (spur_red)
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{
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frqval = (freq_t)(DDS_step_size * rint((double)freq / DDS_step_size));
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}
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else
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{
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frqval = freq;
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}
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rig_debug(RIG_DEBUG_VERBOSE, "%s curr %"PRIll" frqval %"PRIll"\n", __func__,
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(int64_t)freq, (int64_t)frqval);
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if (priv->dds_freq == frqval)
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{
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return RIG_OK;
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}
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/*** */
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ftw = (double)frqval / priv->xtal ;
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for (i = 0; i < 6; i++)
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{
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unsigned word;
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if (spur_red && i == 2)
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{
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word = 128;
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}
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else if (spur_red && i > 2)
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{
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word = 0;
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}
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else
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{
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word = (unsigned)(ftw * 256);
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ftw = ftw * 256 - word;
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}
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rig_debug(RIG_DEBUG_TRACE, "DDS %d [%02x]\n", i, word);
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ret = dds_write_reg(rig, 4 + i, word);
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if (ret != RIG_OK)
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{
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return ret;
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}
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}
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priv->dds_freq = frqval;
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return ret;
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}
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int sdr1k_get_freq(RIG *rig, vfo_t vfo, freq_t *freq)
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{
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struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
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*freq = priv->dds_freq;
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rig_debug(RIG_DEBUG_TRACE, "%s: %"PRIll"\n", __func__, (int64_t)priv->dds_freq);
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return RIG_OK;
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}
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/* Set DAC multiplier value */
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static int DAC_mult(RIG *rig, unsigned mult)
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{
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rig_debug(RIG_DEBUG_TRACE, "DAC [%02x,%02x]\n", mult >> 8, mult & 0xff);
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/* Output Shape Key I Mult */
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dds_write_reg(rig, 0x21, mult >> 8);
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dds_write_reg(rig, 0x22, mult & 0xff);
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/* Output Shape Key Q Mult */
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dds_write_reg(rig, 0x23, mult >> 8);
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dds_write_reg(rig, 0x24, mult & 0xff);
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return RIG_OK;
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}
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int sdr1k_reset(RIG *rig, reset_t reset)
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{
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/* Reset all Latches (relays off) */
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write_latch(rig, L_BAND, 0x00, 0xff);
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write_latch(rig, L_DDS1, 0x00, 0xff);
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write_latch(rig, L_DDS0, 0x00, 0xff);
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write_latch(rig, L_EXT, 0x00, 0xff);
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/* Reset DDS */
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write_latch(rig, L_DDS1, RESET | WRB, 0xff); /* reset the DDS chip */
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write_latch(rig, L_DDS1, WRB, 0xff); /* leave WRB high */
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dds_write_reg(rig, 0x1d, COMP_PD); /* Power down comparator */
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/* TODO: add PLL multiplier property and logic */
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dds_write_reg(rig, 0x1e, BYPASS_PLL); /* Bypass PLL */
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dds_write_reg(rig, 0x20,
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BYPASS_SINC | OSK_EN); /* Bypass Inverse Sinc and enable DAC */
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DAC_mult(rig, DEFAULT_DAC_MULT); /* Set DAC multiplier value */
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return RIG_OK;
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}
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int sdr1k_set_ptt(RIG *rig, vfo_t vfo, ptt_t ptt)
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{
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return set_bit(rig, L_BAND, 6, ptt == RIG_PTT_ON);
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}
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int sdr1k_set_level(RIG *rig, vfo_t vfo, setting_t level, value_t val)
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{
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rig_debug(RIG_DEBUG_TRACE, "%s: %s %d\n", __func__, rig_strlevel(level), val.i);
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switch (level)
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{
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case RIG_LEVEL_PREAMP:
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return set_bit(rig, L_EXT, 7, !(val.i == rig->caps->preamp[0]));
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break;
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default:
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return -RIG_EINVAL;
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}
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}
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int
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write_latch(RIG *rig, latch_t which, unsigned value, unsigned mask)
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{
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struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
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hamlib_port_t *pport = &rig->state.rigport;
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if (!(L_EXT <= which && which <= L_DDS1))
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{
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return -RIG_EINVAL;
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}
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par_lock(pport);
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priv->shadow[which] = (priv->shadow[which] & ~mask) | (value & mask);
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par_write_data(pport, priv->shadow[which]);
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pdelay(rig);
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par_write_control(pport, 0x0F ^ (1 << which));
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pdelay(rig);
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par_write_control(pport, 0x0F);
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pdelay(rig);
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par_unlock(pport);
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return RIG_OK;
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}
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int
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dds_write_reg(RIG *rig, unsigned addr, unsigned data)
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{
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#if 0
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write_latch(rig, L_DDS1, addr & 0x3f, 0x3f);
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write_latch(rig, L_DDS0, data, 0xff);
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write_latch(rig, L_DDS1, 0x40, 0x40);
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write_latch(rig, L_DDS1, 0x00, 0x40);
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#else
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/* set up data bits */
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write_latch(rig, L_DDS0, data, 0xff);
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/* set up address bits with WRB high */
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//write_latch (rig, L_DDS1, addr & 0x3f, 0x3f);
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write_latch(rig, L_DDS1, WRB | addr, 0xff);
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/* send write command with WRB low */
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write_latch(rig, L_DDS1, addr, 0xff);
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/* return WRB high */
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write_latch(rig, L_DDS1, WRB, 0xff);
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#endif
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return RIG_OK;
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}
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int
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set_bit(RIG *rig, latch_t reg, unsigned bit, unsigned state)
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{
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unsigned val;
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val = state ? 1 << bit : 0;
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return write_latch(rig, reg, val, 1 << bit);
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}
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