From 32f9353c03b5426304c1828fb9b0b62fe6079afa Mon Sep 17 00:00:00 2001
From: Mike Black W9MDB <mdblack98@yahoo.com>
Date: Thu, 4 Aug 2022 08:23:26 -0500
Subject: [PATCH] Increase write_delay for Xiegu 6100 to 3ms -- was locking up
 rig < 3ms

---
 rigs/icom/xiegu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rigs/icom/xiegu.c b/rigs/icom/xiegu.c
index dff8778dd..1a790789c 100644
--- a/rigs/icom/xiegu.c
+++ b/rigs/icom/xiegu.c
@@ -330,7 +330,7 @@ const struct rig_caps x6100_caps =
     RIG_MODEL(RIG_MODEL_X6100),
     .model_name = "X6100",
     .mfg_name =  "Xiegu",
-    .version =  BACKEND_VER ".2",
+    .version =  BACKEND_VER ".3",
     .copyright =  "LGPL",
     .status =  RIG_STATUS_STABLE,
     .rig_type =  RIG_TYPE_TRANSCEIVER,
@@ -343,7 +343,7 @@ const struct rig_caps x6100_caps =
     .serial_stop_bits =  1,
     .serial_parity =  RIG_PARITY_NONE,
     .serial_handshake =  RIG_HANDSHAKE_NONE,
-    .write_delay =  0,
+    .write_delay =  3,
     .post_write_delay =  0,
     .timeout =  1000,
     .retry =  3,