From 21ade6493a4a7dd37bed7907f11ce2b0487f5a38 Mon Sep 17 00:00:00 2001 From: Mike Black W9MDB Date: Mon, 5 Jul 2021 11:24:07 -0500 Subject: [PATCH] Add MainA/B and SubA/B to dummy rig for testing Add debug cache display for same when applicable https://github.com/Hamlib/Hamlib/issues/730 --- rigs/dummy/dummy.c | 6 +++++- src/rig.c | 10 ++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/rigs/dummy/dummy.c b/rigs/dummy/dummy.c index cc9e57874..d7765547a 100644 --- a/rigs/dummy/dummy.c +++ b/rigs/dummy/dummy.c @@ -431,9 +431,13 @@ static int dummy_set_freq(RIG *rig, vfo_t vfo, freq_t freq) { case RIG_VFO_MAIN: case RIG_VFO_A: priv->vfo_a.freq = freq; break; + case RIG_VFO_MAIN_A: priv->vfo_maina.freq = freq; break; + case RIG_VFO_MAIN_B: priv->vfo_mainb.freq = freq; break; case RIG_VFO_SUB: case RIG_VFO_B: priv->vfo_b.freq = freq; break; + case RIG_VFO_SUB_A: priv->vfo_suba.freq = freq; break; + case RIG_VFO_SUB_B: priv->vfo_subb.freq = freq; break; case RIG_VFO_C: priv->vfo_c.freq = freq; break; } @@ -2172,7 +2176,7 @@ struct rig_caps dummy_caps = RIG_MODEL(RIG_MODEL_DUMMY), .model_name = "Dummy", .mfg_name = "Hamlib", - .version = "20210702.0", + .version = "20210705.0", .copyright = "LGPL", .status = RIG_STATUS_STABLE, .rig_type = RIG_TYPE_OTHER, diff --git a/src/rig.c b/src/rig.c index 1d2b41980..500c1f74c 100644 --- a/src/rig.c +++ b/src/rig.c @@ -367,6 +367,16 @@ static void cache_show(RIG *rig, const char *func, int line) "%s(%d): freqMainB=%.0f, modeMainB=%s, widthMainB=%d\n", func, line, rig->state.cache.freqMainB, rig_strrmode(rig->state.cache.modeMainB), (int)rig->state.cache.widthMainB); + if (rig->state.vfo_list & RIG_VFO_SUB_A) { + rig_debug(RIG_DEBUG_CACHE, + "%s(%d): freqSubA=%.0f, modeSubA=%s, widthSubA=%d\n", func, line, + rig->state.cache.freqSubA, rig_strrmode(rig->state.cache.modeSubA), + (int)rig->state.cache.widthSubA); + rig_debug(RIG_DEBUG_CACHE, + "%s(%d): freqSubB=%.0f, modeSubB=%s, widthSubB=%d\n", func, line, + rig->state.cache.freqSubB, rig_strrmode(rig->state.cache.modeSubB), + (int)rig->state.cache.widthSubB); + } } /**