kopia lustrzana https://github.com/Hamlib/Hamlib
419 wiersze
9.2 KiB
C
419 wiersze
9.2 KiB
C
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/*
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* Hamlib KIT backend - Sat-Schneider DRT1 DRM receiver description
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* Copyright (c) 2004 by Stephane Fillod
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*
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* $Id: drt1.c,v 1.1 2004-08-19 21:02:47 fillods Exp $
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*
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* This library is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <stdlib.h>
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#include <stdio.h>
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#include "hamlib/rig.h"
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#include "kit.h"
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#include "serial.h"
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#include "token.h"
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#define DRT1_MODES (RIG_MODE_AM)
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#define DRT1_FUNC (RIG_FUNC_NONE)
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#define DRT1_LEVEL_ALL (RIG_LEVEL_NONE)
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#define DRT1_PARM_ALL (RIG_PARM_NONE)
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#define DRT1_VFO (RIG_VFO_A)
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/* defaults */
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#define OSCFREQ MHz(45.012)
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#define IFMIXFREQ MHz(45)
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#define REFMULT 8
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#define CHARGE_PUMP_CURRENT 75
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struct drt1_priv_data {
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freq_t osc_freq;
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freq_t if_mix_freq;
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unsigned ref_mult;
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unsigned pump_crrnt;
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};
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#define TOK_OSCFREQ TOKEN_BACKEND(1)
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#define TOK_IFMIXFREQ TOKEN_BACKEND(2)
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#define TOK_REFMULT TOKEN_BACKEND(3)
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#define TOK_PUMPCRNT TOKEN_BACKEND(4)
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static const struct confparams drt1_cfg_params[] = {
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{ TOK_OSCFREQ, "osc_freq", "Oscillatorfreq", "Oscillator frequency in Hz",
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"45012000", RIG_CONF_NUMERIC, { .n = { 0, MHz(400), 1 } }
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},
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{ TOK_IFMIXFREQ, "if_mix_freq", "IF", "IF mixing frequency in Hz",
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"45000000", RIG_CONF_NUMERIC, { .n = { 0, MHz(400), 1 } }
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},
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{ TOK_REFMULT, "ref_mult", "REFCLK Multiplier", "REFCLK Multiplier",
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"8", RIG_CONF_NUMERIC, { .n = { 4, 20, 1 } }
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},
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{ TOK_PUMPCRNT, "pump_current", "Charge pump current", "Charge pump current in uA",
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"75", RIG_CONF_NUMERIC, { .n = { 75, 150, 25 } }
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},
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{ RIG_CONF_END, NULL, }
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};
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static int drt1_init(RIG *rig);
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static int drt1_cleanup(RIG *rig);
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static int drt1_set_freq(RIG *rig, vfo_t vfo, freq_t freq);
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static int drt1_set_conf(RIG *rig, token_t token, const char *val);
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static int drt1_get_conf(RIG *rig, token_t token, char *val);
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/*
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* Sat-Service Schneider DRM tuner.
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*
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* The receiver is controlled via the TX, RTS and DTR pins of the serial port.
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*/
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const struct rig_caps drt1_caps = {
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.rig_model = RIG_MODEL_DRT1,
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.model_name = "DRT1",
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.mfg_name = "Sat-Schneider",
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.version = "0.1",
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.copyright = "LGPL",
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.status = RIG_STATUS_UNTESTED,
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.rig_type = RIG_TYPE_TUNER,
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.ptt_type = RIG_PTT_NONE,
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.dcd_type = RIG_DCD_NONE,
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.port_type = RIG_PORT_SERIAL, /* bit banging */
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.serial_rate_min = 9600, /* don't care */
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.serial_rate_max = 9600,
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.serial_data_bits = 8,
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.serial_stop_bits = 1,
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.serial_parity = RIG_PARITY_NONE,
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.serial_handshake = RIG_HANDSHAKE_NONE,
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.write_delay = 0,
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.post_write_delay = 0,
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.timeout = 200,
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.retry = 0,
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.has_get_func = DRT1_FUNC,
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.has_set_func = DRT1_FUNC,
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.has_get_level = DRT1_LEVEL_ALL,
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.has_set_level = RIG_LEVEL_SET(DRT1_LEVEL_ALL),
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.has_get_parm = DRT1_PARM_ALL,
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.has_set_parm = RIG_PARM_SET(DRT1_PARM_ALL),
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.level_gran = {},
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.parm_gran = {},
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.ctcss_list = NULL,
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.dcs_list = NULL,
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.preamp = { RIG_DBLST_END },
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.attenuator = { RIG_DBLST_END },
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.max_rit = Hz(0),
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.max_xit = Hz(0),
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.max_ifshift = Hz(0),
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.targetable_vfo = 0,
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.transceive = RIG_TRN_OFF,
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.bank_qty = 0,
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.chan_desc_sz = 0,
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.chan_list = { RIG_CHAN_END, },
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.rx_range_list1 = {
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{kHz(50),MHz(30),DRT1_MODES,-1,-1,DRT1_VFO},
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RIG_FRNG_END,
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},
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.tx_range_list1 = { RIG_FRNG_END, },
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.rx_range_list2 = {
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{kHz(50),MHz(30),DRT1_MODES,-1,-1,DRT1_VFO},
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RIG_FRNG_END,
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},
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.tx_range_list2 = { RIG_FRNG_END, },
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.tuning_steps = {
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{DRT1_MODES,1},
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RIG_TS_END,
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},
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/* mode/filter list, remember: order matters! */
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.filters = {
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{DRT1_MODES, kHz(10)}, /* opt. 20 kHz */
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RIG_FLT_END,
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},
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.cfgparams = drt1_cfg_params,
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.rig_init = drt1_init,
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.rig_cleanup = drt1_cleanup,
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.set_conf = drt1_set_conf,
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.get_conf = drt1_get_conf,
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.set_freq = drt1_set_freq,
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};
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int drt1_init(RIG *rig)
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{
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struct drt1_priv_data *priv;
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priv = (struct drt1_priv_data*)malloc(sizeof(struct drt1_priv_data));
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if (!priv) {
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/* whoops! memory shortage! */
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return -RIG_ENOMEM;
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}
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rig->state.priv = (void*)priv;
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priv->osc_freq = OSCFREQ;
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priv->ref_mult = REFMULT;
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priv->if_mix_freq = IFMIXFREQ;
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priv->pump_crrnt = CHARGE_PUMP_CURRENT;
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return RIG_OK;
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}
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int drt1_cleanup(RIG *rig)
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{
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if (!rig)
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return -RIG_EINVAL;
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if (rig->state.priv)
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free(rig->state.priv);
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rig->state.priv = NULL;
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return RIG_OK;
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}
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/*
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* Assumes rig!=NULL, rig->state.priv!=NULL
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*/
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int drt1_set_conf(RIG *rig, token_t token, const char *val)
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{
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struct drt1_priv_data *priv;
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priv = (struct drt1_priv_data*)rig->state.priv;
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switch(token) {
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case TOK_OSCFREQ:
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sscanf(val, "%"FREQFMT, &priv->osc_freq);
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break;
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case TOK_REFMULT:
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sscanf(val, "%d", &priv->ref_mult);
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break;
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case TOK_IFMIXFREQ:
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sscanf(val, "%"FREQFMT, &priv->if_mix_freq);
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break;
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case TOK_PUMPCRNT:
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sscanf(val, "%d", &priv->pump_crrnt);
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break;
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default:
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return -RIG_EINVAL;
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}
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return RIG_OK;
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}
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/*
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* assumes rig!=NULL,
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* Assumes rig!=NULL, rig->state.priv!=NULL
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* and val points to a buffer big enough to hold the conf value.
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*/
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int drt1_get_conf(RIG *rig, token_t token, char *val)
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{
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struct drt1_priv_data *priv;
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priv = (struct drt1_priv_data*)rig->state.priv;
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switch(token) {
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case TOK_OSCFREQ:
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sprintf(val, "%"FREQFMT, priv->osc_freq);
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break;
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case TOK_REFMULT:
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sprintf(val, "%d", priv->ref_mult);
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break;
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case TOK_IFMIXFREQ:
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sprintf(val, "%"FREQFMT, priv->if_mix_freq);
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break;
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case TOK_PUMPCRNT:
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sprintf(val, "%d", priv->pump_crrnt);
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break;
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default:
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return -RIG_EINVAL;
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}
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return RIG_OK;
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}
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/*
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DDS is AD9951.
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The clock input is 45,012 MHz (also 2nd LO frequencie at the same time).
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The clock multiplier should be set to 8x at start value (possible, that this
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will change to lower clock multiplier).
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The charge pump current to 75 <EFBFBD>A at start value (possible will change).
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The VCO gain bit has to be set.
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The IF offset for LO to the receiving frequency is + 45,000 MHz (fLO =
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frec + 45,000 MHz)
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Don't make the data clock too high, there are 1 KOhms decoupling resistors at
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the input pins of the DDS.
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Inputs (SDI(O)); SCLK und I/O UPDATE haves 5V TTL level, so that a
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level converter from RS232 is needed.
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I will use the attached motorola IC MC1489 as converter for amateur
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application. This IC inverts the signals !
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*/
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#define AD_DELAY 4000
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/*
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* Introduce delay after changing the bit state
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* FIXME: This implementation may not work for very fast computers,
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* or smart compilers. However, nanosleep can have
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* granularity > 10ms!
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*/
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static int ad_delay(int m)
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{
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long j;
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for (j=0; j<=m; j++) {}
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return j;
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}
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static int ad_sdio(port_t *port, int i)
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{
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int ret;
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ret = ser_set_rts(port, i);
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ad_delay(AD_DELAY);
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if (ret != RIG_OK)
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rig_debug(RIG_DEBUG_ERR, "%s: unable to set statusbits\n",
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__FUNCTION__);
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return ret;
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}
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static int ad_sclk(port_t *port, int i)
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{
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int ret;
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ret = ser_set_brk(port, i);
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ad_delay(AD_DELAY);
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if (ret != RIG_OK)
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rig_debug(RIG_DEBUG_ERR, "%s: unable to set statusbits\n",
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__FUNCTION__);
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return ret;
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|||
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}
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|||
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|
|||
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static int ad_ioupd(port_t *port, int i)
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{
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int ret;
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ret = ser_set_dtr(port, i);
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ad_delay(AD_DELAY);
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if (ret != RIG_OK)
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rig_debug(RIG_DEBUG_ERR, "%s: unable to set statusbits\n",
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__FUNCTION__);
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return ret;
|
|||
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}
|
|||
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|
|||
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static int ad_write_reg(port_t *port, unsigned addr, unsigned nb_bytes, unsigned data)
|
|||
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{
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|||
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int i;
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|||
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ad_sclk(port, 0); /* TXD 0 */
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|||
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ad_ioupd(port, 1); /* DTR 1, CE */
|
|||
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|||
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/* Instruction byte, MSB Logic 0 = write */
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|||
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addr &= 0x1f;
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|||
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for (i=7; i>=0; i--)
|
|||
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{
|
|||
|
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ad_sdio(port, addr & (1U<<i) ? 0 : 1); /* RTS 0 or 1 */
|
|||
|
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ad_sclk(port, 1); /* TXD 1, clock */
|
|||
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ad_sclk(port, 0); /* TXD 0 */
|
|||
|
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}
|
|||
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|
|||
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/* Data transfer */
|
|||
|
|
for (i=nb_bytes*8 - 1; i>=0; i--)
|
|||
|
|
{
|
|||
|
|
|
|||
|
|
ad_sdio(port, data & (1U<<i) ? 0 : 1); /* RTS 0 or 1 */
|
|||
|
|
ad_sclk(port, 1); /* TXD 1, clock */
|
|||
|
|
ad_sclk(port, 0); /* TXD 0 */
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
ad_ioupd(port, 0); /* DTR 0 */
|
|||
|
|
|
|||
|
|
return RIG_OK;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Register serial adresses */
|
|||
|
|
#define CFR1 0x0
|
|||
|
|
#define CFR2 0x1
|
|||
|
|
#define ASF 0x2
|
|||
|
|
#define ARR 0x3
|
|||
|
|
#define FTW0 0x4
|
|||
|
|
#define POW0 0x5
|
|||
|
|
|
|||
|
|
int drt1_set_freq(RIG *rig, vfo_t vfo, freq_t freq)
|
|||
|
|
{
|
|||
|
|
unsigned long frg;
|
|||
|
|
unsigned cfr2;
|
|||
|
|
|
|||
|
|
struct drt1_priv_data *priv;
|
|||
|
|
port_t *port = &rig->state.rigport;
|
|||
|
|
|
|||
|
|
priv = (struct drt1_priv_data*)rig->state.priv;
|
|||
|
|
|
|||
|
|
serial_flush(port);
|
|||
|
|
|
|||
|
|
/* Initialization */
|
|||
|
|
ad_ioupd(port, 0);
|
|||
|
|
ad_sdio(port, 0);
|
|||
|
|
ad_sclk(port, 0);
|
|||
|
|
|
|||
|
|
/*
|
|||
|
|
* CFR2:
|
|||
|
|
* clock multiplier set to 8x, charge pump current to 75 <EFBFBD>A
|
|||
|
|
* VCO gain bit has to be set
|
|||
|
|
*/
|
|||
|
|
cfr2 = ((priv->ref_mult<<3) & 0xf8) | 0x4 |
|
|||
|
|
(((priv->pump_crrnt-75)/25)&0x3);
|
|||
|
|
|
|||
|
|
ad_write_reg(port, CFR2, 3, cfr2);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* all frequencies are in Hz */
|
|||
|
|
frg = (unsigned long)(((double)freq + priv->if_mix_freq) /
|
|||
|
|
(priv->osc_freq * priv->ref_mult)
|
|||
|
|
* 4294967296.0);
|
|||
|
|
|
|||
|
|
rig_debug(RIG_DEBUG_VERBOSE, "%s: [%#lx]\n", __FUNCTION__,frg);
|
|||
|
|
|
|||
|
|
ad_write_reg(port, FTW0, 4, frg);
|
|||
|
|
|
|||
|
|
return RIG_OK;
|
|||
|
|
}
|
|||
|
|
|