2021-11-28 18:52:29 +00:00
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/*
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* Hamlib Interface - rig state cache routines
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* Copyright (c) 2000-2012 by Stephane Fillod
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* Copyright (c) 2000-2003 by Frank Singleton
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*
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include "cache.h"
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#include "misc.h"
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#define CHECK_RIG_ARG(r) (!(r) || !(r)->caps || !(r)->state.comm_state)
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/**
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* \addtogroup rig
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* @{
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*/
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int rig_set_cache_mode(RIG *rig, vfo_t vfo, rmode_t mode, pbwidth_t width)
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{
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ENTERFUNC;
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rig_cache_show(rig, __func__, __LINE__);
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if (vfo == RIG_VFO_CURR)
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{
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// if CURR then update this before we figure out the real VFO
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vfo = rig->state.current_vfo;
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}
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// pick a sane default
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if (vfo == RIG_VFO_NONE || vfo == RIG_VFO_CURR) { vfo = RIG_VFO_A; }
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if (vfo == RIG_VFO_SUB && rig->state.cache.satmode) { vfo = RIG_VFO_SUB_A; };
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switch (vfo)
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{
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2022-02-05 21:27:43 +00:00
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case RIG_VFO_ALL: // we'll use NONE to reset all VFO caches
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elapsed_ms(&rig->state.cache.time_modeMainA, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_modeMainB, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_modeMainC, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_widthMainA, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_widthMainB, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_widthMainC, HAMLIB_ELAPSED_INVALIDATE);
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break;
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case RIG_VFO_A:
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case RIG_VFO_VFO:
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case RIG_VFO_MAIN:
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case RIG_VFO_MAIN_A:
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rig->state.cache.modeMainA = mode;
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if (width > 0) { rig->state.cache.widthMainA = width; }
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elapsed_ms(&rig->state.cache.time_modeMainA, HAMLIB_ELAPSED_SET);
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elapsed_ms(&rig->state.cache.time_widthMainA, HAMLIB_ELAPSED_SET);
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break;
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case RIG_VFO_B:
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case RIG_VFO_SUB:
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case RIG_VFO_MAIN_B:
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rig->state.cache.modeMainB = mode;
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if (width > 0) { rig->state.cache.widthMainB = width; }
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elapsed_ms(&rig->state.cache.time_modeMainB, HAMLIB_ELAPSED_SET);
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elapsed_ms(&rig->state.cache.time_widthMainB, HAMLIB_ELAPSED_SET);
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break;
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case RIG_VFO_C:
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case RIG_VFO_MAIN_C:
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rig->state.cache.modeMainC = mode;
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if (width > 0) { rig->state.cache.widthMainC = width; }
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elapsed_ms(&rig->state.cache.time_modeMainC, HAMLIB_ELAPSED_SET);
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elapsed_ms(&rig->state.cache.time_widthMainC, HAMLIB_ELAPSED_SET);
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break;
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default:
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rig_debug(RIG_DEBUG_ERR, "%s: unknown vfo=%s\n", __func__, rig_strvfo(vfo));
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RETURNFUNC(-RIG_EINTERNAL);
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2021-11-28 18:52:29 +00:00
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}
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rig_cache_show(rig, __func__, __LINE__);
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RETURNFUNC(RIG_OK);
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}
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int rig_set_cache_freq(RIG *rig, vfo_t vfo, freq_t freq)
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{
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int flag = HAMLIB_ELAPSED_SET;
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if (rig_need_debug(RIG_DEBUG_CACHE))
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{
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rig_cache_show(rig, __func__, __LINE__);
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}
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rig_debug(RIG_DEBUG_CACHE, "%s: vfo=%s, current_vfo=%s\n", __func__,
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2022-02-05 21:27:43 +00:00
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rig_strvfo(vfo), rig_strvfo(rig->state.current_vfo));
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2021-11-28 18:52:29 +00:00
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if (vfo == RIG_VFO_CURR)
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{
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// if CURR then update this before we figure out the real VFO
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vfo = rig->state.current_vfo;
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}
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// if freq == 0 then we are asking to invalidate the cache
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if (freq == 0) { flag = HAMLIB_ELAPSED_INVALIDATE; }
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// pick a sane default
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if (vfo == RIG_VFO_NONE || vfo == RIG_VFO_CURR) { vfo = RIG_VFO_A; }
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if (vfo == RIG_VFO_SUB && rig->state.cache.satmode) { vfo = RIG_VFO_SUB_A; };
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if (rig_need_debug(RIG_DEBUG_CACHE))
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{
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rig_debug(RIG_DEBUG_CACHE, "%s: set vfo=%s to freq=%.0f\n", __func__,
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2022-02-05 21:27:43 +00:00
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rig_strvfo(vfo), freq);
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2021-11-28 18:52:29 +00:00
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}
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switch (vfo)
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{
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2022-02-05 21:27:43 +00:00
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case RIG_VFO_ALL: // we'll use NONE to reset all VFO caches
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elapsed_ms(&rig->state.cache.time_freqMainA, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_freqMainB, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_freqMainC, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_freqSubA, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_freqSubB, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_freqSubC, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_freqMem, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_vfo, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_modeMainA, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_modeMainB, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_modeMainC, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_widthMainA, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_widthMainB, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_widthMainC, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_ptt, HAMLIB_ELAPSED_INVALIDATE);
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elapsed_ms(&rig->state.cache.time_split, HAMLIB_ELAPSED_INVALIDATE);
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break;
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case RIG_VFO_A:
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case RIG_VFO_VFO:
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case RIG_VFO_MAIN:
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case RIG_VFO_MAIN_A:
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rig->state.cache.freqMainA = freq;
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elapsed_ms(&rig->state.cache.time_freqMainA, flag);
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break;
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case RIG_VFO_B:
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case RIG_VFO_MAIN_B:
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case RIG_VFO_SUB:
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rig->state.cache.freqMainB = freq;
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elapsed_ms(&rig->state.cache.time_freqMainB, flag);
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break;
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case RIG_VFO_C:
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case RIG_VFO_MAIN_C:
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rig->state.cache.freqMainC = freq;
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elapsed_ms(&rig->state.cache.time_freqMainC, flag);
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break;
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case RIG_VFO_SUB_A:
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rig->state.cache.freqSubA = freq;
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elapsed_ms(&rig->state.cache.time_freqSubA, flag);
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break;
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case RIG_VFO_SUB_B:
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rig->state.cache.freqSubB = freq;
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elapsed_ms(&rig->state.cache.time_freqSubB, flag);
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break;
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case RIG_VFO_SUB_C:
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rig->state.cache.freqSubC = freq;
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elapsed_ms(&rig->state.cache.time_freqSubC, flag);
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break;
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case RIG_VFO_MEM:
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rig->state.cache.freqMem = freq;
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elapsed_ms(&rig->state.cache.time_freqMem, flag);
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break;
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default:
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rig_debug(RIG_DEBUG_ERR, "%s: unknown vfo?, vfo=%s\n", __func__,
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rig_strvfo(vfo));
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return (-RIG_EINVAL);
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2021-11-28 18:52:29 +00:00
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}
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if (rig_need_debug(RIG_DEBUG_CACHE))
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{
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rig_cache_show(rig, __func__, __LINE__);
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2022-02-05 21:27:43 +00:00
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return (RIG_OK);
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2021-11-28 18:52:29 +00:00
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}
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2022-02-05 21:27:43 +00:00
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return (RIG_OK);
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2021-11-28 18:52:29 +00:00
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}
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/**
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* \brief get cached values for a VFO
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* \param rig The rig handle
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* \param vfo The VFO to get information from
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* \param freq The frequency is stored here
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* \param cache_ms_freq The age of the last frequency update in ms
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* \param mode The mode is stored here
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* \param cache_ms_mode The age of the last mode update in ms
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* \param width The width is stored here
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* \param cache_ms_width The age of the last width update in ms
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*
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* Use this to query the cache and then determine to actually fetch data from
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* the rig.
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*
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* \note All pointers must be given. No pointer can be left at NULL
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*
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* \return RIG_OK if the operation has been successful, otherwise
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* a negative value if an error occurred (in which case, cause is
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* set appropriately).
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*
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*/
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int rig_get_cache(RIG *rig, vfo_t vfo, freq_t *freq, int *cache_ms_freq,
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2022-02-05 21:27:43 +00:00
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rmode_t *mode, int *cache_ms_mode, pbwidth_t *width, int *cache_ms_width)
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2021-11-28 18:52:29 +00:00
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{
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if (CHECK_RIG_ARG(rig) || !freq || !cache_ms_freq ||
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2022-02-05 21:27:43 +00:00
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!mode || !cache_ms_mode || !width || !cache_ms_width)
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2021-11-28 18:52:29 +00:00
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{
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RETURNFUNC(-RIG_EINVAL);
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}
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if (rig_need_debug(RIG_DEBUG_CACHE))
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{
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2022-02-13 22:13:50 +00:00
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ENTERFUNC2;
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2021-11-28 18:52:29 +00:00
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}
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rig_debug(RIG_DEBUG_CACHE, "%s: vfo=%s, current_vfo=%s\n", __func__,
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2022-02-05 21:27:43 +00:00
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rig_strvfo(vfo), rig_strvfo(rig->state.current_vfo));
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2021-11-28 18:52:29 +00:00
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if (vfo == RIG_VFO_CURR)
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{
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vfo = rig->state.current_vfo;
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}
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else if (vfo == RIG_VFO_OTHER)
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{
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2021-12-12 21:05:26 +00:00
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switch (rig->state.current_vfo)
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2021-11-28 18:52:29 +00:00
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{
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2022-02-05 21:27:43 +00:00
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case RIG_VFO_OTHER:
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vfo = RIG_VFO_OTHER;
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break;
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2021-11-28 18:52:29 +00:00
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2022-02-05 21:27:43 +00:00
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case RIG_VFO_A:
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vfo = RIG_VFO_B;
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2021-12-12 21:05:26 +00:00
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break;
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2022-02-05 21:27:43 +00:00
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case RIG_VFO_MAIN_A:
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vfo = RIG_VFO_MAIN_B;
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2021-12-12 21:05:26 +00:00
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break;
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case RIG_VFO_MAIN:
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2022-02-05 21:27:43 +00:00
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vfo = RIG_VFO_SUB;
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2021-12-12 21:05:26 +00:00
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break;
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case RIG_VFO_B:
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2022-02-05 21:27:43 +00:00
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vfo = RIG_VFO_A;
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break;
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2021-12-12 21:05:26 +00:00
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case RIG_VFO_MAIN_B:
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2022-02-05 21:27:43 +00:00
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vfo = RIG_VFO_MAIN_A;
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2021-12-12 21:05:26 +00:00
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break;
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case RIG_VFO_SUB_A:
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2022-02-05 21:27:43 +00:00
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vfo = RIG_VFO_SUB_B;
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2021-12-12 21:05:26 +00:00
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break;
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case RIG_VFO_SUB_B:
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2022-02-05 21:27:43 +00:00
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vfo = RIG_VFO_SUB_A;
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2021-12-12 21:05:26 +00:00
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break;
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2022-02-05 21:27:43 +00:00
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default:
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rig_debug(RIG_DEBUG_ERR, "%s: unknown vfo=%s\n", __func__, rig_strvfo(vfo));
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}
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}
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2021-12-12 21:05:26 +00:00
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2022-02-05 21:27:43 +00:00
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// pick a sane default
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if (vfo == RIG_VFO_CURR || vfo == RIG_VFO_NONE) { vfo = RIG_VFO_A; }
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2021-12-12 21:05:26 +00:00
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2022-02-05 21:27:43 +00:00
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// If we're in satmode we map SUB to SUB_A
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if (vfo == RIG_VFO_SUB && rig->state.cache.satmode) { vfo = RIG_VFO_SUB_A; };
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2021-12-12 21:05:26 +00:00
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2022-02-05 21:27:43 +00:00
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switch (vfo)
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{
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case RIG_VFO_CURR:
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*freq = rig->state.cache.freqCurr;
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*mode = rig->state.cache.modeCurr;
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*width = rig->state.cache.widthCurr;
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*cache_ms_freq = elapsed_ms(&rig->state.cache.time_freqCurr,
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HAMLIB_ELAPSED_GET);
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*cache_ms_mode = elapsed_ms(&rig->state.cache.time_modeCurr,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_width = elapsed_ms(&rig->state.cache.time_widthCurr,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RIG_VFO_OTHER:
|
|
|
|
*freq = rig->state.cache.freqOther;
|
|
|
|
*mode = rig->state.cache.modeOther;
|
|
|
|
*width = rig->state.cache.widthOther;
|
|
|
|
*cache_ms_freq = elapsed_ms(&rig->state.cache.time_freqOther,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_mode = elapsed_ms(&rig->state.cache.time_modeOther,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_width = elapsed_ms(&rig->state.cache.time_widthOther,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RIG_VFO_A:
|
|
|
|
case RIG_VFO_VFO:
|
|
|
|
case RIG_VFO_MAIN:
|
|
|
|
case RIG_VFO_MAIN_A:
|
|
|
|
*freq = rig->state.cache.freqMainA;
|
|
|
|
*mode = rig->state.cache.modeMainA;
|
|
|
|
*width = rig->state.cache.widthMainA;
|
|
|
|
*cache_ms_freq = elapsed_ms(&rig->state.cache.time_freqMainA,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_mode = elapsed_ms(&rig->state.cache.time_modeMainA,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_width = elapsed_ms(&rig->state.cache.time_widthMainA,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RIG_VFO_B:
|
|
|
|
case RIG_VFO_SUB:
|
|
|
|
case RIG_VFO_MAIN_B:
|
|
|
|
*freq = rig->state.cache.freqMainB;
|
|
|
|
*mode = rig->state.cache.modeMainB;
|
|
|
|
*width = rig->state.cache.widthMainB;
|
|
|
|
*cache_ms_freq = elapsed_ms(&rig->state.cache.time_freqMainB,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_mode = elapsed_ms(&rig->state.cache.time_modeMainB,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_width = elapsed_ms(&rig->state.cache.time_widthMainB,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RIG_VFO_SUB_A:
|
|
|
|
*freq = rig->state.cache.freqSubA;
|
|
|
|
*mode = rig->state.cache.modeSubA;
|
|
|
|
*width = rig->state.cache.widthSubA;
|
|
|
|
*cache_ms_freq = elapsed_ms(&rig->state.cache.time_freqSubA,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_mode = elapsed_ms(&rig->state.cache.time_modeSubA,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_width = elapsed_ms(&rig->state.cache.time_widthSubA,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RIG_VFO_SUB_B:
|
|
|
|
*freq = rig->state.cache.freqSubB;
|
|
|
|
*mode = rig->state.cache.modeSubB;
|
|
|
|
*width = rig->state.cache.widthSubB;
|
|
|
|
*cache_ms_freq = elapsed_ms(&rig->state.cache.time_freqSubB,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_mode = elapsed_ms(&rig->state.cache.time_modeSubB,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_width = elapsed_ms(&rig->state.cache.time_widthSubB,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RIG_VFO_C:
|
|
|
|
//case RIG_VFO_MAINC: // not used by any rig yet
|
|
|
|
*freq = rig->state.cache.freqMainC;
|
|
|
|
*mode = rig->state.cache.modeMainC;
|
|
|
|
*width = rig->state.cache.widthMainC;
|
|
|
|
*cache_ms_freq = elapsed_ms(&rig->state.cache.time_freqMainC,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_mode = elapsed_ms(&rig->state.cache.time_modeMainC,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_width = elapsed_ms(&rig->state.cache.time_widthMainC,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RIG_VFO_SUB_C:
|
|
|
|
*freq = rig->state.cache.freqSubC;
|
|
|
|
*mode = rig->state.cache.modeSubC;
|
|
|
|
*width = rig->state.cache.widthSubC;
|
|
|
|
*cache_ms_freq = elapsed_ms(&rig->state.cache.time_freqSubC,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_mode = elapsed_ms(&rig->state.cache.time_modeSubC,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_width = elapsed_ms(&rig->state.cache.time_widthSubC,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RIG_VFO_MEM:
|
|
|
|
*freq = rig->state.cache.freqMem;
|
|
|
|
*mode = rig->state.cache.modeMem;
|
|
|
|
*width = rig->state.cache.widthMem;
|
|
|
|
*cache_ms_freq = elapsed_ms(&rig->state.cache.time_freqMem, HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_mode = elapsed_ms(&rig->state.cache.time_modeMem, HAMLIB_ELAPSED_GET);
|
|
|
|
*cache_ms_width = elapsed_ms(&rig->state.cache.time_widthMem,
|
|
|
|
HAMLIB_ELAPSED_GET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
rig_debug(RIG_DEBUG_ERR, "%s: unknown vfo?, vfo=%s\n", __func__,
|
|
|
|
rig_strvfo(vfo));
|
|
|
|
RETURNFUNC(-RIG_EINVAL);
|
2021-11-28 18:52:29 +00:00
|
|
|
}
|
|
|
|
|
2021-12-12 21:05:26 +00:00
|
|
|
rig_debug(RIG_DEBUG_CACHE, "%s: vfo=%s, freq=%.0f, mode=%s, width=%d\n",
|
2022-02-05 21:27:43 +00:00
|
|
|
__func__, rig_strvfo(vfo),
|
|
|
|
(double)*freq, rig_strrmode(*mode), (int)*width);
|
2021-11-28 18:52:29 +00:00
|
|
|
|
|
|
|
if (rig_need_debug(RIG_DEBUG_CACHE))
|
|
|
|
{
|
|
|
|
RETURNFUNC(RIG_OK);
|
|
|
|
}
|
|
|
|
|
|
|
|
return RIG_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
void rig_cache_show(RIG *rig, const char *func, int line)
|
|
|
|
{
|
|
|
|
rig_debug(RIG_DEBUG_CACHE,
|
2022-02-05 21:27:43 +00:00
|
|
|
"%s(%d): freqMainA=%.0f, modeMainA=%s, widthMainA=%d\n", func, line,
|
|
|
|
rig->state.cache.freqMainA, rig_strrmode(rig->state.cache.modeMainA),
|
|
|
|
(int)rig->state.cache.widthMainA);
|
2021-11-28 18:52:29 +00:00
|
|
|
rig_debug(RIG_DEBUG_CACHE,
|
2022-02-05 21:27:43 +00:00
|
|
|
"%s(%d): freqMainB=%.0f, modeMainB=%s, widthMainB=%d\n", func, line,
|
|
|
|
rig->state.cache.freqMainB, rig_strrmode(rig->state.cache.modeMainB),
|
|
|
|
(int)rig->state.cache.widthMainB);
|
2021-11-28 18:52:29 +00:00
|
|
|
|
|
|
|
if (rig->state.vfo_list & RIG_VFO_SUB_A)
|
|
|
|
{
|
|
|
|
rig_debug(RIG_DEBUG_CACHE,
|
2022-02-05 21:27:43 +00:00
|
|
|
"%s(%d): freqSubA=%.0f, modeSubA=%s, widthSubA=%d\n", func, line,
|
|
|
|
rig->state.cache.freqSubA, rig_strrmode(rig->state.cache.modeSubA),
|
|
|
|
(int)rig->state.cache.widthSubA);
|
2021-11-28 18:52:29 +00:00
|
|
|
rig_debug(RIG_DEBUG_CACHE,
|
2022-02-05 21:27:43 +00:00
|
|
|
"%s(%d): freqSubB=%.0f, modeSubB=%s, widthSubB=%d\n", func, line,
|
|
|
|
rig->state.cache.freqSubB, rig_strrmode(rig->state.cache.modeSubB),
|
|
|
|
(int)rig->state.cache.widthSubB);
|
2021-11-28 18:52:29 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*! @} */
|