2017-02-22 11:14:50 +00:00
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/*
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* Hamlib Dorji DRA818 backend
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* Copyright (c) 2017 by Jeroen Vreeken
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*
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h> /* String function definitions */
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#include <unistd.h> /* UNIX standard function definitions */
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#include <stdbool.h>
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#include "hamlib/rig.h"
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#include "bandplan.h"
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#include "serial.h"
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#include "register.h"
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#include "tones.h"
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#include "dra818.h"
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#include "dorji.h"
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2019-11-30 16:19:08 +00:00
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static const char *dra818_handshake_cmd = "AT+DMOCONNECT\r\n";
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2017-02-22 11:14:50 +00:00
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static const char *dra818_handshake_res = "+DMOCONNECT:0\r\n";
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static const char *dra818_setgroup_res = "+DMOSETGROUP:0\r\n";
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static const char *dra818_setvolume_res = "+DMOSETVOLUME:0\r\n";
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2019-11-30 16:19:08 +00:00
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struct dra818_priv
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{
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shortfreq_t tx_freq;
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shortfreq_t rx_freq;
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shortfreq_t bw;
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split_t split;
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tone_t ctcss_tone;
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tone_t ctcss_sql;
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tone_t dcs_code;
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tone_t dcs_sql;
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int sql;
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int vol;
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2017-02-22 11:14:50 +00:00
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};
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static int dra818_response(RIG *rig, const char *expected)
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{
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2019-11-30 16:19:08 +00:00
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char response[80];
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int r = read_string(&rig->state.rigport, response, sizeof(response), "\n", 1);
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2017-02-22 11:14:50 +00:00
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2019-11-30 16:19:08 +00:00
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if (r != strlen(expected))
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{
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return -RIG_EIO;
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}
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2017-02-22 11:14:50 +00:00
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2019-11-30 16:19:08 +00:00
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if (strcmp(expected, response))
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{
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rig_debug(RIG_DEBUG_VERBOSE, "dra818: response: %s\n", response);
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return -RIG_ERJCTED;
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}
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2017-02-22 11:14:50 +00:00
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2019-11-30 16:19:08 +00:00
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return RIG_OK;
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2017-02-22 11:14:50 +00:00
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}
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static void dra818_subaudio(RIG *rig, char *subaudio, tone_t tone, tone_t code)
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{
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2019-11-30 16:19:08 +00:00
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if (code)
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{
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2020-03-19 17:10:20 +00:00
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sprintf(subaudio, "%03uI", code);
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2019-11-30 16:19:08 +00:00
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return;
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}
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else if (tone)
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{
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int i;
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for (i = 0; rig->caps->ctcss_list[i]; i++)
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{
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if (rig->caps->ctcss_list[i] == tone)
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{
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sprintf(subaudio, "%04d", i + 1);
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return;
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}
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}
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}
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subaudio[0] = '0';
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subaudio[1] = '0';
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subaudio[2] = '0';
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subaudio[3] = '0';
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2017-02-22 11:14:50 +00:00
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}
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static int dra818_setgroup(RIG *rig)
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{
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2019-11-30 16:19:08 +00:00
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struct dra818_priv *priv = rig->state.priv;
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char cmd[80];
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char subtx[5] = { 0 };
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char subrx[5] = { 0 };
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dra818_subaudio(rig, subtx, priv->ctcss_tone, priv->dcs_code);
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dra818_subaudio(rig, subrx, priv->ctcss_sql, priv->dcs_sql);
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sprintf(cmd, "AT+DMOSETGROUP=%1d,%03d.%04d,%03d.%04d,%4s,%1d,%4s\r\n",
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priv->bw == 12500 ? 0 : 1,
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(int)(priv->tx_freq / 1000000), (int)((priv->tx_freq % 1000000) / 100),
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(int)(priv->rx_freq / 1000000), (int)((priv->rx_freq % 1000000) / 100),
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subtx, priv->sql, subrx);
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write_block(&rig->state.rigport, cmd, strlen(cmd));
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return dra818_response(rig, dra818_setgroup_res);
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2017-02-22 11:14:50 +00:00
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}
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static int dra818_setvolume(RIG *rig)
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{
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2019-11-30 16:19:08 +00:00
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struct dra818_priv *priv = rig->state.priv;
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char cmd[80];
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sprintf(cmd, "AT+DMOSETVOLUME=%1d\r\n",
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priv->vol);
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write_block(&rig->state.rigport, cmd, strlen(cmd));
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return dra818_response(rig, dra818_setvolume_res);
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2017-02-22 11:14:50 +00:00
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}
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int dra818_init(RIG *rig)
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{
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2020-01-13 21:12:56 +00:00
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struct dra818_priv *priv;
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2019-11-30 16:19:08 +00:00
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2019-12-09 23:12:13 +00:00
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rig_debug(RIG_DEBUG_VERBOSE, "%s: dra818_init called\n", __func__);
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2020-01-13 21:12:56 +00:00
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rig->state.priv = calloc(sizeof(*priv), 1);
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if (!rig->state.priv)
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2019-11-30 16:19:08 +00:00
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{
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return -RIG_ENOMEM;
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}
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2020-01-13 21:12:56 +00:00
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priv = rig->state.priv;
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2019-11-30 16:19:08 +00:00
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switch (rig->caps->rig_model)
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{
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case RIG_MODEL_DORJI_DRA818V:
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priv->rx_freq = 145000000;
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break;
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case RIG_MODEL_DORJI_DRA818U:
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priv->rx_freq = 435000000;
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break;
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}
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priv->tx_freq = priv->rx_freq;
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priv->bw = 12500;
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priv->split = RIG_SPLIT_OFF;
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priv->ctcss_tone = 0;
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priv->ctcss_sql = 0;
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priv->dcs_code = 0;
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priv->dcs_sql = 0;
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priv->sql = 4;
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priv->vol = 6;
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return RIG_OK;
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2017-02-22 11:14:50 +00:00
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}
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int dra818_cleanup(RIG *rig)
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{
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2019-11-30 16:19:08 +00:00
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rig_debug(RIG_DEBUG_VERBOSE, "%s: dra818_cleanup called\n", __func__);
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free(rig->state.priv);
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2017-02-22 11:14:50 +00:00
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2019-11-30 16:19:08 +00:00
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return RIG_OK;
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2017-02-22 11:14:50 +00:00
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}
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int dra818_open(RIG *rig)
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{
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2019-11-30 16:19:08 +00:00
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int i;
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int r;
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for (i = 0; i < 3; i++)
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{
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write_block(&rig->state.rigport, dra818_handshake_cmd,
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strlen(dra818_handshake_cmd));
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r = dra818_response(rig, dra818_handshake_res);
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if (r == RIG_OK)
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{
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break;
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}
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}
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if (r != RIG_OK)
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{
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return r;
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}
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r = dra818_setvolume(rig);
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if (r != RIG_OK)
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{
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return r;
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}
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return dra818_setgroup(rig);
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2017-02-22 11:14:50 +00:00
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}
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int dra818_set_freq(RIG *rig, vfo_t vfo, freq_t freq)
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{
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2019-11-30 16:19:08 +00:00
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struct dra818_priv *priv = rig->state.priv;
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/* Nearest channel */
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shortfreq_t sfreq = ((freq + priv->bw / 2) / priv->bw);
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sfreq *= priv->bw;
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rig_debug(RIG_DEBUG_VERBOSE,
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"dra818: requested freq = %"PRIfreq" Hz, set freq = %d Hz\n",
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freq, (int)sfreq);
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if (vfo == RIG_VFO_RX)
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{
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priv->rx_freq = sfreq;
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if (priv->split == RIG_SPLIT_OFF)
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{
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priv->tx_freq = sfreq;
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}
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}
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else if (vfo == RIG_VFO_TX)
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{
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priv->tx_freq = sfreq;
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if (priv->split == RIG_SPLIT_OFF)
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{
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priv->rx_freq = sfreq;
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}
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}
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else
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{
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return -RIG_EINVAL;
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}
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return dra818_setgroup(rig);
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2017-02-22 11:14:50 +00:00
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}
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int dra818_set_mode(RIG *rig, vfo_t vfo, rmode_t mode, pbwidth_t width)
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{
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2019-11-30 16:19:08 +00:00
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struct dra818_priv *priv = rig->state.priv;
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if (width > 12500)
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{
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priv->bw = 25000;
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}
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else
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{
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priv->bw = 12500;
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}
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rig_debug(RIG_DEBUG_VERBOSE, "dra818: bandwidth: %d\n", (int)priv->bw);
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return dra818_setgroup(rig);
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2017-02-22 11:14:50 +00:00
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}
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int dra818_get_mode(RIG *rig, vfo_t vfo, rmode_t *mode, pbwidth_t *width)
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{
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2019-11-30 16:19:08 +00:00
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struct dra818_priv *priv = rig->state.priv;
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2017-02-22 11:14:50 +00:00
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2019-11-30 16:19:08 +00:00
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*mode = RIG_MODE_FM;
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*width = priv->bw;
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return RIG_OK;
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2017-02-22 11:14:50 +00:00
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}
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int dra818_get_dcd(RIG *rig, vfo_t vfo, dcd_t *dcd)
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{
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2019-11-30 16:19:08 +00:00
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struct dra818_priv *priv = rig->state.priv;
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char cmd[80];
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2019-12-09 23:12:13 +00:00
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char response[8];
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int r;
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2019-11-30 16:19:08 +00:00
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sprintf(cmd, "S+%03d.%04d\r\n",
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(int)(priv->rx_freq / 1000000), (int)((priv->rx_freq % 1000000) / 100));
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write_block(&rig->state.rigport, cmd, strlen(cmd));
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2019-12-09 23:12:13 +00:00
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r = read_string(&rig->state.rigport, response, sizeof(response), "\n", 1);
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2019-11-30 16:19:08 +00:00
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if (r != 5)
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{
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return -RIG_EIO;
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}
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if (response[3] == 1)
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{
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*dcd = RIG_DCD_OFF;
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}
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else
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{
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*dcd = RIG_DCD_ON;
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}
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return RIG_OK;
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2017-02-22 11:14:50 +00:00
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}
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int dra818_get_freq(RIG *rig, vfo_t vfo, freq_t *freq)
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{
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2019-11-30 16:19:08 +00:00
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struct dra818_priv *priv = rig->state.priv;
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switch (vfo)
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{
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case RIG_VFO_RX:
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*freq = priv->rx_freq;
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break;
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case RIG_VFO_TX:
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*freq = priv->tx_freq;
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break;
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default:
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return -RIG_EINVAL;
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}
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return RIG_OK;
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2017-02-22 11:14:50 +00:00
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}
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int dra818_set_split_vfo(RIG *rig, vfo_t vfo, split_t split, vfo_t tx_vfo)
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{
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2019-11-30 16:19:08 +00:00
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struct dra818_priv *priv = rig->state.priv;
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priv->split = split;
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2017-02-22 11:14:50 +00:00
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2019-11-30 16:19:08 +00:00
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if (split == RIG_SPLIT_OFF)
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{
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priv->tx_freq = priv->rx_freq;
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}
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return dra818_setgroup(rig);
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2017-02-22 11:14:50 +00:00
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}
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int dra818_get_split_vfo(RIG *rig, vfo_t vfo, split_t *split, vfo_t *tx_vfo)
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{
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2019-11-30 16:19:08 +00:00
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struct dra818_priv *priv = rig->state.priv;
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*split = priv->split;
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|
if (priv->split == RIG_SPLIT_ON)
|
|
|
|
{
|
|
|
|
*tx_vfo = RIG_VFO_TX;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
*tx_vfo = RIG_VFO_RX;
|
|
|
|
}
|
|
|
|
|
|
|
|
return RIG_OK;
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
2019-11-30 16:19:08 +00:00
|
|
|
int dra818_get_level(RIG *rig, vfo_t vfo, setting_t level, value_t *val)
|
2017-02-22 11:14:50 +00:00
|
|
|
{
|
2019-11-30 16:19:08 +00:00
|
|
|
struct dra818_priv *priv = rig->state.priv;
|
|
|
|
|
|
|
|
switch (level)
|
|
|
|
{
|
|
|
|
case RIG_LEVEL_SQL:
|
|
|
|
/* SQL range: 0..8 (0=monitor) */
|
|
|
|
val->f = (priv->sql / 8.0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RIG_LEVEL_AF:
|
|
|
|
/* AF range: 1..8 */
|
|
|
|
val->f = (priv->vol / 8.0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -RIG_EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return RIG_OK;
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int dra818_set_level(RIG *rig, vfo_t vfo, setting_t level, value_t val)
|
|
|
|
{
|
2019-11-30 16:19:08 +00:00
|
|
|
struct dra818_priv *priv = rig->state.priv;
|
|
|
|
|
|
|
|
switch (level)
|
|
|
|
{
|
|
|
|
case RIG_LEVEL_SQL:
|
|
|
|
/* SQL range: 0..8 (0=monitor) */
|
|
|
|
priv->sql = val.f * 8;
|
|
|
|
|
|
|
|
if (priv->sql < 0)
|
|
|
|
{
|
|
|
|
priv->sql = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (priv->sql > 8)
|
|
|
|
{
|
|
|
|
priv->sql = 8;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dra818_setgroup(rig);
|
|
|
|
|
|
|
|
case RIG_LEVEL_AF:
|
|
|
|
/* AF range: 1..8 */
|
|
|
|
priv->vol = val.f * 8;
|
|
|
|
|
|
|
|
if (priv->vol < 1)
|
|
|
|
{
|
|
|
|
priv->vol = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (priv->vol > 8)
|
|
|
|
{
|
|
|
|
priv->vol = 8;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dra818_setvolume(rig);
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -RIG_EINVAL;
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int dra818_set_dcs_code(RIG *rig, vfo_t vfo, tone_t code)
|
|
|
|
{
|
2019-11-30 16:19:08 +00:00
|
|
|
struct dra818_priv *priv = rig->state.priv;
|
|
|
|
|
|
|
|
priv->dcs_code = code;
|
|
|
|
|
|
|
|
if (code)
|
|
|
|
{
|
|
|
|
priv->ctcss_tone = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dra818_setgroup(rig);
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
2019-11-30 16:19:08 +00:00
|
|
|
int dra818_set_ctcss_tone(RIG *rig, vfo_t vfo, tone_t tone)
|
2017-02-22 11:14:50 +00:00
|
|
|
{
|
2019-11-30 16:19:08 +00:00
|
|
|
struct dra818_priv *priv = rig->state.priv;
|
|
|
|
|
|
|
|
priv->ctcss_tone = tone;
|
|
|
|
|
|
|
|
if (tone)
|
|
|
|
{
|
|
|
|
priv->dcs_code = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dra818_setgroup(rig);
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
2019-11-30 16:19:08 +00:00
|
|
|
int dra818_set_dcs_sql(RIG *rig, vfo_t vfo, tone_t code)
|
2017-02-22 11:14:50 +00:00
|
|
|
{
|
2019-11-30 16:19:08 +00:00
|
|
|
struct dra818_priv *priv = rig->state.priv;
|
|
|
|
|
|
|
|
priv->dcs_sql = code;
|
|
|
|
|
|
|
|
if (code)
|
|
|
|
{
|
|
|
|
priv->ctcss_sql = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dra818_setgroup(rig);
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int dra818_set_ctcss_sql(RIG *rig, vfo_t vfo, tone_t tone)
|
|
|
|
{
|
2019-11-30 16:19:08 +00:00
|
|
|
struct dra818_priv *priv = rig->state.priv;
|
|
|
|
|
|
|
|
priv->ctcss_sql = tone;
|
|
|
|
|
|
|
|
if (tone)
|
|
|
|
{
|
|
|
|
priv->dcs_sql = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dra818_setgroup(rig);
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int dra818_get_ctcss_sql(RIG *rig, vfo_t vfo, tone_t *tone)
|
|
|
|
{
|
2019-11-30 16:19:08 +00:00
|
|
|
struct dra818_priv *priv = rig->state.priv;
|
|
|
|
|
|
|
|
*tone = priv->ctcss_sql;
|
|
|
|
return RIG_OK;
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
2019-11-30 16:19:08 +00:00
|
|
|
int dra818_get_dcs_sql(RIG *rig, vfo_t vfo, tone_t *code)
|
2017-02-22 11:14:50 +00:00
|
|
|
{
|
2019-11-30 16:19:08 +00:00
|
|
|
struct dra818_priv *priv = rig->state.priv;
|
|
|
|
|
|
|
|
*code = priv->dcs_sql;
|
|
|
|
return RIG_OK;
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int dra818_get_dcs_code(RIG *rig, vfo_t vfo, tone_t *code)
|
|
|
|
{
|
2019-11-30 16:19:08 +00:00
|
|
|
struct dra818_priv *priv = rig->state.priv;
|
|
|
|
|
|
|
|
*code = priv->dcs_code;
|
|
|
|
return RIG_OK;
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
2019-11-30 16:19:08 +00:00
|
|
|
int dra818_get_ctcss_tone(RIG *rig, vfo_t vfo, tone_t *tone)
|
2017-02-22 11:14:50 +00:00
|
|
|
{
|
2019-11-30 16:19:08 +00:00
|
|
|
struct dra818_priv *priv = rig->state.priv;
|
|
|
|
|
|
|
|
*tone = priv->ctcss_tone;
|
|
|
|
return RIG_OK;
|
2017-02-22 11:14:50 +00:00
|
|
|
}
|
|
|
|
|
2019-11-30 16:19:08 +00:00
|
|
|
const struct rig_caps dra818u_caps =
|
|
|
|
{
|
2020-03-05 14:44:18 +00:00
|
|
|
RIG_MODEL(RIG_MODEL_DORJI_DRA818U),
|
2019-11-30 16:19:08 +00:00
|
|
|
.model_name = "DRA818U",
|
|
|
|
.mfg_name = "Dorji",
|
2020-03-30 04:03:21 +00:00
|
|
|
.version = "20191209.0",
|
2019-11-30 16:19:08 +00:00
|
|
|
.copyright = "LGPL",
|
|
|
|
.status = RIG_STATUS_UNTESTED,
|
|
|
|
.rig_type = RIG_TYPE_TRANSCEIVER,
|
|
|
|
.ptt_type = RIG_PTT_NONE,
|
|
|
|
.dcd_type = RIG_DCD_RIG,
|
|
|
|
.port_type = RIG_PORT_SERIAL,
|
|
|
|
.serial_rate_min = 9600,
|
|
|
|
.serial_rate_max = 9600,
|
|
|
|
.serial_data_bits = 8,
|
|
|
|
.serial_stop_bits = 1,
|
|
|
|
.serial_parity = RIG_PARITY_NONE,
|
|
|
|
.serial_handshake = RIG_HANDSHAKE_NONE,
|
|
|
|
.write_delay = 0,
|
|
|
|
.post_write_delay = 0,
|
|
|
|
.timeout = 1000,
|
|
|
|
.retry = 0,
|
|
|
|
|
|
|
|
.has_get_func = RIG_FUNC_TONE | RIG_FUNC_TSQL | RIG_FUNC_SQL,
|
|
|
|
.has_set_func = RIG_FUNC_TONE | RIG_FUNC_TSQL | RIG_FUNC_SQL,
|
|
|
|
.has_get_level = RIG_LEVEL_AF | RIG_LEVEL_SQL,
|
|
|
|
.has_set_level = RIG_LEVEL_AF | RIG_LEVEL_SQL,
|
|
|
|
.has_get_parm = RIG_PARM_NONE,
|
|
|
|
.has_set_parm = RIG_PARM_NONE,
|
|
|
|
.level_gran = {},
|
|
|
|
.parm_gran = {},
|
|
|
|
.ctcss_list = /* 38 according to doc, are they all correct? */
|
|
|
|
(tone_t[])
|
|
|
|
{
|
|
|
|
670, 719, 744, 770, 797, 825, 854,
|
|
|
|
885, 915, 948, 974, 1000, 1035, 1072,
|
|
|
|
1109, 1148, 1188, 1230, 1273, 1318, 1365,
|
|
|
|
1413, 1462, 1514, 1567, 1622, 1679, 1738,
|
|
|
|
1799, 1862, 1928, 2035, 2107, 2181, 2257,
|
|
|
|
2336, 2418, 2503, 0
|
|
|
|
},
|
|
|
|
.dcs_list = common_dcs_list,
|
|
|
|
.preamp = { RIG_DBLST_END, },
|
|
|
|
.attenuator = { RIG_DBLST_END, },
|
|
|
|
.max_rit = Hz(0),
|
|
|
|
.max_xit = Hz(0),
|
|
|
|
.max_ifshift = Hz(0),
|
|
|
|
.targetable_vfo = 0,
|
|
|
|
.transceive = RIG_TRN_OFF,
|
|
|
|
.bank_qty = 0,
|
|
|
|
.chan_desc_sz = 0,
|
|
|
|
|
|
|
|
.chan_list = { RIG_CHAN_END, },
|
|
|
|
|
|
|
|
.rx_range_list1 = {
|
|
|
|
{MHz(400), MHz(480), RIG_MODE_FM, -1, -1, RIG_VFO_RX },
|
|
|
|
RIG_FRNG_END,
|
|
|
|
},
|
|
|
|
.rx_range_list2 = {
|
|
|
|
{MHz(400), MHz(480), RIG_MODE_FM, -1, -1, RIG_VFO_RX },
|
|
|
|
RIG_FRNG_END,
|
|
|
|
},
|
|
|
|
.tx_range_list1 = {
|
|
|
|
FRQ_RNG_70cm(1, RIG_MODE_FM, W(0.5), W(1), RIG_VFO_TX, RIG_ANT_1),
|
|
|
|
RIG_FRNG_END,
|
|
|
|
},
|
|
|
|
.tx_range_list2 = {
|
|
|
|
FRQ_RNG_70cm(2, RIG_MODE_FM, W(0.5), W(1), RIG_VFO_TX, RIG_ANT_1),
|
|
|
|
RIG_FRNG_END,
|
|
|
|
},
|
|
|
|
|
|
|
|
.tuning_steps = {
|
|
|
|
{RIG_MODE_FM, Hz(12500)},
|
|
|
|
RIG_TS_END,
|
|
|
|
},
|
|
|
|
.filters = {
|
|
|
|
{RIG_MODE_FM, Hz(12500)},
|
|
|
|
{RIG_MODE_FM, Hz(25000)},
|
|
|
|
RIG_FLT_END,
|
|
|
|
},
|
|
|
|
|
|
|
|
.rig_init = dra818_init,
|
|
|
|
.rig_cleanup = dra818_cleanup,
|
|
|
|
.rig_open = dra818_open,
|
|
|
|
.set_freq = dra818_set_freq,
|
|
|
|
.get_freq = dra818_get_freq,
|
|
|
|
.set_split_vfo = dra818_set_split_vfo,
|
|
|
|
.get_split_vfo = dra818_get_split_vfo,
|
|
|
|
.set_mode = dra818_set_mode,
|
|
|
|
.get_mode = dra818_get_mode,
|
|
|
|
.get_dcd = dra818_get_dcd,
|
|
|
|
.set_level = dra818_set_level,
|
|
|
|
.get_level = dra818_get_level,
|
|
|
|
.set_dcs_code = dra818_set_dcs_code,
|
|
|
|
.set_ctcss_tone = dra818_set_ctcss_tone,
|
|
|
|
.set_dcs_sql = dra818_set_dcs_sql,
|
|
|
|
.set_ctcss_sql = dra818_set_ctcss_sql,
|
|
|
|
.get_dcs_code = dra818_get_dcs_code,
|
|
|
|
.get_ctcss_tone = dra818_get_ctcss_tone,
|
|
|
|
.get_dcs_sql = dra818_get_dcs_sql,
|
|
|
|
.get_ctcss_sql = dra818_get_ctcss_sql,
|
2017-02-22 11:14:50 +00:00
|
|
|
};
|
|
|
|
|
2019-11-30 16:19:08 +00:00
|
|
|
const struct rig_caps dra818v_caps =
|
|
|
|
{
|
2020-03-05 14:44:18 +00:00
|
|
|
RIG_MODEL(RIG_MODEL_DORJI_DRA818V),
|
2019-11-30 16:19:08 +00:00
|
|
|
.model_name = "DRA818V",
|
|
|
|
.mfg_name = "Dorji",
|
2020-03-30 04:03:21 +00:00
|
|
|
.version = "20191209.0",
|
2019-11-30 16:19:08 +00:00
|
|
|
.copyright = "LGPL",
|
|
|
|
.status = RIG_STATUS_UNTESTED,
|
|
|
|
.rig_type = RIG_TYPE_TRANSCEIVER,
|
|
|
|
.ptt_type = RIG_PTT_NONE,
|
|
|
|
.dcd_type = RIG_DCD_RIG,
|
|
|
|
.port_type = RIG_PORT_SERIAL,
|
|
|
|
.serial_rate_min = 9600,
|
|
|
|
.serial_rate_max = 9600,
|
|
|
|
.serial_data_bits = 8,
|
|
|
|
.serial_stop_bits = 1,
|
|
|
|
.serial_parity = RIG_PARITY_NONE,
|
|
|
|
.serial_handshake = RIG_HANDSHAKE_NONE,
|
|
|
|
.write_delay = 0,
|
|
|
|
.post_write_delay = 0,
|
|
|
|
.timeout = 1000,
|
|
|
|
.retry = 0,
|
|
|
|
|
|
|
|
.has_get_func = RIG_FUNC_TONE | RIG_FUNC_TSQL | RIG_FUNC_SQL,
|
|
|
|
.has_set_func = RIG_FUNC_TONE | RIG_FUNC_TSQL | RIG_FUNC_SQL,
|
|
|
|
.has_get_level = RIG_LEVEL_AF | RIG_LEVEL_SQL,
|
|
|
|
.has_set_level = RIG_LEVEL_AF | RIG_LEVEL_SQL,
|
|
|
|
.has_get_parm = RIG_PARM_NONE,
|
|
|
|
.has_set_parm = RIG_PARM_NONE,
|
|
|
|
.level_gran = {},
|
|
|
|
.parm_gran = {},
|
|
|
|
.ctcss_list = /* 38 according to doc, are they all correct? */
|
|
|
|
(tone_t[])
|
|
|
|
{
|
|
|
|
670, 719, 744, 770, 797, 825, 854,
|
|
|
|
885, 915, 948, 974, 1000, 1035, 1072,
|
|
|
|
1109, 1148, 1188, 1230, 1273, 1318, 1365,
|
|
|
|
1413, 1462, 1514, 1567, 1622, 1679, 1738,
|
|
|
|
1799, 1862, 1928, 2035, 2107, 2181, 2257,
|
|
|
|
2336, 2418, 2503, 0
|
|
|
|
},
|
|
|
|
.dcs_list = common_dcs_list,
|
|
|
|
.preamp = { RIG_DBLST_END, },
|
|
|
|
.attenuator = { RIG_DBLST_END, },
|
|
|
|
.max_rit = Hz(0),
|
|
|
|
.max_xit = Hz(0),
|
|
|
|
.max_ifshift = Hz(0),
|
|
|
|
.targetable_vfo = 0,
|
|
|
|
.transceive = RIG_TRN_OFF,
|
|
|
|
.bank_qty = 0,
|
|
|
|
.chan_desc_sz = 0,
|
|
|
|
|
|
|
|
.chan_list = { RIG_CHAN_END, },
|
|
|
|
|
|
|
|
.rx_range_list1 = {
|
|
|
|
{MHz(134), MHz(174), RIG_MODE_FM, -1, -1, RIG_VFO_RX },
|
|
|
|
RIG_FRNG_END,
|
|
|
|
},
|
|
|
|
.rx_range_list2 = {
|
|
|
|
{MHz(134), MHz(174), RIG_MODE_FM, -1, -1, RIG_VFO_RX },
|
|
|
|
RIG_FRNG_END,
|
|
|
|
},
|
|
|
|
.tx_range_list1 = {
|
|
|
|
FRQ_RNG_2m(1, RIG_MODE_FM, W(0.5), W(1), RIG_VFO_TX, RIG_ANT_1),
|
|
|
|
RIG_FRNG_END,
|
|
|
|
},
|
|
|
|
.tx_range_list2 = {
|
|
|
|
FRQ_RNG_2m(2, RIG_MODE_FM, W(0.5), W(1), RIG_VFO_TX, RIG_ANT_1),
|
|
|
|
RIG_FRNG_END,
|
|
|
|
},
|
|
|
|
|
|
|
|
.tuning_steps = {
|
|
|
|
{RIG_MODE_FM, Hz(12500)},
|
|
|
|
RIG_TS_END,
|
|
|
|
},
|
|
|
|
.filters = {
|
|
|
|
{RIG_MODE_FM, Hz(12500)},
|
|
|
|
{RIG_MODE_FM, Hz(25000)},
|
|
|
|
RIG_FLT_END,
|
|
|
|
},
|
|
|
|
|
|
|
|
.rig_init = dra818_init,
|
|
|
|
.rig_cleanup = dra818_cleanup,
|
|
|
|
.rig_open = dra818_open,
|
|
|
|
.set_freq = dra818_set_freq,
|
|
|
|
.get_freq = dra818_get_freq,
|
|
|
|
.set_split_vfo = dra818_set_split_vfo,
|
|
|
|
.get_split_vfo = dra818_get_split_vfo,
|
|
|
|
.set_mode = dra818_set_mode,
|
|
|
|
.get_mode = dra818_get_mode,
|
|
|
|
.get_dcd = dra818_get_dcd,
|
|
|
|
.set_level = dra818_set_level,
|
|
|
|
.get_level = dra818_get_level,
|
|
|
|
.set_dcs_code = dra818_set_dcs_code,
|
|
|
|
.set_ctcss_tone = dra818_set_ctcss_tone,
|
|
|
|
.set_dcs_sql = dra818_set_dcs_sql,
|
|
|
|
.set_ctcss_sql = dra818_set_ctcss_sql,
|
|
|
|
.get_dcs_code = dra818_get_dcs_code,
|
|
|
|
.get_ctcss_tone = dra818_get_ctcss_tone,
|
|
|
|
.get_dcs_sql = dra818_get_dcs_sql,
|
|
|
|
.get_ctcss_sql = dra818_get_ctcss_sql,
|
2017-02-22 11:14:50 +00:00
|
|
|
};
|
|
|
|
|