kopia lustrzana https://github.com/F5OEO/rpitx
First implementation of new PLL method
F5OEO
rodzic
4951e011a9
commit
abdadd634e
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@ -15,10 +15,10 @@ LDFLAGS = -lm -lrt -lpthread
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CCP = g++
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CC = gcc
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v2rpitx: gpio.h gpio.cpp dma.h dma.cpp mailbox.c raspberry_pi_revision.c v2rpitx.cpp fmdmasync.h fmdmasync.cpp
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v2rpitx: gpio.h gpio.cpp dma.h dma.cpp mailbox.c raspberry_pi_revision.c v2rpitx.cpp fmdmasync.h fmdmasync.cpp ngfmdmasync.h ngfmdmasync.cpp
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$(CC) $(CFLAGS) -c -o mailbox.o mailbox.c
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$(CC) $(CFLAGS) -c -o raspberry_pi_revision.o raspberry_pi_revision.c
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$(CCP) $(CFLAGS) -o v2rpitx fmdmasync.cpp dma.cpp gpio.cpp mailbox.o raspberry_pi_revision.o v2rpitx.cpp $(LDFLAGS)
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$(CCP) $(CFLAGS) -o v2rpitx ngfmdmasync.cpp fmdmasync.cpp dma.cpp gpio.cpp mailbox.o raspberry_pi_revision.o v2rpitx.cpp $(LDFLAGS)
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@ -22,7 +22,7 @@ void fmdmasync::SetDmaAlgo()
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cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[samplecnt]);
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cbp->dst = 0x7E000000 | (GPCLK_DIV<<2) | CLK_BASE ;
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cbp->dst = 0x7E000000 + (GPCLK_DIV<<2) + CLK_BASE ;
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cbp->length = 4;
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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@ -34,7 +34,7 @@ void fmdmasync::SetDmaAlgo()
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cbp->info = /*BCM2708_DMA_SRC_IGNOR | */BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
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cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
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cbp->dst = 0x7E000000 | (PWM_FIFO<<2) | PWM_BASE ;
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cbp->dst = 0x7E000000 + (PWM_FIFO<<2) + PWM_BASE ;
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cbp->length = 4;
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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39
src/gpio.cpp
39
src/gpio.cpp
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@ -73,7 +73,8 @@ int clkgpio::SetPllNumber(int PllNo,int MashType)
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Mash=MashType;
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else
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Mash=0;
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gpioreg[GPCLK_CNTL]= 0x5A000000 | (Mash << 9) | pllnumber|(1 << 4) ; //4 is START CLK
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gpioreg[GPCLK_CNTL]= 0x5A000000 | (Mash << 9) | pllnumber|(0 << 4) ; //4 is START CLK
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usleep(100);
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Pllfrequency=GetPllFrequency(pllnumber);
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return 0;
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}
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@ -95,6 +96,18 @@ uint64_t clkgpio::GetPllFrequency(int PllNo)
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return Freq;
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}
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int clkgpio::SetClkDivFrac(uint32_t Div,uint32_t Frac)
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{
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gpioreg[GPCLK_DIV] = 0x5A000000 | ((Div)<<12) | Frac;
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usleep(10);
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gpioreg[GPCLK_CNTL]= 0x5A000000 | (Mash << 9) | pllnumber |(1<<4) ; //4 is START CLK
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usleep(10);
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return 0;
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}
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int clkgpio::SetFrequency(uint64_t Frequency)
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{
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@ -103,9 +116,9 @@ int clkgpio::SetFrequency(uint64_t Frequency)
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uint32_t FreqFractionnal=(uint32_t) (4096*(Freqresult-(double)FreqDivider));
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if((FreqDivider>4096)||(FreqDivider<2)) fprintf(stderr,"Frequency out of range\n");
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printf("DIV/FRAC %u/%u \n",FreqDivider,FreqFractionnal);
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gpioreg[GPCLK_DIV] = 0x5A000000 | ((FreqDivider)<<12) | FreqFractionnal;
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//gpioreg[GPCLK_CNTL]= 0x5A000000 | (Mash << 9) | pllnumber |4 ; //4 is START CLK
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SetClkDivFrac(FreqDivider,FreqFractionnal);
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return 0;
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}
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@ -162,6 +175,7 @@ void clkgpio::print_clock_tree(void)
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printf("TIMER CTL=%08x DIV=%8x\n",gpioreg[58],gpioreg[59]);
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printf("UART CTL=%08x DIV=%8x ",gpioreg[60],gpioreg[61]);
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printf("VEC CTL=%08x DIV=%8x\n",gpioreg[62],gpioreg[63]);
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printf("PULSE CTL=%08x DIV=%8x ",gpioreg[100],gpioreg[101]);
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printf("PLLT CTL=%08x DIV=????????\n",gpioreg[76]);
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@ -170,10 +184,15 @@ void clkgpio::print_clock_tree(void)
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printf("DSI1P CTL=%08x DIV=%8x\n",gpioreg[88],gpioreg[89]);
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printf("AVE0 CTL=%08x DIV=%8x\n",gpioreg[90],gpioreg[91]);
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printf("SDC CTL=%08x DIV=%8x ",gpioreg[106],gpioreg[107]);
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printf("ARM CTL=%08x DIV=%8x\n",gpioreg[108],gpioreg[109]);
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printf("AVE0 CTL=%08x DIV=%8x ",gpioreg[110],gpioreg[111]);
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printf("EMMC CTL=%08x DIV=%8x\n",gpioreg[112],gpioreg[113]);
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printf("CMPLLA=%08x ",gpioreg[0x104/4]);
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printf("CMPLLC=%08x \n",gpioreg[0x108/4]);
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printf("CMPLLD=%08x ",gpioreg[0x10C/4]);
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printf("CMPLLH=%08x \n",gpioreg[0x110/4]);
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printf("EMMC CTL=%08x DIV=%8x\n",gpioreg[112],gpioreg[113]);
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printf("EMMC CTL=%08x DIV=%8x\n",gpioreg[112],gpioreg[113]);
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printf("EMMC CTL=%08x DIV=%8x\n",gpioreg[112],gpioreg[113]);
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// Sometimes calculated frequencies are off by a factor of 2
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// ANA1 bit 14 may indicate that a /2 prescaler is active
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@ -248,6 +267,7 @@ int pwmgpio::SetPllNumber(int PllNo,int MashType)
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else
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Mash=0;
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clk.gpioreg[PWMCLK_CNTL]= 0x5A000000 | (Mash << 9) | pllnumber|(0 << 4) ; //4 is STOP CLK
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usleep(100);
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Pllfrequency=GetPllFrequency(pllnumber);
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return 0;
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}
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@ -266,8 +286,9 @@ int pwmgpio::SetFrequency(uint64_t Frequency)
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uint32_t FreqFractionnal=(uint32_t) (4096*(Freqresult-(double)FreqDivider));
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if((FreqDivider>4096)||(FreqDivider<2)) fprintf(stderr,"Frequency out of range\n");
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clk.gpioreg[PWMCLK_DIV] = 0x5A000000 | ((FreqDivider)<<12) | FreqFractionnal;
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usleep(10);
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usleep(100);
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clk.gpioreg[PWMCLK_CNTL]= 0x5A000000 | (Mash << 9) | pllnumber|(1 << 4) ; //4 is STAR CLK
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usleep(100);
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return 0;
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}
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@ -119,6 +119,7 @@ class clkgpio:public gpio
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uint64_t GetPllFrequency(int PllNo);
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void print_clock_tree(void);
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int SetFrequency(uint64_t Frequency);
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int SetClkDivFrac(uint32_t Div,uint32_t Frac);
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};
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@ -0,0 +1,81 @@
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#include "stdio.h"
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#include "ngfmdmasync.h"
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ngfmdmasync::ngfmdmasync(uint64_t TuneFrequency,uint32_t SampleRate,int Channel,uint32_t FifoSize):dma(Channel,FifoSize*2,FifoSize)
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{
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tunefreq=TuneFrequency;
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clkgpio::SetPllNumber(clk_plla,0); // Use PPL_A , Do not USE MASH which generates spurious
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clkgpio::gpioreg[0x104/4]=0x5A00020A; // Enable Plla_PER
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clkgpio::gpioreg[PLLA_PER]=0x5A000002; // Div ?
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double FloatMult=((double)TuneFrequency)/(double)(XOSC_FREQUENCY);
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uint32_t freqctl = FloatMult*((double)(1<<20)) ;
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int IntMultiply= freqctl>>20; // Need to be calculated to have a center frequency
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freqctl&=0xFFFFF; // Fractionnal is 20bits
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//fprintf(stderr,"freqctl=%d\n", freqctl);
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uint32_t FracMultiply=freqctl&0xFFFFC; // Check if last 2 bits are really there
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clkgpio::gpioreg[PLLA_CTRL] = (0x5a<<24) | (0x21<<12) | IntMultiply;
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//clkgpio::gpioreg[PLLA_FRAC] = (0x5a<<24) | (0xFFFF);
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SetClkDivFrac(2,0); // CLK is not divided for now !
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pwmgpio::SetPllNumber(clk_osc,1);
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pwmgpio::SetFrequency(SampleRate);
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pwmgpio::SetMode(0);
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//clkgpio::print_clock_tree();
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SetDmaAlgo();
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FillMemory(FracMultiply);
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}
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ngfmdmasync::~ngfmdmasync()
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{
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}
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void ngfmdmasync::SetDmaAlgo()
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{
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dma_cb_t *cbp = cbarray;
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for (uint32_t samplecnt = 0; samplecnt < cbsize/2; samplecnt++) { //cbsize/2 because we have 2 CB by sample
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// Write a frequency sample
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cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[samplecnt]);
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cbp->dst = 0x7E000000 + (PLLA_FRAC<<2) + CLK_BASE ;
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cbp->length = 4;
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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//fprintf(stderr,"cbp : sample %x src %x dest %x next %x\n",samplecnt,cbp->src,cbp->dst,cbp->next);
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cbp++;
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// Delay
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cbp->info = /*BCM2708_DMA_SRC_IGNOR | */BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
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cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
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cbp->dst = 0x7E000000 + (PWM_FIFO<<2) + PWM_BASE ;
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cbp->length = 4;
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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//fprintf(stderr,"cbp : sample %x src %x dest %x next %x\n",samplecnt,cbp->src,cbp->dst,cbp->next);
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cbp++;
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}
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cbp--;
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cbp->next = mem_virt_to_phys(cbarray); // We loop to the first CB
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//fprintf(stderr,"Last cbp : src %x dest %x next %x\n",cbp->src,cbp->dst,cbp->next);
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}
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void ngfmdmasync::FillMemory(uint32_t FirstFrac)
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{
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if(FirstFrac<usermemsize) FirstFrac=usermemsize;
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for (uint32_t samplecnt = 0; samplecnt < usermemsize; samplecnt++)
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{
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uint32_t Frac=(FirstFrac+samplecnt*((samplecnt%2==0)?1:-1))&0xFFFFF;
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usermem[samplecnt]=0x5A000000 | Frac;
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}
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}
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@ -0,0 +1,19 @@
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#ifndef DEF_NGFMDMASYNC
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#define DEF_NGFMDMASYNC
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#include "stdint.h"
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#include "dma.h"
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#include "gpio.h"
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class ngfmdmasync:public dma,clkgpio,pwmgpio
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{
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protected:
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uint64_t tunefreq;
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public:
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ngfmdmasync(uint64_t TuneFrequency,uint32_t SampleRate,int Channel,uint32_t FifoSize);
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~ngfmdmasync();
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void SetDmaAlgo();
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void FillMemory(uint32_t FirstFrac);
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};
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#endif
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@ -2,38 +2,38 @@
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#include "dma.h"
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#include "gpio.h"
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#include "fmdmasync.h"
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#include "ngfmdmasync.h"
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#include "stdio.h"
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int main(int argc, char* argv[])
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{
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clkgpio clk;
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//clk.print_clock_tree();
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clk.SetPllNumber(clk_plld,1);
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generalgpio generalio;
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generalio.enableclk();
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ngfmdmasync ngfmtest(751000000,10000,14,1024);
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ngfmtest.start();
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sleep(30);
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ngfmtest.stop();
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// Test Fmdmasync
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/*
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pwmgpio pwm;
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pwm.SetPllNumber(clk_osc,1);
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pwm.SetFrequency(10000);
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pwm.SetFrequency(5000);
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pwm.SetMode(0);
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//clk.SetFrequency(89100000);
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fmdmasync fmtest(14,400);
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fmdmasync fmtest(14,72);
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fmtest.start();
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for(int i=0;i<10000;i++)
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{
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}
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sleep(10);
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fmtest.stop();
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}
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/*
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{
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for(int i=0;i<10000;i++)
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{
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usleep(50);
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clk.SetFrequency(89000000+(i%2)*200000);
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}
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}*/
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}
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sleep(180);
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fmtest.stop();
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*/
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}
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