kopia lustrzana https://github.com/F5OEO/rpidatv
Digithin 4MHZ depends on PLL
rodzic
37255fcc61
commit
096b395958
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@ -401,7 +401,9 @@ int InitIQ(int DigithinMode)
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uint32_t DigiThin_ClockBySymbol=0;
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// CLK_DIGITHIN 500MHZ(PLLD)/4MHZ = 125
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#define CLK_4MHZ 125
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int CLK_DIGITHIN=PLLFREQ_PCM/4E6;
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//#define CLK_4MHZ 125
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if(DigithinMode==1)
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{
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@ -411,11 +413,11 @@ int InitIQ(int DigithinMode)
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usleep(1000);
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clk_reg[GPCLK_CNTL] = 0x5A << 24 |0<<4 | PLL_PCM;
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usleep(1000);
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clk_reg[GPCLK_DIV] = 0x5A << 24 | (CLK_4MHZ<<12) ; //CLK FREQ = 4MHZ: Fixed for Digithin
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clk_reg[GPCLK_DIV] = 0x5A << 24 | (CLK_DIGITHIN<<12) ; //CLK FREQ = 4MHZ: Fixed for Digithin
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usleep(100);
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DigiThin_ClockBySymbol=( PLLFREQ_PCM/(CLK_4MHZ));
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DigiThin_ClockBySymbol=( PLLFREQ_PCM/(CLK_DIGITHIN));
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//SRClock=DigiThin_ClockBySymbol*CLK_4MHZ;
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printf("Digithin Clock at 4MHZ:%ld clock by Symbol (SR=%d)\n",(long int)DigiThin_ClockBySymbol,4000000/(SymbolRate*1000));
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printf("Digithin Clock at 4MHZ:%ld clock by Symbol (SR=%d)\n",(long int)DigiThin_ClockBySymbol,4000000/(SymbolRate*1000L));
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udelay(500);
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clk_reg[GPCLK_CNTL] = 0x5A << 24 | 0 << 9 | 1 << 4 | PLL_PCM; //NO MASH !!!
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udelay(500);
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