kopia lustrzana https://github.com/F5OEO/librpitx
Work on spurious - still investigate
F5OEO
rodzic
9e757ea566
commit
8d0ff49fa7
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@ -6,23 +6,52 @@
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#include <signal.h>
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bool running=true;
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/*int
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gcd ( int a, int b )
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{
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int c;
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while ( a != 0 ) {
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c = a; a = b%a; b = c;
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}
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return b;
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}*/
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uint64_t gcd(uint64_t x,uint64_t y)
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{
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return y == 0 ? x : gcd(y, x % y);
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}
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uint64_t lcm(uint64_t x, uint64_t y)
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{
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return x * y / gcd(x, y);
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}
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void SimpleTest(uint64_t Freq)
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{
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generalgpio genpio;
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fprintf(stderr,"GPIOPULL =%x\n",genpio.gpioreg[GPPUDCLK0]);
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#define PULL_OFF 0
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#define PULL_DOWN 1
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#define PULL_UP 2
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genpio.gpioreg[GPPUD]=PULL_DOWN;
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usleep(100);
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genpio.gpioreg[GPPUD]=1;//PULL_DOWN;
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usleep(150);
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genpio.gpioreg[GPPUDCLK0]=(1<<4); //GPIO CLK is GPIO 4
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usleep(100);
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//genpio.gpioreg[GPPUDCLK0]=(0); //GPIO CLK is GPIO 4
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usleep(150);
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genpio.gpioreg[GPPUDCLK0]=(0); //GPIO CLK is GPIO 4
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//genpio.setpulloff(4);
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padgpio pad;
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pad.setlevel(7);
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clkgpio clk;
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clk.print_clock_tree();
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clk.SetPllNumber(clk_plld,1);
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clk.SetAdvancedPllMode(true);
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clk.SetPllNumber(clk_plla,0);
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//clk.SetAdvancedPllMode(true);
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//clk.SetPLLMasterLoop(0,4,0);
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//clk.Setppm(+7.7);
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clk.SetCenterFrequency(Freq,1000);
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double freqresolution=clk.GetFrequencyResolution();
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@ -30,14 +59,47 @@ void SimpleTest(uint64_t Freq)
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fprintf(stderr,"Frequency resolution=%f Error freq=%f\n",freqresolution,RealFreq);
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int Deviation=0;
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clk.SetFrequency(000);
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clk.enableclk(4);
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clk.enableclk(4);
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usleep(100);
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//clk.SetClkDivFrac(100,0); // If mash!=0 update doesnt seem to work
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int count=0;
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while(running)
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{
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clk.SetFrequency(000);
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//clk.SetMasterMultFrac(44,(1<<count));
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//uint32_t N=(1<<18);
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uint32_t N=(1<<13)*count;
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//clk.SetMasterMultFrac(34,N);
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printf("count =%d gcd%d spurious%f N=%x %f\n",count,lcm(N,1<<20),(double)gcd(1<<20,N)*19.2e6/(double)(1<<20),N,N/(float)(1<<20));
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count=(count+1)%128;
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//usleep(10000000);
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int a=getc(stdin);
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static int Ki=4,Kp=0,Ka=0;
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Kp=Kp+1;
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if(Kp>15)
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{ Kp=0;
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Ki=Ki+1;
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}
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//Ki=Ki+1;
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if(Ki>11)
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{
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Ki=4;
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Ka++;
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}
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Ki=Kp;
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clk.SetClkDivFrac(count,count);
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//clk.SetPLLMasterLoop(Ki,4,Ka);
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//clk.SetPLLMasterLoop(2,4,0);
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//clk.SetPLLMasterLoop(3,4,0); //best one
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//printf("Ki=%d :Kp %d Ka %d\n ",Ki,Kp,Ka);
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/*clk.SetFrequency(000);
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sleep(5);
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clk.SetFrequency(freqresolution);
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sleep(5);
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sleep(5);*/
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}
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/*
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for(int i=0;i<100000;i+=1)
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@ -64,6 +64,8 @@ dma::dma(int Channel,uint32_t CBSize,uint32_t UserMemSize) // Fixme! Need to che
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dma_reg.gpioreg[DMA_CS+channel*0x40] = BCM2708_DMA_RESET|DMA_CS_INT; // Remove int flag
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usleep(100);
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dma_reg.gpioreg[DMA_CONBLK_AD+channel*0x40]=mem_virt_to_phys((void*)cbarray ); // reset to beginning
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//get_clocks(mbox.handle);
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}
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void dma::GetRpiInfo()
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77
src/gpio.cpp
77
src/gpio.cpp
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@ -29,6 +29,11 @@ gpio::gpio(uint32_t base, uint32_t len)
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{
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gpioreg = (uint32_t *)mapmem(base, len);
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/*int mhandle=mbox_open();
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get_clocks(mhandle);
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mbox_close(mhandle);
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*/
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}
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uint32_t gpio::GetPeripheralBase()
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@ -144,8 +149,10 @@ int clkgpio::SetFrequency(double Frequency)
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uint32_t freqctl = FloatMult * ((double)(1 << 20));
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int IntMultiply = freqctl >> 20; // Need to be calculated to have a center frequency
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freqctl &= 0xFFFFF; // Fractionnal is 20bits
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uint32_t FracMultiply = freqctl & 0xFFFFF;
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//gpioreg[PLLA_FRAC]= 0x5A000000 | FracMultiply ; // Only Frac is Sent
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//uint32_t FracMultiply = 0.75*(1<<20);
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SetMasterMultFrac(IntMultiply, FracMultiply);
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}
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else
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@ -192,7 +199,7 @@ int clkgpio::ComputeBestLO(uint64_t Frequency, int Bandwidth)
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int divider, min_int_multiplier, max_int_multiplier, fom, int_multiplier, best_fom = 0;
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double frac_multiplier;
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best_divider = 0;
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for (divider = 1; divider < 4096; divider++)//1 is allowed only for MASH=0
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for (divider = 2; divider < 4096; divider++)//1 is allowed only for MASH=0
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{
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if (Frequency * divider < 600e6)
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continue; // widest accepted frequency range
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@ -202,7 +209,11 @@ int clkgpio::ComputeBestLO(uint64_t Frequency, int Bandwidth)
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max_int_multiplier = ((int)((double)(Frequency + Bandwidth) * divider * xtal_freq_recip));
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min_int_multiplier = ((int)((double)(Frequency - Bandwidth) * divider * xtal_freq_recip));
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if (min_int_multiplier != max_int_multiplier)
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continue; // don't cross integer boundary
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{
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//fprintf(stderr,"Warning : cross boundary frequency\n");
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continue; // don't cross integer boundary
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}
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// continue; // don't cross integer boundary
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solution_count++; // if we make it here the solution is acceptable,
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fom = 0; // but we want a good solution
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@ -219,16 +230,18 @@ int clkgpio::ComputeBestLO(uint64_t Frequency, int Bandwidth)
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frac_multiplier = ((double)(Frequency)*divider * xtal_freq_recip);
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int_multiplier = (int)frac_multiplier;
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frac_multiplier = frac_multiplier - int_multiplier;
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if ((int_multiplier % 2) == 0)
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fom++;
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if ((frac_multiplier > 0.4) && (frac_multiplier < 0.6))
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//if ((int_multiplier % 2) == 0)
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// fom++;
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//if (((frac_multiplier > 0.7) && (frac_multiplier < 1.0))||((frac_multiplier > 0.0) && (frac_multiplier < 0.3)))
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if (((frac_multiplier > 0.2) && (frac_multiplier < 0.3))||((frac_multiplier > 0.7) && (frac_multiplier < 0.8)))
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//if (((frac_multiplier > 0.4) && (frac_multiplier < 0.6)))
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fom += 2; // prefer mulipliers away from integer boundaries
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//if( divider%2 == 1 ) fom+=2; // prefer odd dividers
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// Even and odd dividers could have different harmonic content,
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// but the latest measurements have shown no significant difference.
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printf("Try multiplier:%f divider:%d VCO: %4.1fMHz\n",Frequency*divider*xtal_freq_recip,divider,(double)Frequency*divider/1e6);
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//printf("Try multiplier:%f divider:%d VCO: %4.1fMHz Spurious %f\n",Frequency*divider*xtal_freq_recip,divider,(double)Frequency*divider/1e6,frac_multiplier*19.2e6/(double)divider);
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if (fom > best_fom)
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{
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best_fom = fom;
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@ -238,7 +251,7 @@ int clkgpio::ComputeBestLO(uint64_t Frequency, int Bandwidth)
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if (solution_count > 0)
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{
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PllFixDivider = best_divider;
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fprintf(stderr, " multiplier:%f divider:%d VCO: %4.1fMHz\n", Frequency * best_divider * xtal_freq_recip, best_divider, (double)Frequency * best_divider / 1e6);
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//fprintf(stderr, " multiplier:%f divider:%d VCO: %4.1fMHz Spurious %f \n", Frequency * best_divider * xtal_freq_recip, best_divider, (double)Frequency * best_divider / 1e6,frac_multiplier*xtal_freq_recip/(double)divider);
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return 0;
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}
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else
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@ -289,7 +302,7 @@ int clkgpio::SetCenterFrequency(uint64_t Frequency, int Bandwidth)
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fprintf(stderr, "Master PLLA Locked\n");
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else
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fprintf(stderr, "Warning ! Master PLLA NOT Locked !!!!\n");
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SetClkDivFrac(PllFixDivider, 0); // NO MASH !!!!
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SetClkDivFrac(PllFixDivider, 0x0); // NO MASH !!!!
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usleep(100);
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usleep(100);
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@ -319,29 +332,48 @@ void clkgpio::SetAdvancedPllMode(bool Advanced)
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if (ModulateFromMasterPLL)
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{
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SetPllNumber(clk_plla, 0); // Use PPL_A , Do not USE MASH which generates spurious
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gpioreg[0x104 / 4] = 0x5A00022A; // Enable Plla_PER
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gpioreg[CM_PLLA] = 0x5A00022A; // Enable Plla_PER
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usleep(100);
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uint32_t ana[4];
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for (int i = 3; i >= 0; i--)
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{
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ana[i] = gpioreg[(0x1010 / 4) + i];
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ana[i] = gpioreg[(A2W_PLLA_ANA0 ) + i];
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}
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ana[1]&=~(1<<14); // No use prediv means Frequency
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//ana[1] |= (1 << 14); // use prediv means Frequency*2
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for (int i = 3; i >= 0; i--)
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{
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gpioreg[(0x1010 / 4) + i] = (0x5A << 24) | ana[i];
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gpioreg[(A2W_PLLA_ANA0 ) + i] = (0x5A << 24) | ana[i];
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}
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usleep(100);
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gpioreg[PLLA_CORE] = 0x5A000001; // Div ?
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gpioreg[PLLA_PER] = 0x5A000001; // Div ?
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gpioreg[PLLA_CORE] = 0x5A000000|(1<<8);//Disable
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gpioreg[PLLA_PER] = 0x5A000001; // Divisor
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usleep(100);
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}
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}
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void clkgpio::SetPLLMasterLoop(int Ki,int Kp,int Ka)
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{
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uint32_t ana[4];
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for (int i = 3; i >= 0; i--)
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{
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ana[i] = gpioreg[(A2W_PLLA_ANA0 ) + i];
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}
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ana[1]=(Ki<<A2W_PLL_KI_SHIFT)|(Kp<<A2W_PLL_KP_SHIFT)|(Ka<<A2W_PLL_KA_SHIFT);
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fprintf(stderr,"Loop parameter =%x\n",ana[1]);
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for (int i = 3; i >= 0; i--)
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{
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gpioreg[(A2W_PLLA_ANA0 ) + i] = (0x5A << 24) | ana[i];
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}
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usleep(100) ;
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//Only PLLA for now
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}
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void clkgpio::print_clock_tree(void)
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{
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@ -519,6 +551,17 @@ int generalgpio::setmode(uint32_t gpio, uint32_t mode)
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return 0;
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}
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int generalgpio::setpulloff(uint32_t gpio)
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{
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gpioreg[GPPUD]=0;
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usleep(150);
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gpioreg[GPPUDCLK0]=1<<gpio;
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usleep(150);
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gpioreg[GPPUDCLK0]=0;
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return 0;
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}
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// ********************************** PWM GPIO **********************************
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pwmgpio::pwmgpio() : gpio(GetPeripheralBase() + PWM_BASE, PWM_LEN)
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@ -762,3 +805,9 @@ padgpio::padgpio() : gpio(GetPeripheralBase() + PADS_GPIO, PADS_GPIO_LEN)
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padgpio::~padgpio()
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{
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}
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int padgpio::setlevel(int level)
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{
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gpioreg[PADS_GPIO_0]=0x5a000000 + (level&0x7) + (0<<4) + (0<<3);
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return 0;
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}
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36
src/gpio.h
36
src/gpio.h
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@ -64,7 +64,8 @@ class dmagpio:public gpio
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#define GPFSEL1 (0x04/4)
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#define GPFSEL2 (0x08/4)
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#define GPPUD (0x94/4)
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#define GPPUDCLK0 (0x9C/4)
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#define GPPUDCLK0 (0x98/4)
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#define GPPUDCLK1 (0x9C/4)
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enum {fsel_input,fsel_output,fsel_alt5,fsel_alt4,fsel_alt0,fsel_alt1,fsel_alt2,fsel_alt3};
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@ -75,12 +76,13 @@ class generalgpio:public gpio
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generalgpio();
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int setmode(uint32_t gpio, uint32_t mode);
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~generalgpio();
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int setpulloff(uint32_t gpio);
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};
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// Add for PLL frequency CTRL wihout divider
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// https://github.com/raspberrypi/linux/blob/rpi-4.9.y/drivers/clk/bcm/clk-bcm2835.c
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// See interesting patch for jitter https://github.com/raspberrypi/linux/commit/76527b4e6a5dbe55e0b2d8ab533c2388b36c86be
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#define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l))
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#define CLK_BASE (0x00101000)
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#define CLK_LEN 0x1300
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@ -99,6 +101,34 @@ class generalgpio:public gpio
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# define CM_LOCK_FLOCKB (1<<9)
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# define CM_LOCK_FLOCKA (1<<8)
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#define CM_PLLA (0x104/4)
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/*
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# define CM_PLL_ANARST BIT(8)
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# define CM_PLLA_HOLDPER BIT(7)
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# define CM_PLLA_LOADPER BIT(6)
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# define CM_PLLA_HOLDCORE BIT(5)
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# define CM_PLLA_LOADCORE BIT(4)
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# define CM_PLLA_HOLDCCP2 BIT(3)
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# define CM_PLLA_LOADCCP2 BIT(2)
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# define CM_PLLA_HOLDDSI0 BIT(1)
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# define CM_PLLA_LOADDSI0 BIT(0)
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*/
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#define CM_PLLC (0x108/4)
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#define CM_PLLD (0x10c/4)
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#define CM_PLLH (0x110/4)
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#define CM_PLLB (0x170/4)
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#define A2W_PLLA_ANA0 (0x1010/4)
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#define A2W_PLLC_ANA0 (0x1030/4)
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#define A2W_PLLD_ANA0 (0x1050/4)
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#define A2W_PLLH_ANA0 (0x1070/4)
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#define A2W_PLLB_ANA0 (0x10f0/4)
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#define A2W_PLL_KA_SHIFT 7
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#define A2W_PLL_KI_SHIFT 19
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#define A2W_PLL_KP_SHIFT 15
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#define PLLA_CTRL (0x1100/4)
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#define PLLA_FRAC (0x1200/4)
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#define PLLA_DSI0 (0x1300/4)
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@ -171,6 +201,7 @@ class clkgpio:public gpio
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void disableclk(int gpio);
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void Setppm(double ppm);
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void SetppmFromNTP();
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void SetPLLMasterLoop(int Ki,int Kp,int Ka);
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};
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@ -284,6 +315,7 @@ class padgpio:public gpio
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public:
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padgpio();
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~padgpio();
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int setlevel(int level);
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};
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#endif
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@ -25,3 +25,4 @@ This program is free software: you can redistribute it and/or modify
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#include "amdmasync.h"
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#include "fskburst.h"
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#include "dsp.h"
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@ -246,6 +246,28 @@ unsigned execute_qpu(int file_desc, unsigned num_qpus, unsigned control, unsigne
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return p[5];
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}
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unsigned get_clocks(int file_desc ) //FixMe !!!!!!
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{
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int i=0;
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unsigned p[256];
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p[i++] = 0; // size
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p[i++] = 0x00000000; // process request
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p[i++] = 0x00010007; // (the tag id)
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p[i++] = 0; // (size of the buffer)
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p[i++] = 128; // (size of the data)
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p[i++] = 0x00000000; // end tag
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p[0] = i*sizeof *p; // actual size
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mbox_property(file_desc, p);
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fprintf(stderr,"Clock size = %d\n",p[4]&0xFFF);
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for(i=0;i<128/4;i++) fprintf(stderr,"%x ",p[i]);
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fprintf(stderr,"\n");
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return p[5];
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}
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int mbox_open() {
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int file_desc;
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@ -53,4 +53,5 @@ void *unmapmem(void *addr, unsigned size);
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unsigned execute_code(int file_desc, unsigned code, unsigned r0, unsigned r1, unsigned r2, unsigned r3, unsigned r4, unsigned r5);
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unsigned execute_qpu(int file_desc, unsigned num_qpus, unsigned control, unsigned noflush, unsigned timeout);
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unsigned qpu_enable(int file_desc, unsigned enable);
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unsigned get_clocks(int file_desc );
|
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#endif
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||||
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Ładowanie…
Reference in New Issue