Add 2nd clock:experimental

src/gpio.cpp

@@ -70,7 +70,7 @@ clkgpio::clkgpio() : gpio(GetPeripheralBase() + CLK_BASE, CLK_LEN)
 clkgpio::~clkgpio()
 {
 	gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (0 << 4); //4 is START CLK
-
+	gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (0 << 4); //4 is START CLK
 	usleep(100);
 }
 
@@ -87,6 +87,7 @@ int clkgpio::SetPllNumber(int PllNo, int MashType)
 	else
 		Mash = 0;
 	gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber /*|(1 << 5)*/; //5 is Reset CLK
+	gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber /*|(1 << 5)*/; //5 is Reset CLK
 	usleep(100);
 	Pllfrequency = GetPllFrequency(pllnumber);
 	return 0;
@@ -123,6 +124,7 @@ int clkgpio::SetClkDivFrac(uint32_t Div, uint32_t Frac)
 {
 
 	gpioreg[GPCLK_DIV] = 0x5A000000 | ((Div) << 12) | Frac;
+	gpioreg[GPCLK_DIV_2] = 0x5A000000 | ((Div) << 12) | Frac;
 	usleep(100);
 	fprintf(stderr, "Clk Number %d div %d frac %d\n", pllnumber, Div, Frac);
 	//gpioreg[GPCLK_CNTL]= 0x5A000000 | (Mash << 9) | pllnumber |(1<<4)  ; //4 is START CLK
@@ -307,14 +309,17 @@ int clkgpio::SetCenterFrequency(uint64_t Frequency, int Bandwidth)
 
 		usleep(100);
 		gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
+		gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
 		usleep(100);
 		gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
+		gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
 		usleep(100);
 	}
 	else
 	{
 		GetPllFrequency(pllnumber);											   // Be sure to get the master PLL frequency
 		gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
+		gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
 	}
 	return 0;
 }
@@ -323,7 +328,9 @@ void clkgpio::SetPhase(bool inversed)
 {
 	uint32_t StateBefore = clkgpio::gpioreg[GPCLK_CNTL];
 	clkgpio::gpioreg[GPCLK_CNTL] = (0x5A << 24) | StateBefore | ((inversed ? 1 : 0) << 8) | 1 << 5;
+	clkgpio::gpioreg[GPCLK_CNTL_2] = (0x5A << 24) | StateBefore | ((inversed ? 1 : 0) << 8) | 1 << 5;
 	clkgpio::gpioreg[GPCLK_CNTL] = (0x5A << 24) | StateBefore | ((inversed ? 1 : 0) << 8) | 0 << 5;
+	clkgpio::gpioreg[GPCLK_CNTL_2] = (0x5A << 24) | StateBefore | ((inversed ? 1 : 0) << 8) | 0 << 5;
 }
 //Should inspect https://github.com/raspberrypi/linux/blob/ffd7bf4085b09447e5db96edd74e524f118ca3fe/drivers/clk/bcm/clk-bcm2835.c#L695
 void clkgpio::SetAdvancedPllMode(bool Advanced)
@@ -487,6 +494,10 @@ void clkgpio::enableclk(int gpio)
 	case 34:
 		gengpio.setmode(gpio, fsel_alt0);
 		break;
+	//CLK2	
+	case 6:
+		gengpio.setmode(gpio, fsel_alt0);
+		break;	
 	default:
 		fprintf(stderr, "gpio %d has no clk - available(4,20,32,34)\n", gpio);
 		break;

src/gpio.h

@@ -92,6 +92,8 @@ class generalgpio:public gpio
 #define CORECLK_DIV       (0x0c/4)
 #define GPCLK_CNTL        (0x70/4)
 #define GPCLK_DIV         (0x74/4)
+#define GPCLK_CNTL_2	 (0x80/4)
+#define GPCLK_DIV_2      (0x84/4)
 #define EMMCCLK_CNTL     (0x1C0/4)
 #define EMMCCLK_DIV      (0x1C4/4)