388 wiersze
13 KiB
C
388 wiersze
13 KiB
C
// 1-channel LoRa Gateway for ESP8266
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// Copyright (c) 2016, 2017 Maarten Westenberg version for ESP8266
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// Version 5.0.6
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// Date: 2018-02-12
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//
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// based on work done by Thomas Telkamp for Raspberry PI 1ch gateway
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// and many other contributors.
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//
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// All rights reserved. This program and the accompanying materials
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// are made available under the terms of the MIT License
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// which accompanies this distribution, and is available at
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// https://opensource.org/licenses/mit-license.php
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//
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// Author: Maarten Westenberg (mw12554@hotmail.com)
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//
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// This file contains a number of compile-time settings and declarations that are
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// specific to the LoRa rfm95, sx1276, sx1272 radio of the gateway.
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//
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//
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// ------------------------------------------------------------------------------------
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// ----------------------------------------
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// Used by REG_PAYLOAD_LENGTH to set receive payload length
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#define PAYLOAD_LENGTH 0x40 // 64 bytes
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#define MAX_PAYLOAD_LENGTH 0x80 // 128 bytes
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// In order to make the CAD behaviour dynamic we set a variable
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// when the CAD functions are defined. Value of 3 is minimum frequencies a
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// gateway should support to be fully LoRa compliant.
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#define NUM_HOPS 2 // 3 should be the minimum
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// Do not change these setting for RSSI detection. They are used for CAD
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// Given the correction factor of 157, we can get to -122dB with this rating
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//
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#define RSSI_LIMIT 35 //
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// How long to wait in LoRa mode before using the RSSI value.
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// This period should be as short as possible, yet sufficient
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//
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#define RSSI_WAIT 6 // was 25
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// How long will it take when hopping before a CDONE or CDETD value
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// is measured.
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//
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#define EVENT_WAIT 600 // was 200
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// Our code should correct the server Tramission delay settings
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long txDelay= 0x00; // tx delay time on top of server TMST
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// SPI setting. 8MHz seems to be the max
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#define SPISPEED 8000000 // Set to 8 * 10E6
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// Frequencies
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// Set center frequency. If in doubt, choose the first one, comment all others
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// Each "real" gateway should support the first 3 frequencies according to LoRa spec.
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int freqs [] = {
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868100000, // Channel 0, 868.1 MHz primary
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868300000, // Channel 1, 868.3 MHz mandatory
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868500000, // Channel 2, 868.5 MHz mandatory
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867100000, // Channel 3, 867.1 MHz Optional
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867300000,
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867500000,
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867700000,
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867900000,
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868800000,
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869525000 // Channel, for responses gateway (10%)
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// TTN defines an additional channel at 869.525Mhz using SF9 for class B. Not used
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};
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uint32_t freq = freqs[0];
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uint8_t ifreq = 0; // Channel Index
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// Set the structure for spreading factor
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enum sf_t { SF6=6, SF7, SF8, SF9, SF10, SF11, SF12 };
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// The state of the receiver. See Semtech Datasheet (rev 4, March 2015) page 43
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// The _state is of the enum type (and should be cast when used as a number)
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enum state_t { S_INIT=0, S_SCAN, S_CAD, S_RX, S_TX, S_TXDONE};
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volatile state_t _state;
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volatile uint8_t _event=0;
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// rssi is measured at specific moments and reported on others
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// so we need to store the current value we like to work with
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uint8_t _rssi;
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bool _cad= (bool) _CAD; // Set to true for Channel Activity Detection, only when dio 1 connected
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bool _hop=false; // experimental; frequency hopping. Only use when dio2 connected
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bool inHop=false;
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unsigned long nowTime=0;
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unsigned long msgTime=0;
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unsigned long hopTime=0;
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unsigned long detTime=0;
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#if _PIN_OUT==1
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// Definition of the GPIO pins used by the Gateway for Hallard type boards
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//
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struct pins {
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uint8_t dio0=15; // GPIO15 / D8. For the Hallard board shared between DIO0/DIO1/DIO2
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uint8_t dio1=15; // GPIO15 / D8. Used for CAD, may or not be shared with DIO0
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uint8_t dio2=15; // GPIO15 / D8. Used for frequency hopping, don't care
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uint8_t ss=16; // GPIO16 / D0. Select pin connected to GPIO16 / D0
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uint8_t rst=0; // GPIO 0 / D3. Reset pin not used
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// MISO 12 / D6
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// MOSI 13 / D7
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// CLK 14 / D5
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} pins;
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#elif _PIN_OUT==2
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// For ComResult gateway PCB use the following settings
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struct pins {
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uint8_t dio0=5; // GPIO5 / D1. Dio0 used for one frequency and one SF
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uint8_t dio1=4; // GPIO4 / D2. Used for CAD, may or not be shared with DIO0
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uint8_t dio2=0; // GPIO0 / D3. Used for frequency hopping, don't care
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uint8_t ss=15; // GPIO15 / D8. Select pin connected to GPIO15
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uint8_t rst=0; // GPIO0 / D3. Reset pin not used
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} pins;
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#elif _PIN_OUT==3
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// For ESP32 based board
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// SCK == GPIO5/ PIN5
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// SS == GPIO18/PIN18
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// MISO == GPIO19/ PIN19
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// MOSI == GPIO27/ PIN27
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// RST == GPIO14/ PIN14
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struct pins {
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uint8_t dio0=26; // GPIO26 / Dio0 used for one frequency and one SF
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uint8_t dio1=26; // GPIO26 / Used for CAD, may or not be shared with DIO0
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uint8_t dio2=26; // GPI26 / Used for frequency hopping, don't care
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uint8_t ss=18; // GPIO18 / Dx. Select pin connected to GPIO18
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uint8_t rst=14; // GPIO0 / D3. Reset pin not used
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} pins;
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#else
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// Use your own pin definitions, and comment #error line below
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// MISO 12 / D6
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// MOSI 13 / D7
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// CLK 14 / D5
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// SS 16 / D0
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#error "Pin Definitions _PIN_OUT must be 1(HALLARD) or 2 (COMRESULT)"
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#endif
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// STATR contains the statictis that are kept by message.
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// Ech time a message is received or sent the statistics are updated.
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// In case STATISTICS==1 we define the last MAX_STAT messages as statistics
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struct stat_t {
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unsigned long tmst; // Time since 1970 in seconds
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unsigned long node; // 4-byte DEVaddr (the only one known to gateway)
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uint8_t ch; // Channel index to freqs array
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uint8_t sf;
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#if RSSI==1
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int8_t rssi; // XXX Can be < -128
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#endif
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int8_t prssi; // XXX Can be < -128
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} stat_t;
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#if STATISTICS >= 1
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// STATC contains the statistic that are gateway related and not per
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// message. Example: Number of messages received on SF7 or number of (re) boots
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// So where statr contains the statistics gathered per packet the statc
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// contains general statics of the node
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#if STATISTICS >= 2 // Only if we explicitely set it higher
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struct stat_c {
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unsigned long sf7; // Spreading factor 7
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unsigned long sf8; // Spreading factor 8
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unsigned long sf9; // Spreading factor 9
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unsigned long sf10; // Spreading factor 10
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unsigned long sf11; // Spreading factor 11
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unsigned long sf12; // Spreading factor 12
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uint16_t boots; // Number of boots
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uint16_t resets;
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} stat_c;
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struct stat_c statc;
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#endif
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// History of received uplink messages from nodes
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struct stat_t statr[MAX_STAT];
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#else // STATISTICS==0
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struct stat_t statr[1]; // Always have at least one element to store in
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#endif
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// Define the payload structure used to separate interrupt ans SPI
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// processing from the loop() part
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uint8_t payLoad[128]; // Payload i
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struct LoraBuffer {
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uint8_t * payLoad;
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uint8_t payLength;
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uint32_t tmst; // in millis()
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uint8_t sfTx;
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uint8_t powe;
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uint32_t fff;
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uint8_t crc;
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uint8_t iiq;
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} LoraDown;
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// Up buffer (from Lora sensor to UDP)
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//
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struct LoraUp {
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uint8_t payLoad[128];
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uint8_t payLength;
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int prssi;
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long snr;
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int rssicorr;
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uint8_t sf;
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} LoraUp;
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// ============================================================================
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// Set all definitions for Gateway
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// ============================================================================
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// Register definitions. These are the addresses of the TFM95, SX1276 that we
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// need to set in the program.
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#define REG_FIFO 0x00 // rw FIFO address
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#define REG_OPMODE 0x01
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// Register 2 to 5 are unused for LoRa
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#define REG_FRF_MSB 0x06
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#define REG_FRF_MID 0x07
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#define REG_FRF_LSB 0x08
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#define REG_PAC 0x09
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#define REG_PARAMP 0x0A
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#define REG_LNA 0x0C
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#define REG_FIFO_ADDR_PTR 0x0D // rw SPI interface address pointer in FIFO data buffer
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#define REG_FIFO_TX_BASE_AD 0x0E // rw write base address in FIFO data buffer for TX modulator
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#define REG_FIFO_RX_BASE_AD 0x0F // rw read base address in FIFO data buffer for RX demodulator (0x00)
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#define REG_FIFO_RX_CURRENT_ADDR 0x10 // r Address of last packet received
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#define REG_IRQ_FLAGS_MASK 0x11
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#define REG_IRQ_FLAGS 0x12
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#define REG_RX_NB_BYTES 0x13
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#define REG_PKT_SNR_VALUE 0x19
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#define REG_PKT_RSSI 0x1A // latest package
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#define REG_RSSI 0x1B // Current RSSI, section 6.4, or 5.5.5
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#define REG_HOP_CHANNEL 0x1C
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#define REG_MODEM_CONFIG1 0x1D
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#define REG_MODEM_CONFIG2 0x1E
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#define REG_SYMB_TIMEOUT_LSB 0x1F
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#define REG_PAYLOAD_LENGTH 0x22
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#define REG_MAX_PAYLOAD_LENGTH 0x23
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#define REG_HOP_PERIOD 0x24
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#define REG_MODEM_CONFIG3 0x26
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#define REG_RSSI_WIDEBAND 0x2C
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#define REG_INVERTIQ 0x33
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#define REG_DET_TRESH 0x37 // SF6
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#define REG_SYNC_WORD 0x39
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#define REG_TEMP 0x3C
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#define REG_DIO_MAPPING_1 0x40
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#define REG_DIO_MAPPING_2 0x41
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#define REG_VERSION 0x42
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#define REG_PADAC 0x5A
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#define REG_PADAC_SX1272 0x5A
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#define REG_PADAC_SX1276 0x4D
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// ----------------------------------------
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// opModes
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#define SX72_MODE_SLEEP 0x80
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#define SX72_MODE_STANDBY 0x81
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#define SX72_MODE_FSTX 0x82
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#define SX72_MODE_TX 0x83 // 0x80 | 0x03
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#define SX72_MODE_RX_CONTINUOS 0x85
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// ----------------------------------------
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// LMIC Constants for radio registers
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#define OPMODE_LORA 0x80
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#define OPMODE_MASK 0x07
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#define OPMODE_SLEEP 0x00
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#define OPMODE_STANDBY 0x01
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#define OPMODE_FSTX 0x02
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#define OPMODE_TX 0x03
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#define OPMODE_FSRX 0x04
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#define OPMODE_RX 0x05
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#define OPMODE_RX_SINGLE 0x06
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#define OPMODE_CAD 0x07
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// ----------------------------------------
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// LOW NOISE AMPLIFIER
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#define LNA_MAX_GAIN 0x23 // Max gain 0x20 | Boost 0x03
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#define LNA_OFF_GAIN 0x00
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#define LNA_LOW_GAIN 0x20
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// CONF REG
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#define REG1 0x0A
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#define REG2 0x84
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// ----------------------------------------
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// MC1 sx1276 RegModemConfig1
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#define SX1276_MC1_BW_125 0x70
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#define SX1276_MC1_BW_250 0x80
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#define SX1276_MC1_BW_500 0x90
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#define SX1276_MC1_CR_4_5 0x02
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#define SX1276_MC1_CR_4_6 0x04
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#define SX1276_MC1_CR_4_7 0x06
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#define SX1276_MC1_CR_4_8 0x08
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#define SX1276_MC1_IMPLICIT_HEADER_MODE_ON 0x01
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#define SX72_MC1_LOW_DATA_RATE_OPTIMIZE 0x01 // mandated for SF11 and SF12
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// ----------------------------------------
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// MC2 definitions
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#define SX72_MC2_FSK 0x00
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#define SX72_MC2_SF7 0x70 // SF7 == 0x07, so (SF7<<4) == SX7_MC2_SF7
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#define SX72_MC2_SF8 0x80
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#define SX72_MC2_SF9 0x90
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#define SX72_MC2_SF10 0xA0
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#define SX72_MC2_SF11 0xB0
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#define SX72_MC2_SF12 0xC0
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// ----------------------------------------
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// MC3
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#define SX1276_MC3_LOW_DATA_RATE_OPTIMIZE 0x08
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#define SX1276_MC3_AGCAUTO 0x04
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// ----------------------------------------
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// FRF
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#define FRF_MSB 0xD9 // 868.1 Mhz
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#define FRF_MID 0x06
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#define FRF_LSB 0x66
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// ----------------------------------------
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// DIO function mappings D0D1D2D3
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#define MAP_DIO0_LORA_RXDONE 0x00 // 00------ bit 7 and 6
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#define MAP_DIO0_LORA_TXDONE 0x40 // 01------
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#define MAP_DIO0_LORA_CADDONE 0x80 // 10------
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#define MAP_DIO0_LORA_NOP 0xC0 // 11------
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#define MAP_DIO1_LORA_RXTOUT 0x00 // --00---- bit 5 and 4
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#define MAP_DIO1_LORA_FCC 0x10 // --01----
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#define MAP_DIO1_LORA_CADDETECT 0x20 // --10----
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#define MAP_DIO1_LORA_NOP 0x30 // --11----
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#define MAP_DIO2_LORA_FCC0 0x00 // ----00-- bit 3 and 2
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#define MAP_DIO2_LORA_FCC1 0x04 // ----01-- bit 3 and 2
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#define MAP_DIO2_LORA_FCC2 0x08 // ----10-- bit 3 and 2
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#define MAP_DIO2_LORA_NOP 0x0C // ----11-- bit 3 and 2
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#define MAP_DIO3_LORA_CADDONE 0x00 // ------00 bit 1 and 0
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#define MAP_DIO3_LORA_HEADER 0x01 // ------01
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#define MAP_DIO3_LORA_CRC 0x02 // ------10
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#define MAP_DIO3_LORA_NOP 0x03 // ------11
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// FSK specific
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#define MAP_DIO0_FSK_READY 0x00 // 00------ (packet sent / payload ready)
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#define MAP_DIO1_FSK_NOP 0x30 // --11----
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#define MAP_DIO2_FSK_TXNOP 0x04 // ----01--
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#define MAP_DIO2_FSK_TIMEOUT 0x08 // ----10--
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// ----------------------------------------
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// Bits masking the corresponding IRQs from the radio
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#define IRQ_LORA_RXTOUT_MASK 0x80
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#define IRQ_LORA_RXDONE_MASK 0x40
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#define IRQ_LORA_CRCERR_MASK 0x20
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#define IRQ_LORA_HEADER_MASK 0x10
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#define IRQ_LORA_TXDONE_MASK 0x08
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#define IRQ_LORA_CDDONE_MASK 0x04
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#define IRQ_LORA_FHSSCH_MASK 0x02
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#define IRQ_LORA_CDDETD_MASK 0x01
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// ----------------------------------------
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// Definitions for UDP message arriving from server
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#define PROTOCOL_VERSION 0x01
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#define PKT_PUSH_DATA 0x00
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#define PKT_PUSH_ACK 0x01
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#define PKT_PULL_DATA 0x02
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#define PKT_PULL_RESP 0x03
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#define PKT_PULL_ACK 0x04
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#define PKT_TX_ACK 0x05
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#define MGT_RESET 0x15 // Not a LoRa Gateway Spec message
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#define MGT_SET_SF 0x16
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#define MGT_SET_FREQ 0x17
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