kopia lustrzana https://github.com/skuep/AIOC
350 wiersze
21 KiB
C
350 wiersze
21 KiB
C
#ifndef SETTINGS_H_
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#define SETTINGS_H_
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#include <stdint.h>
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#include "usb_descriptors.h"
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#define SETTINGS_REGMAP_SIZE 256
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#define SETTINGS_REGMAP_READONLYADDR 0xC0
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extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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/* Magic number register. Mainly used to see if flash data is valid */
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#define SETTINGS_REG_MAGIC 0x00
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#define SETTINGS_REG_MAGIC_DEFAULT ( (((uint32_t) 'A') << 0) | \
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(((uint32_t) 'I') << 8) | \
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(((uint32_t) 'O') << 16) | \
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(((uint32_t) 'C') << 24) )
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/* USB ID register. The default USB VID and PID can be overwritten. Use with caution */
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#define SETTINGS_REG_USBID 0x08
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#define SETTINGS_REG_USBID_DEFAULT (SETTINGS_REG_USBID_VID_DFLT | SETTINGS_REG_USBID_PID_DFLT)
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/* VID: USB Vendor Id */
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#define SETTINGS_REG_USBID_VID_DFLT ((uint32_t) USB_VID << SETTINGS_REG_USBID_VID_OFFS)
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#define SETTINGS_REG_USBID_VID_OFFS 0
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#define SETTINGS_REG_USBID_VID_MASK 0x0000FFFFUL
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/* PID: USB Product Id */
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#define SETTINGS_REG_USBID_PID_DFLT ((uint32_t) USB_PID << SETTINGS_REG_USBID_PID_OFFS)
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#define SETTINGS_REG_USBID_PID_OFFS 16
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#define SETTINGS_REG_USBID_PID_MASK 0xFFFF0000UL
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/* AIOC IOMUX0 register */
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#define SETTINGS_REG_AIOC_IOMUX0 0x24
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#define SETTINGS_REG_AIOC_IOMUX0_DEFAULT (SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_DFLT)
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/* OUT1SRC: Source for OUT1 signal */
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_DFLT (SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO3_MASK | SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALDTRNRTS_MASK)
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_OFFS 0
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_MASK 0xFFFFFFFFUL
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_NONE_MASK 0x00000000UL
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO1_MASK 0x00000001UL
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO2_MASK 0x00000002UL
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO3_MASK 0x00000004UL
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO4_MASK 0x00000008UL
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALDTR_MASK 0x00000100UL
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALRTS_MASK 0x00000200UL
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALDTRNRTS_MASK 0x00000400UL
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALNDTRRTS_MASK 0x00000800UL
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#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_VPTT_MASK 0x00001000UL
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/* AIOC IOMUX1 register */
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#define SETTINGS_REG_AIOC_IOMUX1 0x25
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#define SETTINGS_REG_AIOC_IOMUX1_DEFAULT (SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_DFLT)
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/* OUT2SRC: Source for OUT2 signal */
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_DFLT (SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_CM108GPIO4_MASK)
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_OFFS SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_OFFS
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_NONE_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_NONE_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_CM108GPIO1_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO1_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_CM108GPIO2_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO2_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_CM108GPIO3_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO3_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_CM108GPIO4_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO4_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_SERIALDTR_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALDTR_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_SERIALRTS_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALRTS_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_SERIALDTRNRTS_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALDTRNRTS_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_SERIALNDTRRTS_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALNDTRRTS_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_VPTT_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_VPTT_MASK
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/* CM108 IOMUX0 register */
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#define SETTINGS_REG_CM108_IOMUX0 0x44
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#define SETTINGS_REG_CM108_IOMUX0_DEFAULT (SETTINGS_REG_CM108_IOMUX0_BTN1SRC_DFLT)
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/* BTN1SRC: Volume-Up Button source */
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#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_DFLT (SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK)
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#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_OFFS 0
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#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_MASK 0xFFFFFFFFUL
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#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_NONE_MASK 0x00000000UL
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#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK 0x00010000UL /* AIOC's IN1 */
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#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK 0x00020000UL /* AIOC's IN2 */
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#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK 0x01000000UL /* Virtual COS */
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/* CM108 IOMUX1 register */
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#define SETTINGS_REG_CM108_IOMUX1 0x45
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#define SETTINGS_REG_CM108_IOMUX1_DEFAULT (SETTINGS_REG_CM108_IOMUX1_BTN2SRC_DFLT)
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/* BTN2SRC: Volume-Down Button source */
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#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_DFLT (SETTINGS_REG_CM108_IOMUX1_BTN2SRC_VCOS_MASK)
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#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_OFFS SETTINGS_REG_CM108_IOMUX0_BTN1SRC_OFFS
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#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_MASK
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#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_NONE_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_NONE_MASK
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#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_IN1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK
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#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_IN2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK
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#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_VCOS_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK
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/* CM108 IOMUX2 register */
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#define SETTINGS_REG_CM108_IOMUX2 0x46
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#define SETTINGS_REG_CM108_IOMUX2_DEFAULT (SETTINGS_REG_CM108_IOMUX2_BTN3SRC_DFLT)
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/* BTN3SRC: Playback-Mute Button source */
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#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_DFLT (SETTINGS_REG_CM108_IOMUX2_BTN3SRC_NONE_MASK)
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#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_OFFS SETTINGS_REG_CM108_IOMUX0_BTN1SRC_OFFS
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#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_MASK
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#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_NONE_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_NONE_MASK
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#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_IN1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK
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#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_IN2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK
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#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_VCOS_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK
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/* CM108 IOMUX3 register */
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#define SETTINGS_REG_CM108_IOMUX3 0x47
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#define SETTINGS_REG_CM108_IOMUX3_DEFAULT (SETTINGS_REG_CM108_IOMUX3_BTN4SRC_DFLT)
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/* BTN4SRC: Record-Mute Button source */
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#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_DFLT (SETTINGS_REG_CM108_IOMUX3_BTN4SRC_NONE_MASK)
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#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_OFFS SETTINGS_REG_CM108_IOMUX0_BTN1SRC_OFFS
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#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_MASK
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#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_NONE_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_NONE_MASK
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#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_IN1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK
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#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_IN2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK
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#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_VCOS_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK
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/* Serial (CDC) Control register */
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#define SETTINGS_REG_SERIAL_CTRL 0x60
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#define SETTINGS_REG_SERIAL_CTRL_DEFAULT (SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_DFLT | SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_DFLT)
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/* TXFRCPTT: Forces PTT signal(s) to zero when transmitting serial data to radio if enabled */
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_DFLT (SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_PTT1_MASK)
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_OFFS 8
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_MASK 0x00000F00UL
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_NONE_MASK 0x00000000UL
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_PTT1_MASK 0x00000100UL
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_PTT2_MASK 0x00000200UL
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/* RXIGNPTT: Ignores reception of data from radio when PTT signal(s) asserted if enabled */
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_DFLT (SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_PTT1_MASK)
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_OFFS 16
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_MASK 0x000F0000UL
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_NONE_MASK 0x00000000UL
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_PTT1_MASK 0x00010000UL
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_PTT2_MASK 0x00020000UL
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/* Serial (CDC) IOMUX0 register */
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#define SETTINGS_REG_SERIAL_IOMUX0 0x64
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#define SETTINGS_REG_SERIAL_IOMUX0_DEFAULT (SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_DFLT)
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/* DCDSRC: DCD (Data Carrier Detect) signal source */
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#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_DFLT (SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK)
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#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_OFFS SETTINGS_REG_CM108_IOMUX0_BTN1SRC_OFFS
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#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_MASK
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#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_NONE_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_NONE_MASK
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#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK
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#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK
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#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK
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/* Serial (CDC) IOMUX1 register */
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#define SETTINGS_REG_SERIAL_IOMUX1 0x65
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#define SETTINGS_REG_SERIAL_IOMUX1_DEFAULT (SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_DFLT)
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/* DSRSRC: DSR (Data Set Ready) signal source */
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#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_DFLT (SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_NONE_MASK)
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#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_OFFS SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_OFFS
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#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_MASK
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#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_NONE_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_NONE_MASK
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#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_IN1_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN1_MASK
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#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_IN2_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN2_MASK
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#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_VCOS_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK
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/* Serial (CDC) IOMUX2 register */
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#define SETTINGS_REG_SERIAL_IOMUX2 0x66
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#define SETTINGS_REG_SERIAL_IOMUX2_DEFAULT (SETTINGS_REG_SERIAL_IOMUX2_RISRC_DFLT)
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/* RISRC: RI (Ring Indicator) signal source */
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#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_DFLT (SETTINGS_REG_SERIAL_IOMUX2_RISRC_NONE_MASK)
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#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_OFFS SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_OFFS
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#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_MASK
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#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_NONE_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_NONE_MASK
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#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_IN1_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN1_MASK
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#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_IN2_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN2_MASK
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#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_VCOS_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK
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/* Serial (CDC) IOMUX3 register */
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#define SETTINGS_REG_SERIAL_IOMUX3 0x67
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#define SETTINGS_REG_SERIAL_IOMUX3_DEFAULT (SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_DFLT)
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/* BRKSRC: BREAK (Break) signal source */
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#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_DFLT (SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_NONE_MASK)
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#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_OFFS SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_OFFS
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#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_MASK
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#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_NONE_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_NONE_MASK
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#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_IN1_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN1_MASK
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#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_IN2_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN2_MASK
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#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_VCOS_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK
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/* Virtual PTT level control register */
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#define SETTINGS_REG_VPTT_LVLCTRL 0x82
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#define SETTINGS_REG_VPTT_LVLCTRL_DEFAULT (SETTINGS_REG_VPTT_LVLCTRL_THRSHLD_DFLT)
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/* THRSHLD: Virtual PTT threshold level */
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#define SETTINGS_REG_VPTT_LVLCTRL_THRSHLD_DFLT ((uint32_t) 16 << SETTINGS_REG_VPTT_LVLCTRL_THRSHLD_OFFS)
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#define SETTINGS_REG_VPTT_LVLCTRL_THRSHLD_OFFS 0
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#define SETTINGS_REG_VPTT_LVLCTRL_THRSHLD_MASK 0x0000FFFFUL
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/* Virtual PTT timing control register */
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#define SETTINGS_REG_VPTT_TIMCTRL 0x84
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#define SETTINGS_REG_VPTT_TIMCTRL_DEFAULT (SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_DFLT)
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/* TIMEOUT: Timeout (trailing) time in milliseconds in 12.4 format */
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#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_DFLT ((uint32_t) (20 << 4) << SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS)
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#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS 0
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#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_MASK 0xFFFFFFFFUL
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/* Virtual COS level control register */
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#define SETTINGS_REG_VCOS_LVLCTRL 0x92
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#define SETTINGS_REG_VCOS_LVLCTRL_DEFAULT (SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_DFLT)
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/* THRSHLD: Virtual COS threshold level */
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#define SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_DFLT ((uint32_t) 256 << SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_OFFS)
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#define SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_OFFS 0
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#define SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_MASK 0x0000FFFFUL
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/* Virtual COS timing control register */
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#define SETTINGS_REG_VCOS_TIMCTRL 0x94
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#define SETTINGS_REG_VCOS_TIMCTRL_DEFAULT (SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_DFLT)
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/* TIMEOUT: Timeout (trailing) time in milliseconds in 12.4 format */
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#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_DFLT ((uint32_t) (200 << 4) << SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_OFFS)
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#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_OFFS 0
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#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_MASK 0x0000FFFFUL
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/* AIOC debug register 0 */
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#define SETTINGS_REG_INFO_AIOC0 0xC0
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#define SETTINGS_REG_INFO_AIOC0_DEFAULT 0
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/* Various digital signal states */
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#define SETTINGS_REG_INFO_AIOC0_PTT1STATE_MASK 0x00010000UL
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#define SETTINGS_REG_INFO_AIOC0_PTT2STATE_MASK 0x00020000UL
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/* UAC audio debug register 0 */
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#define SETTINGS_REG_INFO_AUDIO0 0xD0
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#define SETTINGS_REG_INFO_AUDIO0_DEFAULT 0
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/* Playback or recording muted (master and first channel) */
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#define SETTINGS_REG_INFO_AUDIO0_RECMUTE0_MASK 0x00010000UL
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#define SETTINGS_REG_INFO_AUDIO0_RECMUTE1_MASK 0x00020000UL
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#define SETTINGS_REG_INFO_AUDIO0_PLAYMUTE0_MASK 0x00100000UL
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#define SETTINGS_REG_INFO_AUDIO0_PLAYMUTE1_MASK 0x00200000UL
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/* Virtual PTT and COS states */
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#define SETTINGS_REG_INFO_AIOC0_VPTTSTATE_MASK 0x01000000UL
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#define SETTINGS_REG_INFO_AIOC0_VCOSSTATE_MASK 0x10000000UL
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/* Playback and recording state */
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#define SETTINGS_REG_INFO_AUDIO0_RECSTATE_OFFS 24
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#define SETTINGS_REG_INFO_AUDIO0_RECSTATE_MASK 0x0F000000UL
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#define SETTINGS_REG_INFO_AUDIO0_RECSTATE_OFF_ENUM 0
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#define SETTINGS_REG_INFO_AUDIO0_RECSTATE_START_ENUM 1
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#define SETTINGS_REG_INFO_AUDIO0_RECSTATE_RUN_ENUM 2
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#define SETTINGS_REG_INFO_AUDIO0_PLAYSTATE_OFFS 28
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#define SETTINGS_REG_INFO_AUDIO0_PLAYSTATE_MASK 0xF0000000UL
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#define SETTINGS_REG_INFO_AUDIO0_PLAYSTATE_OFF_ENUM 0
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#define SETTINGS_REG_INFO_AUDIO0_PLAYSTATE_START_ENUM 1
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#define SETTINGS_REG_INFO_AUDIO0_PLAYSTATE_RUN_ENUM 2
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/* Audio debug register 1 */
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#define SETTINGS_REG_INFO_AUDIO1 0xD1
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#define SETTINGS_REG_INFO_AUDIO1_DEFAULT 0
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/* Audio debug register 2 */
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#define SETTINGS_REG_INFO_AUDIO2 0xD2
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#define SETTINGS_REG_INFO_AUDIO2_DEFAULT 0
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/* Recording samplerate */
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#define SETTINGS_REG_INFO_AUDIO2_RECRATE_OFFS 0
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#define SETTINGS_REG_INFO_AUDIO2_RECRATE_MASK 0xFFFFFFFFUL
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/* Audio debug register 3 */
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#define SETTINGS_REG_INFO_AUDIO3 0xD3
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#define SETTINGS_REG_INFO_AUDIO3_DEFAULT 0
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/* Recording volume (master and first channel) */
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#define SETTINGS_REG_INFO_AUDIO3_RECVOL0_OFFS 0
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#define SETTINGS_REG_INFO_AUDIO3_RECVOL0_MASK 0x0000FFFFUL
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#define SETTINGS_REG_INFO_AUDIO3_RECVOL1_OFFS 16
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#define SETTINGS_REG_INFO_AUDIO3_RECVOL1_MASK 0xFFFF0000UL
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/* TODO: D4, D5, D6 -> Recording buffer levels (avg/min/max) */
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/* Audio debug register 4 */
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#define SETTINGS_REG_INFO_AUDIO4 0xD4
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#define SETTINGS_REG_INFO_AUDIO4_DEFAULT 0
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/* Audio debug register 5 */
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#define SETTINGS_REG_INFO_AUDIO5 0xD5
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#define SETTINGS_REG_INFO_AUDIO5_DEFAULT 0
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/* Audio debug register 6 */
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#define SETTINGS_REG_INFO_AUDIO6 0xD6
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#define SETTINGS_REG_INFO_AUDIO6_DEFAULT 0
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/* Audio debug register 7 */
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#define SETTINGS_REG_INFO_AUDIO7 0xD7
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#define SETTINGS_REG_INFO_AUDIO7_DEFAULT 0
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/* Audio debug register 8 */
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#define SETTINGS_REG_INFO_AUDIO8 0xD8
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#define SETTINGS_REG_INFO_AUDIO8_DEFAULT 0
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/* Playback samplerate */
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#define SETTINGS_REG_INFO_AUDIO8_PLAYRATE_OFFS 0
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#define SETTINGS_REG_INFO_AUDIO8_PLAYRATE_MASK 0xFFFFFFFFUL
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/* Audio debug register 9 */
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#define SETTINGS_REG_INFO_AUDIO9 0xD9
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#define SETTINGS_REG_INFO_AUDIO9_DEFAULT 0
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/* Playback volume (master and first channel) */
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#define SETTINGS_REG_INFO_AUDIO9_PLAYVOL0_OFFS 0
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#define SETTINGS_REG_INFO_AUDIO9_PLAYVOL0_MASK 0x0000FFFFUL
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#define SETTINGS_REG_INFO_AUDIO9_PLAYVOL1_OFFS 16
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#define SETTINGS_REG_INFO_AUDIO9_PLAYVOL1_MASK 0xFFFF0000UL
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/* Audio debug register 10 */
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#define SETTINGS_REG_INFO_AUDIO10 0xDA
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#define SETTINGS_REG_INFO_AUDIO10_DEFAULT 0
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/* Average playback buffer level */
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#define SETTINGS_REG_INFO_AUDIO10_PLAYBUFAVG_OFFS 0
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#define SETTINGS_REG_INFO_AUDIO10_PLAYBUFAVG_MASK 0x0000FFFFUL
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/* Audio debug register 11 */
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#define SETTINGS_REG_INFO_AUDIO11 0xDB
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#define SETTINGS_REG_INFO_AUDIO11_DEFAULT 0
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/* Minimum playback buffer level */
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#define SETTINGS_REG_INFO_AUDIO11_PLAYBUFMIN_OFFS 0
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#define SETTINGS_REG_INFO_AUDIO11_PLAYBUFMIN_MASK 0x0000FFFFUL
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/* Audio debug register 12 */
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#define SETTINGS_REG_INFO_AUDIO12 0xDC
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#define SETTINGS_REG_INFO_AUDIO12_DEFAULT 0
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/* Maximum playback buffer level */
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#define SETTINGS_REG_INFO_AUDIO12_PLAYBUFMAX_OFFS 0
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#define SETTINGS_REG_INFO_AUDIO12_PLAYBUFMAX_MASK 0x0000FFFFUL
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/* Audio debug register 13 */
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#define SETTINGS_REG_INFO_AUDIO13 0xDD
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#define SETTINGS_REG_INFO_AUDIO13_DEFAULT 0
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/* Average UAC2.0 Feedback Value since last playback */
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#define SETTINGS_REG_INFO_AUDIO13_PLAYFBAVG_OFFS 0
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#define SETTINGS_REG_INFO_AUDIO13_PLAYFBAVG_MASK 0xFFFFFFFFUL
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/* Audio debug register 14 */
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#define SETTINGS_REG_INFO_AUDIO14 0xDE
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#define SETTINGS_REG_INFO_AUDIO14_DEFAULT 0
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/* Minimum UAC2.0 Feedback Value since last playback */
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#define SETTINGS_REG_INFO_AUDIO14_PLAYFBMIN_OFFS 0
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#define SETTINGS_REG_INFO_AUDIO14_PLAYFBMIN_MASK 0xFFFFFFFFUL
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/* Audio debug register 15 */
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#define SETTINGS_REG_INFO_AUDIO15 0xDF
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#define SETTINGS_REG_INFO_AUDIO15_DEFAULT 0
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/* Maximum UAC2.0 Feedback Value since last playback */
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#define SETTINGS_REG_INFO_AUDIO15_PLAYFBMAX_OFFS 0
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#define SETTINGS_REG_INFO_AUDIO15_PLAYFBMAX_MASK 0xFFFFFFFFUL
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void Settings_Init();
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uint8_t Settings_RegWrite(uint8_t address, uint32_t data);
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uint8_t Settings_RegRead(uint8_t address, uint32_t * data);
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void Settings_Store(void);
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void Settings_Recall(void);
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void Settings_Default(void);
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#endif /* SETTINGS_H_ */
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